1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Novena video output support
4 *
5 * IT6251 code based on code Copyright (C) 2014 Sean Cross
6 * from https://github.com/xobs/novena-linux.git commit
7 * 3d85836ee1377d445531928361809612aa0a18db
8 *
9 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
10 */
11
12 #include <common.h>
13 #include <log.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/iomux.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/mach-imx/iomux-v3.h>
25 #include <asm/mach-imx/mxc_i2c.h>
26 #include <asm/mach-imx/video.h>
27 #include <i2c.h>
28 #include <input.h>
29 #include <ipu_pixfmt.h>
30 #include <linux/fb.h>
31 #include <linux/input.h>
32 #include <malloc.h>
33 #include <stdio_dev.h>
34
35 #include "novena.h"
36
37 #define IT6251_VENDOR_ID_LOW 0x00
38 #define IT6251_VENDOR_ID_HIGH 0x01
39 #define IT6251_DEVICE_ID_LOW 0x02
40 #define IT6251_DEVICE_ID_HIGH 0x03
41 #define IT6251_SYSTEM_STATUS 0x0d
42 #define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0)
43 #define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1)
44 #define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2)
45 #define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3)
46 #define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4)
47 #define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5)
48 #define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6)
49 #define IT6251_REF_STATE 0x0e
50 #define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0)
51 #define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1)
52 #define IT6251_REF_STATE_CR_PATTERN (1 << 2)
53 #define IT6251_REF_STATE_EQ_PATTERN (1 << 3)
54 #define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4)
55 #define IT6251_REF_STATE_MUTED (1 << 5)
56
57 #define IT6251_REG_PCLK_CNT_LOW 0x57
58 #define IT6251_REG_PCLK_CNT_HIGH 0x58
59
60 #define IT6521_RETRY_MAX 20
61
it6251_is_stable(void)62 static int it6251_is_stable(void)
63 {
64 const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
65 const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
66 int status;
67 int clkcnt;
68 int rpclkcnt;
69 int refstate;
70
71 rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
72 ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
73 debug("RPCLKCnt: %d\n", rpclkcnt);
74
75 status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
76 debug("System status: 0x%02x\n", status);
77
78 clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
79 ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
80 0x0f00);
81 debug("Clock: 0x%02x\n", clkcnt);
82
83 refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
84 debug("Ref Link State: 0x%02x\n", refstate);
85
86 if ((refstate & 0x1f) != 0)
87 return 0;
88
89 /* If video is muted, that's a failure */
90 if (refstate & IT6251_REF_STATE_MUTED)
91 return 0;
92
93 if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
94 return 0;
95
96 return 1;
97 }
98
it6251_ready(void)99 static int it6251_ready(void)
100 {
101 const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
102
103 /* Test if the IT6251 came out of reset by reading ID regs. */
104 if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
105 return 0;
106 if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
107 return 0;
108 if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
109 return 0;
110 if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
111 return 0;
112
113 return 1;
114 }
115
it6251_program_regs(void)116 static void it6251_program_regs(void)
117 {
118 const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
119 const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
120
121 i2c_reg_write(caddr, 0x05, 0x00);
122 mdelay(1);
123
124 /* set LVDSRX address, and enable */
125 i2c_reg_write(caddr, 0xfd, 0xbc);
126 i2c_reg_write(caddr, 0xfe, 0x01);
127
128 /*
129 * LVDSRX
130 */
131 /* This write always fails, because the chip goes into reset */
132 /* reset LVDSRX */
133 i2c_reg_write(laddr, 0x05, 0xff);
134 i2c_reg_write(laddr, 0x05, 0x00);
135
136 /* reset LVDSRX PLL */
137 i2c_reg_write(laddr, 0x3b, 0x42);
138 i2c_reg_write(laddr, 0x3b, 0x43);
139
140 /* something with SSC PLL */
141 i2c_reg_write(laddr, 0x3c, 0x08);
142 /* don't swap links, but writing reserved registers */
143 i2c_reg_write(laddr, 0x0b, 0x88);
144
145 /* JEIDA, 8-bit depth 0x11, orig 0x42 */
146 i2c_reg_write(laddr, 0x2c, 0x01);
147 /* "reserved" */
148 i2c_reg_write(laddr, 0x32, 0x04);
149 /* "reserved" */
150 i2c_reg_write(laddr, 0x35, 0xe0);
151 /* "reserved" + clock delay */
152 i2c_reg_write(laddr, 0x2b, 0x24);
153
154 /* reset LVDSRX pix clock */
155 i2c_reg_write(laddr, 0x05, 0x02);
156 i2c_reg_write(laddr, 0x05, 0x00);
157
158 /*
159 * DPTX
160 */
161 /* set for two lane mode, normal op, no swapping, no downspread */
162 i2c_reg_write(caddr, 0x16, 0x02);
163
164 /* some AUX channel EDID magic */
165 i2c_reg_write(caddr, 0x23, 0x40);
166
167 /* power down lanes 3-0 */
168 i2c_reg_write(caddr, 0x5c, 0xf3);
169
170 /* enable DP scrambling, change EQ CR phase */
171 i2c_reg_write(caddr, 0x5f, 0x06);
172
173 /* color mode RGB, pclk/2 */
174 i2c_reg_write(caddr, 0x60, 0x02);
175 /* dual pixel input mode, no EO swap, no RGB swap */
176 i2c_reg_write(caddr, 0x61, 0x04);
177 /* M444B24 video format */
178 i2c_reg_write(caddr, 0x62, 0x01);
179
180 /* vesa range / not interlace / vsync high / hsync high */
181 i2c_reg_write(caddr, 0xa0, 0x0F);
182
183 /* hpd event timer set to 1.6-ish ms */
184 i2c_reg_write(caddr, 0xc9, 0xf5);
185
186 /* more reserved magic */
187 i2c_reg_write(caddr, 0xca, 0x4d);
188 i2c_reg_write(caddr, 0xcb, 0x37);
189
190 /* enhanced framing mode, auto video fifo reset, video mute disable */
191 i2c_reg_write(caddr, 0xd3, 0x03);
192
193 /* "vidstmp" and some reserved stuff */
194 i2c_reg_write(caddr, 0xd4, 0x45);
195
196 /* queue number -- reserved */
197 i2c_reg_write(caddr, 0xe7, 0xa0);
198 /* info frame packets and reserved */
199 i2c_reg_write(caddr, 0xe8, 0x33);
200 /* more AVI stuff */
201 i2c_reg_write(caddr, 0xec, 0x00);
202
203 /* select PC master reg for aux channel? */
204 i2c_reg_write(caddr, 0x23, 0x42);
205
206 /* send PC request commands */
207 i2c_reg_write(caddr, 0x24, 0x00);
208 i2c_reg_write(caddr, 0x25, 0x00);
209 i2c_reg_write(caddr, 0x26, 0x00);
210
211 /* native aux read */
212 i2c_reg_write(caddr, 0x2b, 0x00);
213 /* back to internal */
214 i2c_reg_write(caddr, 0x23, 0x40);
215
216 /* voltage swing level 3 */
217 i2c_reg_write(caddr, 0x19, 0xff);
218 /* pre-emphasis level 3 */
219 i2c_reg_write(caddr, 0x1a, 0xff);
220
221 /* start link training */
222 i2c_reg_write(caddr, 0x17, 0x01);
223 }
224
it6251_init(void)225 static int it6251_init(void)
226 {
227 const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
228 int reg;
229 int tries, retries = 0;
230
231 for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
232 /* Program the chip. */
233 it6251_program_regs();
234
235 /* Wait for video stable. */
236 for (tries = 0; tries < 100; tries++) {
237 reg = i2c_reg_read(caddr, 0x17);
238 /* Test Link CFG, STS, LCS read done. */
239 if ((reg & 0xe0) != 0xe0) {
240 /* Not yet, wait a bit more. */
241 mdelay(2);
242 continue;
243 }
244
245 /* Test if the video input is stable. */
246 if (it6251_is_stable())
247 return 0;
248 }
249 /*
250 * If we couldn't stabilize, requeue and try again,
251 * because it means that the LVDS channel isn't
252 * stable yet.
253 */
254 printf("Display didn't stabilize.\n");
255 printf("This may be because the LVDS port is still in powersave mode.\n");
256 mdelay(50);
257 }
258
259 return -EINVAL;
260 }
261
enable_hdmi(struct display_info_t const * dev)262 static void enable_hdmi(struct display_info_t const *dev)
263 {
264 imx_enable_hdmi_phy();
265 }
266
267 static int lvds_enabled;
268
enable_lvds(struct display_info_t const * dev)269 static void enable_lvds(struct display_info_t const *dev)
270 {
271 if (lvds_enabled)
272 return;
273
274 /* ITE IT6251 power enable. */
275 gpio_request(NOVENA_ITE6251_PWR_GPIO, "ite6251-power");
276 gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
277 mdelay(10);
278 gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
279 mdelay(20);
280 lvds_enabled = 1;
281 }
282
detect_lvds(struct display_info_t const * dev)283 static int detect_lvds(struct display_info_t const *dev)
284 {
285 int ret, loops = 250;
286
287 enable_lvds(dev);
288
289 ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
290 if (ret) {
291 puts("Cannot select IT6251 I2C bus.\n");
292 return 0;
293 }
294
295 /* Wait up-to ~250 mS for the LVDS to come up. */
296 while (--loops) {
297 ret = it6251_ready();
298 if (ret)
299 return ret;
300
301 mdelay(1);
302 }
303
304 return 0;
305 }
306
307 struct display_info_t const displays[] = {
308 {
309 /* HDMI Output */
310 .bus = -1,
311 .addr = 0,
312 .pixfmt = IPU_PIX_FMT_RGB24,
313 .detect = detect_hdmi,
314 .enable = enable_hdmi,
315 .mode = {
316 .name = "HDMI",
317 .refresh = 60,
318 .xres = 1024,
319 .yres = 768,
320 .pixclock = 15384,
321 .left_margin = 220,
322 .right_margin = 40,
323 .upper_margin = 21,
324 .lower_margin = 7,
325 .hsync_len = 60,
326 .vsync_len = 10,
327 .sync = FB_SYNC_EXT,
328 .vmode = FB_VMODE_NONINTERLACED
329 },
330 }, {
331 /* LVDS Output: N133HSE-EA1 Rev. C1 */
332 .bus = -1,
333 .pixfmt = IPU_PIX_FMT_RGB24,
334 .detect = detect_lvds,
335 .enable = enable_lvds,
336 .mode = {
337 .name = "Chimei-FHD",
338 .refresh = 60,
339 .xres = 1920,
340 .yres = 1080,
341 .pixclock = 15384,
342 .left_margin = 148,
343 .right_margin = 88,
344 .upper_margin = 36,
345 .lower_margin = 4,
346 .hsync_len = 44,
347 .vsync_len = 5,
348 .sync = FB_SYNC_HOR_HIGH_ACT |
349 FB_SYNC_VERT_HIGH_ACT |
350 FB_SYNC_EXT,
351 .vmode = FB_VMODE_NONINTERLACED,
352 },
353 },
354 };
355
356 size_t display_count = ARRAY_SIZE(displays);
357
enable_vpll(void)358 static void enable_vpll(void)
359 {
360 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
361 int timeout = 100000;
362
363 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
364
365 clrsetbits_le32(&ccm->analog_pll_video,
366 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
367 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
368 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
369 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
370
371 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
372 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
373
374 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
375
376 while (timeout--)
377 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
378 break;
379 if (timeout < 0)
380 printf("Warning: video pll lock timeout!\n");
381
382 clrsetbits_le32(&ccm->analog_pll_video,
383 BM_ANADIG_PLL_VIDEO_BYPASS,
384 BM_ANADIG_PLL_VIDEO_ENABLE);
385 }
386
setup_display_clock(void)387 void setup_display_clock(void)
388 {
389 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
390 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
391
392 enable_ipu_clock();
393 enable_vpll();
394 imx_setup_hdmi();
395
396 /* Turn on IPU LDB DI0 clocks */
397 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
398
399 /* Switch LDB DI0 to PLL5 (Video PLL) */
400 clrsetbits_le32(&mxc_ccm->cs2cdr,
401 MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
402 (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
403
404 /* LDB clock div by 3.5 */
405 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
406
407 /* DI0 clock derived from ldb_di0_clk */
408 clrsetbits_le32(&mxc_ccm->chsccdr,
409 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
410 (CHSCCDR_CLK_SEL_LDB_DI0 <<
411 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
412 );
413
414 /* Enable both LVDS channels, both connected to DI0. */
415 writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
416 IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
417 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
418 IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
419 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
420 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
421 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
422 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
423 &iomux->gpr[2]);
424
425 clrsetbits_le32(&iomux->gpr[3],
426 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
427 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
428 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
429 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
430 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
431 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
432 );
433 }
434
setup_display_lvds(void)435 void setup_display_lvds(void)
436 {
437 int ret;
438
439 ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
440 if (ret) {
441 puts("Cannot select LVDS-to-eDP I2C bus.\n");
442 return;
443 }
444
445 /* The IT6251 should be ready now, if it's not, it's not connected. */
446 ret = it6251_ready();
447 if (!ret)
448 return;
449
450 /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
451 ret = it6251_init();
452 if (!ret) {
453 gpio_request(NOVENA_BACKLIGHT_PWR_GPIO, "backlight-power");
454 gpio_request(NOVENA_BACKLIGHT_PWM_GPIO, "backlight-pwm");
455 /* Backlight power enable. */
456 gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
457 /* PWM backlight pin, always on for full brightness. */
458 gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
459 }
460 }
461