1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L1
24
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_smu.h"
30 #include "smu_internal.h"
31 #include "atom.h"
32 #include "arcturus_ppt.h"
33 #include "navi10_ppt.h"
34 #include "sienna_cichlid_ppt.h"
35 #include "renoir_ppt.h"
36 #include "vangogh_ppt.h"
37 #include "aldebaran_ppt.h"
38 #include "yellow_carp_ppt.h"
39 #include "cyan_skillfish_ppt.h"
40 #include "amd_pcie.h"
41
42 /*
43 * DO NOT use these for err/warn/info/debug messages.
44 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
45 * They are more MGPU friendly.
46 */
47 #undef pr_err
48 #undef pr_warn
49 #undef pr_info
50 #undef pr_debug
51
52 static const struct amd_pm_funcs swsmu_pm_funcs;
53 static int smu_force_smuclk_levels(struct smu_context *smu,
54 enum smu_clk_type clk_type,
55 uint32_t mask);
56 static int smu_handle_task(struct smu_context *smu,
57 enum amd_dpm_forced_level level,
58 enum amd_pp_task task_id,
59 bool lock_needed);
60 static int smu_reset(struct smu_context *smu);
61 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
62 static int smu_set_fan_control_mode(struct smu_context *smu, int value);
63 static int smu_set_power_limit(void *handle, uint32_t limit);
64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
66
smu_sys_get_pp_feature_mask(void * handle,char * buf)67 static int smu_sys_get_pp_feature_mask(void *handle,
68 char *buf)
69 {
70 struct smu_context *smu = handle;
71 int size = 0;
72
73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
74 return -EOPNOTSUPP;
75
76 mutex_lock(&smu->mutex);
77
78 size = smu_get_pp_feature_mask(smu, buf);
79
80 mutex_unlock(&smu->mutex);
81
82 return size;
83 }
84
smu_sys_set_pp_feature_mask(void * handle,uint64_t new_mask)85 static int smu_sys_set_pp_feature_mask(void *handle,
86 uint64_t new_mask)
87 {
88 struct smu_context *smu = handle;
89 int ret = 0;
90
91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
92 return -EOPNOTSUPP;
93
94 mutex_lock(&smu->mutex);
95
96 ret = smu_set_pp_feature_mask(smu, new_mask);
97
98 mutex_unlock(&smu->mutex);
99
100 return ret;
101 }
102
smu_get_status_gfxoff(struct amdgpu_device * adev,uint32_t * value)103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
104 {
105 int ret = 0;
106 struct smu_context *smu = &adev->smu;
107
108 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
109 *value = smu_get_gfx_off_status(smu);
110 else
111 ret = -EINVAL;
112
113 return ret;
114 }
115
smu_set_soft_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)116 int smu_set_soft_freq_range(struct smu_context *smu,
117 enum smu_clk_type clk_type,
118 uint32_t min,
119 uint32_t max)
120 {
121 int ret = 0;
122
123 mutex_lock(&smu->mutex);
124
125 if (smu->ppt_funcs->set_soft_freq_limited_range)
126 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
127 clk_type,
128 min,
129 max);
130
131 mutex_unlock(&smu->mutex);
132
133 return ret;
134 }
135
smu_get_dpm_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)136 int smu_get_dpm_freq_range(struct smu_context *smu,
137 enum smu_clk_type clk_type,
138 uint32_t *min,
139 uint32_t *max)
140 {
141 int ret = 0;
142
143 if (!min && !max)
144 return -EINVAL;
145
146 mutex_lock(&smu->mutex);
147
148 if (smu->ppt_funcs->get_dpm_ultimate_freq)
149 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
150 clk_type,
151 min,
152 max);
153
154 mutex_unlock(&smu->mutex);
155
156 return ret;
157 }
158
smu_get_mclk(void * handle,bool low)159 static u32 smu_get_mclk(void *handle, bool low)
160 {
161 struct smu_context *smu = handle;
162 uint32_t clk_freq;
163 int ret = 0;
164
165 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
166 low ? &clk_freq : NULL,
167 !low ? &clk_freq : NULL);
168 if (ret)
169 return 0;
170 return clk_freq * 100;
171 }
172
smu_get_sclk(void * handle,bool low)173 static u32 smu_get_sclk(void *handle, bool low)
174 {
175 struct smu_context *smu = handle;
176 uint32_t clk_freq;
177 int ret = 0;
178
179 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
180 low ? &clk_freq : NULL,
181 !low ? &clk_freq : NULL);
182 if (ret)
183 return 0;
184 return clk_freq * 100;
185 }
186
smu_dpm_set_vcn_enable_locked(struct smu_context * smu,bool enable)187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
188 bool enable)
189 {
190 struct smu_power_context *smu_power = &smu->smu_power;
191 struct smu_power_gate *power_gate = &smu_power->power_gate;
192 int ret = 0;
193
194 if (!smu->ppt_funcs->dpm_set_vcn_enable)
195 return 0;
196
197 if (atomic_read(&power_gate->vcn_gated) ^ enable)
198 return 0;
199
200 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
201 if (!ret)
202 atomic_set(&power_gate->vcn_gated, !enable);
203
204 return ret;
205 }
206
smu_dpm_set_vcn_enable(struct smu_context * smu,bool enable)207 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
208 bool enable)
209 {
210 struct smu_power_context *smu_power = &smu->smu_power;
211 struct smu_power_gate *power_gate = &smu_power->power_gate;
212 int ret = 0;
213
214 mutex_lock(&power_gate->vcn_gate_lock);
215
216 ret = smu_dpm_set_vcn_enable_locked(smu, enable);
217
218 mutex_unlock(&power_gate->vcn_gate_lock);
219
220 return ret;
221 }
222
smu_dpm_set_jpeg_enable_locked(struct smu_context * smu,bool enable)223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
224 bool enable)
225 {
226 struct smu_power_context *smu_power = &smu->smu_power;
227 struct smu_power_gate *power_gate = &smu_power->power_gate;
228 int ret = 0;
229
230 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
231 return 0;
232
233 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
234 return 0;
235
236 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
237 if (!ret)
238 atomic_set(&power_gate->jpeg_gated, !enable);
239
240 return ret;
241 }
242
smu_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
244 bool enable)
245 {
246 struct smu_power_context *smu_power = &smu->smu_power;
247 struct smu_power_gate *power_gate = &smu_power->power_gate;
248 int ret = 0;
249
250 mutex_lock(&power_gate->jpeg_gate_lock);
251
252 ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
253
254 mutex_unlock(&power_gate->jpeg_gate_lock);
255
256 return ret;
257 }
258
259 /**
260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
261 *
262 * @handle: smu_context pointer
263 * @block_type: the IP block to power gate/ungate
264 * @gate: to power gate if true, ungate otherwise
265 *
266 * This API uses no smu->mutex lock protection due to:
267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
268 * This is guarded to be race condition free by the caller.
269 * 2. Or get called on user setting request of power_dpm_force_performance_level.
270 * Under this case, the smu->mutex lock protection is already enforced on
271 * the parent API smu_force_performance_level of the call path.
272 */
smu_dpm_set_power_gate(void * handle,uint32_t block_type,bool gate)273 static int smu_dpm_set_power_gate(void *handle,
274 uint32_t block_type,
275 bool gate)
276 {
277 struct smu_context *smu = handle;
278 int ret = 0;
279
280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
281 return -EOPNOTSUPP;
282
283 switch (block_type) {
284 /*
285 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
286 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
287 */
288 case AMD_IP_BLOCK_TYPE_UVD:
289 case AMD_IP_BLOCK_TYPE_VCN:
290 ret = smu_dpm_set_vcn_enable(smu, !gate);
291 if (ret)
292 dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
293 gate ? "gate" : "ungate");
294 break;
295 case AMD_IP_BLOCK_TYPE_GFX:
296 ret = smu_gfx_off_control(smu, gate);
297 if (ret)
298 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
299 gate ? "enable" : "disable");
300 break;
301 case AMD_IP_BLOCK_TYPE_SDMA:
302 ret = smu_powergate_sdma(smu, gate);
303 if (ret)
304 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
305 gate ? "gate" : "ungate");
306 break;
307 case AMD_IP_BLOCK_TYPE_JPEG:
308 ret = smu_dpm_set_jpeg_enable(smu, !gate);
309 if (ret)
310 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
311 gate ? "gate" : "ungate");
312 break;
313 default:
314 dev_err(smu->adev->dev, "Unsupported block type!\n");
315 return -EINVAL;
316 }
317
318 return ret;
319 }
320
321 /**
322 * smu_set_user_clk_dependencies - set user profile clock dependencies
323 *
324 * @smu: smu_context pointer
325 * @clk: enum smu_clk_type type
326 *
327 * Enable/Disable the clock dependency for the @clk type.
328 */
smu_set_user_clk_dependencies(struct smu_context * smu,enum smu_clk_type clk)329 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
330 {
331 if (smu->adev->in_suspend)
332 return;
333
334 if (clk == SMU_MCLK) {
335 smu->user_dpm_profile.clk_dependency = 0;
336 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
337 } else if (clk == SMU_FCLK) {
338 /* MCLK takes precedence over FCLK */
339 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
340 return;
341
342 smu->user_dpm_profile.clk_dependency = 0;
343 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
344 } else if (clk == SMU_SOCCLK) {
345 /* MCLK takes precedence over SOCCLK */
346 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
347 return;
348
349 smu->user_dpm_profile.clk_dependency = 0;
350 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
351 } else
352 /* Add clk dependencies here, if any */
353 return;
354 }
355
356 /**
357 * smu_restore_dpm_user_profile - reinstate user dpm profile
358 *
359 * @smu: smu_context pointer
360 *
361 * Restore the saved user power configurations include power limit,
362 * clock frequencies, fan control mode and fan speed.
363 */
smu_restore_dpm_user_profile(struct smu_context * smu)364 static void smu_restore_dpm_user_profile(struct smu_context *smu)
365 {
366 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
367 int ret = 0;
368
369 if (!smu->adev->in_suspend)
370 return;
371
372 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
373 return;
374
375 /* Enable restore flag */
376 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
377
378 /* set the user dpm power limit */
379 if (smu->user_dpm_profile.power_limit) {
380 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
381 if (ret)
382 dev_err(smu->adev->dev, "Failed to set power limit value\n");
383 }
384
385 /* set the user dpm clock configurations */
386 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
387 enum smu_clk_type clk_type;
388
389 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
390 /*
391 * Iterate over smu clk type and force the saved user clk
392 * configs, skip if clock dependency is enabled
393 */
394 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
395 smu->user_dpm_profile.clk_mask[clk_type]) {
396 ret = smu_force_smuclk_levels(smu, clk_type,
397 smu->user_dpm_profile.clk_mask[clk_type]);
398 if (ret)
399 dev_err(smu->adev->dev,
400 "Failed to set clock type = %d\n", clk_type);
401 }
402 }
403 }
404
405 /* set the user dpm fan configurations */
406 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
407 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
408 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
409 if (ret) {
410 smu->user_dpm_profile.fan_speed_pwm = 0;
411 smu->user_dpm_profile.fan_speed_rpm = 0;
412 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
413 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
414 }
415
416 if (smu->user_dpm_profile.fan_speed_pwm) {
417 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
418 if (ret)
419 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
420 }
421
422 if (smu->user_dpm_profile.fan_speed_rpm) {
423 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
424 if (ret)
425 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
426 }
427 }
428
429 /* Restore user customized OD settings */
430 if (smu->user_dpm_profile.user_od) {
431 if (smu->ppt_funcs->restore_user_od_settings) {
432 ret = smu->ppt_funcs->restore_user_od_settings(smu);
433 if (ret)
434 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
435 }
436 }
437
438 /* Disable restore flag */
439 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
440 }
441
smu_get_power_num_states(void * handle,struct pp_states_info * state_info)442 static int smu_get_power_num_states(void *handle,
443 struct pp_states_info *state_info)
444 {
445 if (!state_info)
446 return -EINVAL;
447
448 /* not support power state */
449 memset(state_info, 0, sizeof(struct pp_states_info));
450 state_info->nums = 1;
451 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
452
453 return 0;
454 }
455
is_support_sw_smu(struct amdgpu_device * adev)456 bool is_support_sw_smu(struct amdgpu_device *adev)
457 {
458 /* vega20 is 11.0.2, but it's supported via the powerplay code */
459 if (adev->asic_type == CHIP_VEGA20)
460 return false;
461
462 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
463 return true;
464
465 return false;
466 }
467
is_support_cclk_dpm(struct amdgpu_device * adev)468 bool is_support_cclk_dpm(struct amdgpu_device *adev)
469 {
470 struct smu_context *smu = &adev->smu;
471
472 if (!is_support_sw_smu(adev))
473 return false;
474
475 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
476 return false;
477
478 return true;
479 }
480
481
smu_sys_get_pp_table(void * handle,char ** table)482 static int smu_sys_get_pp_table(void *handle,
483 char **table)
484 {
485 struct smu_context *smu = handle;
486 struct smu_table_context *smu_table = &smu->smu_table;
487 uint32_t powerplay_table_size;
488
489 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
490 return -EOPNOTSUPP;
491
492 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
493 return -EINVAL;
494
495 mutex_lock(&smu->mutex);
496
497 if (smu_table->hardcode_pptable)
498 *table = smu_table->hardcode_pptable;
499 else
500 *table = smu_table->power_play_table;
501
502 powerplay_table_size = smu_table->power_play_table_size;
503
504 mutex_unlock(&smu->mutex);
505
506 return powerplay_table_size;
507 }
508
smu_sys_set_pp_table(void * handle,const char * buf,size_t size)509 static int smu_sys_set_pp_table(void *handle,
510 const char *buf,
511 size_t size)
512 {
513 struct smu_context *smu = handle;
514 struct smu_table_context *smu_table = &smu->smu_table;
515 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
516 int ret = 0;
517
518 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
519 return -EOPNOTSUPP;
520
521 if (header->usStructureSize != size) {
522 dev_err(smu->adev->dev, "pp table size not matched !\n");
523 return -EIO;
524 }
525
526 mutex_lock(&smu->mutex);
527 if (!smu_table->hardcode_pptable)
528 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
529 if (!smu_table->hardcode_pptable) {
530 ret = -ENOMEM;
531 goto failed;
532 }
533
534 memcpy(smu_table->hardcode_pptable, buf, size);
535 smu_table->power_play_table = smu_table->hardcode_pptable;
536 smu_table->power_play_table_size = size;
537
538 /*
539 * Special hw_fini action(for Navi1x, the DPMs disablement will be
540 * skipped) may be needed for custom pptable uploading.
541 */
542 smu->uploading_custom_pp_table = true;
543
544 ret = smu_reset(smu);
545 if (ret)
546 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
547
548 smu->uploading_custom_pp_table = false;
549
550 failed:
551 mutex_unlock(&smu->mutex);
552 return ret;
553 }
554
smu_get_driver_allowed_feature_mask(struct smu_context * smu)555 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
556 {
557 struct smu_feature *feature = &smu->smu_feature;
558 int ret = 0;
559 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
560
561 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
562
563 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
564 SMU_FEATURE_MAX/32);
565 if (ret)
566 return ret;
567
568 bitmap_or(feature->allowed, feature->allowed,
569 (unsigned long *)allowed_feature_mask,
570 feature->feature_num);
571
572 return ret;
573 }
574
smu_set_funcs(struct amdgpu_device * adev)575 static int smu_set_funcs(struct amdgpu_device *adev)
576 {
577 struct smu_context *smu = &adev->smu;
578
579 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
580 smu->od_enabled = true;
581
582 switch (adev->ip_versions[MP1_HWIP][0]) {
583 case IP_VERSION(11, 0, 0):
584 case IP_VERSION(11, 0, 5):
585 case IP_VERSION(11, 0, 9):
586 navi10_set_ppt_funcs(smu);
587 break;
588 case IP_VERSION(11, 0, 7):
589 case IP_VERSION(11, 0, 11):
590 case IP_VERSION(11, 0, 12):
591 case IP_VERSION(11, 0, 13):
592 sienna_cichlid_set_ppt_funcs(smu);
593 break;
594 case IP_VERSION(12, 0, 0):
595 case IP_VERSION(12, 0, 1):
596 renoir_set_ppt_funcs(smu);
597 break;
598 case IP_VERSION(11, 5, 0):
599 vangogh_set_ppt_funcs(smu);
600 break;
601 case IP_VERSION(13, 0, 1):
602 case IP_VERSION(13, 0, 3):
603 yellow_carp_set_ppt_funcs(smu);
604 break;
605 case IP_VERSION(11, 0, 8):
606 cyan_skillfish_set_ppt_funcs(smu);
607 break;
608 case IP_VERSION(11, 0, 2):
609 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
610 arcturus_set_ppt_funcs(smu);
611 /* OD is not supported on Arcturus */
612 smu->od_enabled =false;
613 break;
614 case IP_VERSION(13, 0, 2):
615 aldebaran_set_ppt_funcs(smu);
616 /* Enable pp_od_clk_voltage node */
617 smu->od_enabled = true;
618 break;
619 default:
620 return -EINVAL;
621 }
622
623 return 0;
624 }
625
smu_early_init(void * handle)626 static int smu_early_init(void *handle)
627 {
628 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
629 struct smu_context *smu = &adev->smu;
630
631 smu->adev = adev;
632 smu->pm_enabled = !!amdgpu_dpm;
633 smu->is_apu = false;
634 mutex_init(&smu->mutex);
635 mutex_init(&smu->smu_baco.mutex);
636 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
637 smu->smu_baco.platform_support = false;
638 smu->user_dpm_profile.fan_mode = -1;
639
640 adev->powerplay.pp_handle = smu;
641 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
642
643 return smu_set_funcs(adev);
644 }
645
smu_set_default_dpm_table(struct smu_context * smu)646 static int smu_set_default_dpm_table(struct smu_context *smu)
647 {
648 struct smu_power_context *smu_power = &smu->smu_power;
649 struct smu_power_gate *power_gate = &smu_power->power_gate;
650 int vcn_gate, jpeg_gate;
651 int ret = 0;
652
653 if (!smu->ppt_funcs->set_default_dpm_table)
654 return 0;
655
656 mutex_lock(&power_gate->vcn_gate_lock);
657 mutex_lock(&power_gate->jpeg_gate_lock);
658
659 vcn_gate = atomic_read(&power_gate->vcn_gated);
660 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
661
662 ret = smu_dpm_set_vcn_enable_locked(smu, true);
663 if (ret)
664 goto err0_out;
665
666 ret = smu_dpm_set_jpeg_enable_locked(smu, true);
667 if (ret)
668 goto err1_out;
669
670 ret = smu->ppt_funcs->set_default_dpm_table(smu);
671 if (ret)
672 dev_err(smu->adev->dev,
673 "Failed to setup default dpm clock tables!\n");
674
675 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
676 err1_out:
677 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
678 err0_out:
679 mutex_unlock(&power_gate->jpeg_gate_lock);
680 mutex_unlock(&power_gate->vcn_gate_lock);
681
682 return ret;
683 }
684
685
smu_late_init(void * handle)686 static int smu_late_init(void *handle)
687 {
688 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
689 struct smu_context *smu = &adev->smu;
690 int ret = 0;
691
692 smu_set_fine_grain_gfx_freq_parameters(smu);
693
694 if (!smu->pm_enabled)
695 return 0;
696
697 ret = smu_post_init(smu);
698 if (ret) {
699 dev_err(adev->dev, "Failed to post smu init!\n");
700 return ret;
701 }
702
703 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) ||
704 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)))
705 return 0;
706
707 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
708 ret = smu_set_default_od_settings(smu);
709 if (ret) {
710 dev_err(adev->dev, "Failed to setup default OD settings!\n");
711 return ret;
712 }
713 }
714
715 ret = smu_populate_umd_state_clk(smu);
716 if (ret) {
717 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
718 return ret;
719 }
720
721 ret = smu_get_asic_power_limits(smu,
722 &smu->current_power_limit,
723 &smu->default_power_limit,
724 &smu->max_power_limit);
725 if (ret) {
726 dev_err(adev->dev, "Failed to get asic power limits!\n");
727 return ret;
728 }
729
730 if (!amdgpu_sriov_vf(adev))
731 smu_get_unique_id(smu);
732
733 smu_get_fan_parameters(smu);
734
735 smu_handle_task(&adev->smu,
736 smu->smu_dpm.dpm_level,
737 AMD_PP_TASK_COMPLETE_INIT,
738 false);
739
740 smu_restore_dpm_user_profile(smu);
741
742 return 0;
743 }
744
smu_init_fb_allocations(struct smu_context * smu)745 static int smu_init_fb_allocations(struct smu_context *smu)
746 {
747 struct amdgpu_device *adev = smu->adev;
748 struct smu_table_context *smu_table = &smu->smu_table;
749 struct smu_table *tables = smu_table->tables;
750 struct smu_table *driver_table = &(smu_table->driver_table);
751 uint32_t max_table_size = 0;
752 int ret, i;
753
754 /* VRAM allocation for tool table */
755 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
756 ret = amdgpu_bo_create_kernel(adev,
757 tables[SMU_TABLE_PMSTATUSLOG].size,
758 tables[SMU_TABLE_PMSTATUSLOG].align,
759 tables[SMU_TABLE_PMSTATUSLOG].domain,
760 &tables[SMU_TABLE_PMSTATUSLOG].bo,
761 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
762 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
763 if (ret) {
764 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
765 return ret;
766 }
767 }
768
769 /* VRAM allocation for driver table */
770 for (i = 0; i < SMU_TABLE_COUNT; i++) {
771 if (tables[i].size == 0)
772 continue;
773
774 if (i == SMU_TABLE_PMSTATUSLOG)
775 continue;
776
777 if (max_table_size < tables[i].size)
778 max_table_size = tables[i].size;
779 }
780
781 driver_table->size = max_table_size;
782 driver_table->align = PAGE_SIZE;
783 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
784
785 ret = amdgpu_bo_create_kernel(adev,
786 driver_table->size,
787 driver_table->align,
788 driver_table->domain,
789 &driver_table->bo,
790 &driver_table->mc_address,
791 &driver_table->cpu_addr);
792 if (ret) {
793 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
794 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
795 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
796 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
797 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
798 }
799
800 return ret;
801 }
802
smu_fini_fb_allocations(struct smu_context * smu)803 static int smu_fini_fb_allocations(struct smu_context *smu)
804 {
805 struct smu_table_context *smu_table = &smu->smu_table;
806 struct smu_table *tables = smu_table->tables;
807 struct smu_table *driver_table = &(smu_table->driver_table);
808
809 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
810 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
811 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
812 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
813
814 amdgpu_bo_free_kernel(&driver_table->bo,
815 &driver_table->mc_address,
816 &driver_table->cpu_addr);
817
818 return 0;
819 }
820
821 /**
822 * smu_alloc_memory_pool - allocate memory pool in the system memory
823 *
824 * @smu: amdgpu_device pointer
825 *
826 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
827 * and DramLogSetDramAddr can notify it changed.
828 *
829 * Returns 0 on success, error on failure.
830 */
smu_alloc_memory_pool(struct smu_context * smu)831 static int smu_alloc_memory_pool(struct smu_context *smu)
832 {
833 struct amdgpu_device *adev = smu->adev;
834 struct smu_table_context *smu_table = &smu->smu_table;
835 struct smu_table *memory_pool = &smu_table->memory_pool;
836 uint64_t pool_size = smu->pool_size;
837 int ret = 0;
838
839 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
840 return ret;
841
842 memory_pool->size = pool_size;
843 memory_pool->align = PAGE_SIZE;
844 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
845
846 switch (pool_size) {
847 case SMU_MEMORY_POOL_SIZE_256_MB:
848 case SMU_MEMORY_POOL_SIZE_512_MB:
849 case SMU_MEMORY_POOL_SIZE_1_GB:
850 case SMU_MEMORY_POOL_SIZE_2_GB:
851 ret = amdgpu_bo_create_kernel(adev,
852 memory_pool->size,
853 memory_pool->align,
854 memory_pool->domain,
855 &memory_pool->bo,
856 &memory_pool->mc_address,
857 &memory_pool->cpu_addr);
858 if (ret)
859 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
860 break;
861 default:
862 break;
863 }
864
865 return ret;
866 }
867
smu_free_memory_pool(struct smu_context * smu)868 static int smu_free_memory_pool(struct smu_context *smu)
869 {
870 struct smu_table_context *smu_table = &smu->smu_table;
871 struct smu_table *memory_pool = &smu_table->memory_pool;
872
873 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
874 return 0;
875
876 amdgpu_bo_free_kernel(&memory_pool->bo,
877 &memory_pool->mc_address,
878 &memory_pool->cpu_addr);
879
880 memset(memory_pool, 0, sizeof(struct smu_table));
881
882 return 0;
883 }
884
smu_alloc_dummy_read_table(struct smu_context * smu)885 static int smu_alloc_dummy_read_table(struct smu_context *smu)
886 {
887 struct smu_table_context *smu_table = &smu->smu_table;
888 struct smu_table *dummy_read_1_table =
889 &smu_table->dummy_read_1_table;
890 struct amdgpu_device *adev = smu->adev;
891 int ret = 0;
892
893 dummy_read_1_table->size = 0x40000;
894 dummy_read_1_table->align = PAGE_SIZE;
895 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
896
897 ret = amdgpu_bo_create_kernel(adev,
898 dummy_read_1_table->size,
899 dummy_read_1_table->align,
900 dummy_read_1_table->domain,
901 &dummy_read_1_table->bo,
902 &dummy_read_1_table->mc_address,
903 &dummy_read_1_table->cpu_addr);
904 if (ret)
905 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
906
907 return ret;
908 }
909
smu_free_dummy_read_table(struct smu_context * smu)910 static void smu_free_dummy_read_table(struct smu_context *smu)
911 {
912 struct smu_table_context *smu_table = &smu->smu_table;
913 struct smu_table *dummy_read_1_table =
914 &smu_table->dummy_read_1_table;
915
916
917 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
918 &dummy_read_1_table->mc_address,
919 &dummy_read_1_table->cpu_addr);
920
921 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
922 }
923
smu_smc_table_sw_init(struct smu_context * smu)924 static int smu_smc_table_sw_init(struct smu_context *smu)
925 {
926 int ret;
927
928 /**
929 * Create smu_table structure, and init smc tables such as
930 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
931 */
932 ret = smu_init_smc_tables(smu);
933 if (ret) {
934 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
935 return ret;
936 }
937
938 /**
939 * Create smu_power_context structure, and allocate smu_dpm_context and
940 * context size to fill the smu_power_context data.
941 */
942 ret = smu_init_power(smu);
943 if (ret) {
944 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
945 return ret;
946 }
947
948 /*
949 * allocate vram bos to store smc table contents.
950 */
951 ret = smu_init_fb_allocations(smu);
952 if (ret)
953 return ret;
954
955 ret = smu_alloc_memory_pool(smu);
956 if (ret)
957 return ret;
958
959 ret = smu_alloc_dummy_read_table(smu);
960 if (ret)
961 return ret;
962
963 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
964 if (ret)
965 return ret;
966
967 return 0;
968 }
969
smu_smc_table_sw_fini(struct smu_context * smu)970 static int smu_smc_table_sw_fini(struct smu_context *smu)
971 {
972 int ret;
973
974 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
975
976 smu_free_dummy_read_table(smu);
977
978 ret = smu_free_memory_pool(smu);
979 if (ret)
980 return ret;
981
982 ret = smu_fini_fb_allocations(smu);
983 if (ret)
984 return ret;
985
986 ret = smu_fini_power(smu);
987 if (ret) {
988 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
989 return ret;
990 }
991
992 ret = smu_fini_smc_tables(smu);
993 if (ret) {
994 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
995 return ret;
996 }
997
998 return 0;
999 }
1000
smu_throttling_logging_work_fn(struct work_struct * work)1001 static void smu_throttling_logging_work_fn(struct work_struct *work)
1002 {
1003 struct smu_context *smu = container_of(work, struct smu_context,
1004 throttling_logging_work);
1005
1006 smu_log_thermal_throttling(smu);
1007 }
1008
smu_interrupt_work_fn(struct work_struct * work)1009 static void smu_interrupt_work_fn(struct work_struct *work)
1010 {
1011 struct smu_context *smu = container_of(work, struct smu_context,
1012 interrupt_work);
1013
1014 mutex_lock(&smu->mutex);
1015
1016 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1017 smu->ppt_funcs->interrupt_work(smu);
1018
1019 mutex_unlock(&smu->mutex);
1020 }
1021
smu_sw_init(void * handle)1022 static int smu_sw_init(void *handle)
1023 {
1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025 struct smu_context *smu = &adev->smu;
1026 int ret;
1027
1028 smu->pool_size = adev->pm.smu_prv_buffer_size;
1029 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1030 mutex_init(&smu->smu_feature.mutex);
1031 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1032 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
1033 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1034
1035 mutex_init(&smu->sensor_lock);
1036 mutex_init(&smu->metrics_lock);
1037 mutex_init(&smu->message_lock);
1038
1039 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1040 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1041 atomic64_set(&smu->throttle_int_counter, 0);
1042 smu->watermarks_bitmap = 0;
1043 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1044 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1045
1046 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1047 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1048 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
1049 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
1050
1051 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1052 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1053 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1054 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1055 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1056 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1057 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1058 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1059
1060 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1061 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1062 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1063 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1064 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1065 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1066 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1067 smu->display_config = &adev->pm.pm_display_cfg;
1068
1069 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1070 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1071
1072 ret = smu_init_microcode(smu);
1073 if (ret) {
1074 dev_err(adev->dev, "Failed to load smu firmware!\n");
1075 return ret;
1076 }
1077
1078 ret = smu_smc_table_sw_init(smu);
1079 if (ret) {
1080 dev_err(adev->dev, "Failed to sw init smc table!\n");
1081 return ret;
1082 }
1083
1084 ret = smu_register_irq_handler(smu);
1085 if (ret) {
1086 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1087 return ret;
1088 }
1089
1090 /* If there is no way to query fan control mode, fan control is not supported */
1091 if (!smu->ppt_funcs->get_fan_control_mode)
1092 smu->adev->pm.no_fan = true;
1093
1094 return 0;
1095 }
1096
smu_sw_fini(void * handle)1097 static int smu_sw_fini(void *handle)
1098 {
1099 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1100 struct smu_context *smu = &adev->smu;
1101 int ret;
1102
1103 ret = smu_smc_table_sw_fini(smu);
1104 if (ret) {
1105 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1106 return ret;
1107 }
1108
1109 smu_fini_microcode(smu);
1110
1111 return 0;
1112 }
1113
smu_get_thermal_temperature_range(struct smu_context * smu)1114 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1115 {
1116 struct amdgpu_device *adev = smu->adev;
1117 struct smu_temperature_range *range =
1118 &smu->thermal_range;
1119 int ret = 0;
1120
1121 if (!smu->ppt_funcs->get_thermal_temperature_range)
1122 return 0;
1123
1124 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1125 if (ret)
1126 return ret;
1127
1128 adev->pm.dpm.thermal.min_temp = range->min;
1129 adev->pm.dpm.thermal.max_temp = range->max;
1130 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1131 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1132 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1133 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1134 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1135 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1136 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1137
1138 return ret;
1139 }
1140
smu_smc_hw_setup(struct smu_context * smu)1141 static int smu_smc_hw_setup(struct smu_context *smu)
1142 {
1143 struct amdgpu_device *adev = smu->adev;
1144 uint32_t pcie_gen = 0, pcie_width = 0;
1145 int ret = 0;
1146
1147 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1148 dev_info(adev->dev, "dpm has been enabled\n");
1149 /* this is needed specifically */
1150 switch (adev->ip_versions[MP1_HWIP][0]) {
1151 case IP_VERSION(11, 0, 7):
1152 case IP_VERSION(11, 0, 11):
1153 case IP_VERSION(11, 5, 0):
1154 case IP_VERSION(11, 0, 12):
1155 ret = smu_system_features_control(smu, true);
1156 break;
1157 default:
1158 break;
1159 }
1160 return ret;
1161 }
1162
1163 ret = smu_init_display_count(smu, 0);
1164 if (ret) {
1165 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1166 return ret;
1167 }
1168
1169 ret = smu_set_driver_table_location(smu);
1170 if (ret) {
1171 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1172 return ret;
1173 }
1174
1175 /*
1176 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1177 */
1178 ret = smu_set_tool_table_location(smu);
1179 if (ret) {
1180 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1181 return ret;
1182 }
1183
1184 /*
1185 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1186 * pool location.
1187 */
1188 ret = smu_notify_memory_pool_location(smu);
1189 if (ret) {
1190 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1191 return ret;
1192 }
1193
1194 /* smu_dump_pptable(smu); */
1195 /*
1196 * Copy pptable bo in the vram to smc with SMU MSGs such as
1197 * SetDriverDramAddr and TransferTableDram2Smu.
1198 */
1199 ret = smu_write_pptable(smu);
1200 if (ret) {
1201 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1202 return ret;
1203 }
1204
1205 /* issue Run*Btc msg */
1206 ret = smu_run_btc(smu);
1207 if (ret)
1208 return ret;
1209
1210 ret = smu_feature_set_allowed_mask(smu);
1211 if (ret) {
1212 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1213 return ret;
1214 }
1215
1216 ret = smu_system_features_control(smu, true);
1217 if (ret) {
1218 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1219 return ret;
1220 }
1221
1222 if (!smu_is_dpm_running(smu))
1223 dev_info(adev->dev, "dpm has been disabled\n");
1224
1225 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1226 pcie_gen = 3;
1227 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1228 pcie_gen = 2;
1229 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1230 pcie_gen = 1;
1231 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1232 pcie_gen = 0;
1233
1234 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1235 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1236 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1237 */
1238 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1239 pcie_width = 6;
1240 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1241 pcie_width = 5;
1242 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1243 pcie_width = 4;
1244 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1245 pcie_width = 3;
1246 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1247 pcie_width = 2;
1248 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1249 pcie_width = 1;
1250 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1251 if (ret) {
1252 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1253 return ret;
1254 }
1255
1256 ret = smu_get_thermal_temperature_range(smu);
1257 if (ret) {
1258 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1259 return ret;
1260 }
1261
1262 ret = smu_enable_thermal_alert(smu);
1263 if (ret) {
1264 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1265 return ret;
1266 }
1267
1268 /*
1269 * Set initialized values (get from vbios) to dpm tables context such as
1270 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1271 * type of clks.
1272 */
1273 ret = smu_set_default_dpm_table(smu);
1274 if (ret) {
1275 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1276 return ret;
1277 }
1278
1279 ret = smu_notify_display_change(smu);
1280 if (ret)
1281 return ret;
1282
1283 /*
1284 * Set min deep sleep dce fclk with bootup value from vbios via
1285 * SetMinDeepSleepDcefclk MSG.
1286 */
1287 ret = smu_set_min_dcef_deep_sleep(smu,
1288 smu->smu_table.boot_values.dcefclk / 100);
1289 if (ret)
1290 return ret;
1291
1292 return ret;
1293 }
1294
smu_start_smc_engine(struct smu_context * smu)1295 static int smu_start_smc_engine(struct smu_context *smu)
1296 {
1297 struct amdgpu_device *adev = smu->adev;
1298 int ret = 0;
1299
1300 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1301 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
1302 if (smu->ppt_funcs->load_microcode) {
1303 ret = smu->ppt_funcs->load_microcode(smu);
1304 if (ret)
1305 return ret;
1306 }
1307 }
1308 }
1309
1310 if (smu->ppt_funcs->check_fw_status) {
1311 ret = smu->ppt_funcs->check_fw_status(smu);
1312 if (ret) {
1313 dev_err(adev->dev, "SMC is not ready\n");
1314 return ret;
1315 }
1316 }
1317
1318 /*
1319 * Send msg GetDriverIfVersion to check if the return value is equal
1320 * with DRIVER_IF_VERSION of smc header.
1321 */
1322 ret = smu_check_fw_version(smu);
1323 if (ret)
1324 return ret;
1325
1326 return ret;
1327 }
1328
smu_hw_init(void * handle)1329 static int smu_hw_init(void *handle)
1330 {
1331 int ret;
1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1333 struct smu_context *smu = &adev->smu;
1334
1335 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1336 smu->pm_enabled = false;
1337 return 0;
1338 }
1339
1340 ret = smu_start_smc_engine(smu);
1341 if (ret) {
1342 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1343 return ret;
1344 }
1345
1346 if (smu->is_apu) {
1347 smu_powergate_sdma(&adev->smu, false);
1348 smu_dpm_set_vcn_enable(smu, true);
1349 smu_dpm_set_jpeg_enable(smu, true);
1350 smu_set_gfx_cgpg(&adev->smu, true);
1351 }
1352
1353 if (!smu->pm_enabled)
1354 return 0;
1355
1356 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1357 ret = smu_get_vbios_bootup_values(smu);
1358 if (ret) {
1359 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1360 return ret;
1361 }
1362
1363 ret = smu_setup_pptable(smu);
1364 if (ret) {
1365 dev_err(adev->dev, "Failed to setup pptable!\n");
1366 return ret;
1367 }
1368
1369 ret = smu_get_driver_allowed_feature_mask(smu);
1370 if (ret)
1371 return ret;
1372
1373 ret = smu_smc_hw_setup(smu);
1374 if (ret) {
1375 dev_err(adev->dev, "Failed to setup smc hw!\n");
1376 return ret;
1377 }
1378
1379 /*
1380 * Move maximum sustainable clock retrieving here considering
1381 * 1. It is not needed on resume(from S3).
1382 * 2. DAL settings come between .hw_init and .late_init of SMU.
1383 * And DAL needs to know the maximum sustainable clocks. Thus
1384 * it cannot be put in .late_init().
1385 */
1386 ret = smu_init_max_sustainable_clocks(smu);
1387 if (ret) {
1388 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1389 return ret;
1390 }
1391
1392 adev->pm.dpm_enabled = true;
1393
1394 dev_info(adev->dev, "SMU is initialized successfully!\n");
1395
1396 return 0;
1397 }
1398
smu_disable_dpms(struct smu_context * smu)1399 static int smu_disable_dpms(struct smu_context *smu)
1400 {
1401 struct amdgpu_device *adev = smu->adev;
1402 int ret = 0;
1403 /*
1404 * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair
1405 * the workaround which always reset the asic in suspend.
1406 * It's likely that workaround will be dropped in the future.
1407 * Then the change here should be dropped together.
1408 */
1409 bool use_baco = !smu->is_apu &&
1410 (((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) &&
1411 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1412 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1413
1414 /*
1415 * For custom pptable uploading, skip the DPM features
1416 * disable process on Navi1x ASICs.
1417 * - As the gfx related features are under control of
1418 * RLC on those ASICs. RLC reinitialization will be
1419 * needed to reenable them. That will cost much more
1420 * efforts.
1421 *
1422 * - SMU firmware can handle the DPM reenablement
1423 * properly.
1424 */
1425 if (smu->uploading_custom_pp_table) {
1426 switch (adev->ip_versions[MP1_HWIP][0]) {
1427 case IP_VERSION(11, 0, 0):
1428 case IP_VERSION(11, 0, 5):
1429 case IP_VERSION(11, 0, 9):
1430 case IP_VERSION(11, 0, 7):
1431 case IP_VERSION(11, 0, 11):
1432 case IP_VERSION(11, 5, 0):
1433 case IP_VERSION(11, 0, 12):
1434 case IP_VERSION(11, 0, 13):
1435 return smu_disable_all_features_with_exception(smu,
1436 true,
1437 SMU_FEATURE_COUNT);
1438 default:
1439 break;
1440 }
1441 }
1442
1443 /*
1444 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1445 * on BACO in. Driver involvement is unnecessary.
1446 */
1447 if (use_baco) {
1448 switch (adev->ip_versions[MP1_HWIP][0]) {
1449 case IP_VERSION(11, 0, 7):
1450 case IP_VERSION(11, 0, 0):
1451 case IP_VERSION(11, 0, 5):
1452 case IP_VERSION(11, 0, 9):
1453 return smu_disable_all_features_with_exception(smu,
1454 true,
1455 SMU_FEATURE_BACO_BIT);
1456 default:
1457 break;
1458 }
1459 }
1460
1461 /*
1462 * For gpu reset, runpm and hibernation through BACO,
1463 * BACO feature has to be kept enabled.
1464 */
1465 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1466 ret = smu_disable_all_features_with_exception(smu,
1467 false,
1468 SMU_FEATURE_BACO_BIT);
1469 if (ret)
1470 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1471 } else {
1472 ret = smu_system_features_control(smu, false);
1473 if (ret)
1474 dev_err(adev->dev, "Failed to disable smu features.\n");
1475 }
1476
1477 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) &&
1478 adev->gfx.rlc.funcs->stop)
1479 adev->gfx.rlc.funcs->stop(adev);
1480
1481 return ret;
1482 }
1483
smu_smc_hw_cleanup(struct smu_context * smu)1484 static int smu_smc_hw_cleanup(struct smu_context *smu)
1485 {
1486 struct amdgpu_device *adev = smu->adev;
1487 int ret = 0;
1488
1489 cancel_work_sync(&smu->throttling_logging_work);
1490 cancel_work_sync(&smu->interrupt_work);
1491
1492 ret = smu_disable_thermal_alert(smu);
1493 if (ret) {
1494 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1495 return ret;
1496 }
1497
1498 ret = smu_disable_dpms(smu);
1499 if (ret) {
1500 dev_err(adev->dev, "Fail to disable dpm features!\n");
1501 return ret;
1502 }
1503
1504 return 0;
1505 }
1506
smu_hw_fini(void * handle)1507 static int smu_hw_fini(void *handle)
1508 {
1509 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1510 struct smu_context *smu = &adev->smu;
1511
1512 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1513 return 0;
1514
1515 if (smu->is_apu) {
1516 smu_powergate_sdma(&adev->smu, true);
1517 }
1518
1519 smu_dpm_set_vcn_enable(smu, false);
1520 smu_dpm_set_jpeg_enable(smu, false);
1521
1522 adev->vcn.cur_state = AMD_PG_STATE_GATE;
1523 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1524
1525 if (!smu->pm_enabled)
1526 return 0;
1527
1528 adev->pm.dpm_enabled = false;
1529
1530 return smu_smc_hw_cleanup(smu);
1531 }
1532
smu_reset(struct smu_context * smu)1533 static int smu_reset(struct smu_context *smu)
1534 {
1535 struct amdgpu_device *adev = smu->adev;
1536 int ret;
1537
1538 amdgpu_gfx_off_ctrl(smu->adev, false);
1539
1540 ret = smu_hw_fini(adev);
1541 if (ret)
1542 return ret;
1543
1544 ret = smu_hw_init(adev);
1545 if (ret)
1546 return ret;
1547
1548 ret = smu_late_init(adev);
1549 if (ret)
1550 return ret;
1551
1552 amdgpu_gfx_off_ctrl(smu->adev, true);
1553
1554 return 0;
1555 }
1556
smu_suspend(void * handle)1557 static int smu_suspend(void *handle)
1558 {
1559 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1560 struct smu_context *smu = &adev->smu;
1561 int ret;
1562
1563 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1564 return 0;
1565
1566 if (!smu->pm_enabled)
1567 return 0;
1568
1569 adev->pm.dpm_enabled = false;
1570
1571 ret = smu_smc_hw_cleanup(smu);
1572 if (ret)
1573 return ret;
1574
1575 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1576
1577 smu_set_gfx_cgpg(&adev->smu, false);
1578
1579 return 0;
1580 }
1581
smu_resume(void * handle)1582 static int smu_resume(void *handle)
1583 {
1584 int ret;
1585 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1586 struct smu_context *smu = &adev->smu;
1587
1588 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1589 return 0;
1590
1591 if (!smu->pm_enabled)
1592 return 0;
1593
1594 dev_info(adev->dev, "SMU is resuming...\n");
1595
1596 ret = smu_start_smc_engine(smu);
1597 if (ret) {
1598 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1599 return ret;
1600 }
1601
1602 ret = smu_smc_hw_setup(smu);
1603 if (ret) {
1604 dev_err(adev->dev, "Failed to setup smc hw!\n");
1605 return ret;
1606 }
1607
1608 smu_set_gfx_cgpg(&adev->smu, true);
1609
1610 smu->disable_uclk_switch = 0;
1611
1612 adev->pm.dpm_enabled = true;
1613
1614 dev_info(adev->dev, "SMU is resumed successfully!\n");
1615
1616 return 0;
1617 }
1618
smu_display_configuration_change(void * handle,const struct amd_pp_display_configuration * display_config)1619 static int smu_display_configuration_change(void *handle,
1620 const struct amd_pp_display_configuration *display_config)
1621 {
1622 struct smu_context *smu = handle;
1623 int index = 0;
1624 int num_of_active_display = 0;
1625
1626 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1627 return -EOPNOTSUPP;
1628
1629 if (!display_config)
1630 return -EINVAL;
1631
1632 mutex_lock(&smu->mutex);
1633
1634 smu_set_min_dcef_deep_sleep(smu,
1635 display_config->min_dcef_deep_sleep_set_clk / 100);
1636
1637 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1638 if (display_config->displays[index].controller_id != 0)
1639 num_of_active_display++;
1640 }
1641
1642 mutex_unlock(&smu->mutex);
1643
1644 return 0;
1645 }
1646
smu_set_clockgating_state(void * handle,enum amd_clockgating_state state)1647 static int smu_set_clockgating_state(void *handle,
1648 enum amd_clockgating_state state)
1649 {
1650 return 0;
1651 }
1652
smu_set_powergating_state(void * handle,enum amd_powergating_state state)1653 static int smu_set_powergating_state(void *handle,
1654 enum amd_powergating_state state)
1655 {
1656 return 0;
1657 }
1658
smu_enable_umd_pstate(void * handle,enum amd_dpm_forced_level * level)1659 static int smu_enable_umd_pstate(void *handle,
1660 enum amd_dpm_forced_level *level)
1661 {
1662 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1663 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1664 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1665 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1666
1667 struct smu_context *smu = (struct smu_context*)(handle);
1668 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1669
1670 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1671 return -EINVAL;
1672
1673 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1674 /* enter umd pstate, save current level, disable gfx cg*/
1675 if (*level & profile_mode_mask) {
1676 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1677 smu_dpm_ctx->enable_umd_pstate = true;
1678 smu_gpo_control(smu, false);
1679 amdgpu_device_ip_set_powergating_state(smu->adev,
1680 AMD_IP_BLOCK_TYPE_GFX,
1681 AMD_PG_STATE_UNGATE);
1682 amdgpu_device_ip_set_clockgating_state(smu->adev,
1683 AMD_IP_BLOCK_TYPE_GFX,
1684 AMD_CG_STATE_UNGATE);
1685 smu_gfx_ulv_control(smu, false);
1686 smu_deep_sleep_control(smu, false);
1687 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1688 }
1689 } else {
1690 /* exit umd pstate, restore level, enable gfx cg*/
1691 if (!(*level & profile_mode_mask)) {
1692 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1693 *level = smu_dpm_ctx->saved_dpm_level;
1694 smu_dpm_ctx->enable_umd_pstate = false;
1695 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1696 smu_deep_sleep_control(smu, true);
1697 smu_gfx_ulv_control(smu, true);
1698 amdgpu_device_ip_set_clockgating_state(smu->adev,
1699 AMD_IP_BLOCK_TYPE_GFX,
1700 AMD_CG_STATE_GATE);
1701 amdgpu_device_ip_set_powergating_state(smu->adev,
1702 AMD_IP_BLOCK_TYPE_GFX,
1703 AMD_PG_STATE_GATE);
1704 smu_gpo_control(smu, true);
1705 }
1706 }
1707
1708 return 0;
1709 }
1710
smu_bump_power_profile_mode(struct smu_context * smu,long * param,uint32_t param_size)1711 static int smu_bump_power_profile_mode(struct smu_context *smu,
1712 long *param,
1713 uint32_t param_size)
1714 {
1715 int ret = 0;
1716
1717 if (smu->ppt_funcs->set_power_profile_mode)
1718 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1719
1720 return ret;
1721 }
1722
smu_adjust_power_state_dynamic(struct smu_context * smu,enum amd_dpm_forced_level level,bool skip_display_settings)1723 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1724 enum amd_dpm_forced_level level,
1725 bool skip_display_settings)
1726 {
1727 int ret = 0;
1728 int index = 0;
1729 long workload;
1730 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1731
1732 if (!skip_display_settings) {
1733 ret = smu_display_config_changed(smu);
1734 if (ret) {
1735 dev_err(smu->adev->dev, "Failed to change display config!");
1736 return ret;
1737 }
1738 }
1739
1740 ret = smu_apply_clocks_adjust_rules(smu);
1741 if (ret) {
1742 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1743 return ret;
1744 }
1745
1746 if (!skip_display_settings) {
1747 ret = smu_notify_smc_display_config(smu);
1748 if (ret) {
1749 dev_err(smu->adev->dev, "Failed to notify smc display config!");
1750 return ret;
1751 }
1752 }
1753
1754 if (smu_dpm_ctx->dpm_level != level) {
1755 ret = smu_asic_set_performance_level(smu, level);
1756 if (ret) {
1757 dev_err(smu->adev->dev, "Failed to set performance level!");
1758 return ret;
1759 }
1760
1761 /* update the saved copy */
1762 smu_dpm_ctx->dpm_level = level;
1763 }
1764
1765 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1766 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1767 index = fls(smu->workload_mask);
1768 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1769 workload = smu->workload_setting[index];
1770
1771 if (smu->power_profile_mode != workload)
1772 smu_bump_power_profile_mode(smu, &workload, 0);
1773 }
1774
1775 return ret;
1776 }
1777
smu_handle_task(struct smu_context * smu,enum amd_dpm_forced_level level,enum amd_pp_task task_id,bool lock_needed)1778 static int smu_handle_task(struct smu_context *smu,
1779 enum amd_dpm_forced_level level,
1780 enum amd_pp_task task_id,
1781 bool lock_needed)
1782 {
1783 int ret = 0;
1784
1785 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1786 return -EOPNOTSUPP;
1787
1788 if (lock_needed)
1789 mutex_lock(&smu->mutex);
1790
1791 switch (task_id) {
1792 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1793 ret = smu_pre_display_config_changed(smu);
1794 if (ret)
1795 goto out;
1796 ret = smu_adjust_power_state_dynamic(smu, level, false);
1797 break;
1798 case AMD_PP_TASK_COMPLETE_INIT:
1799 case AMD_PP_TASK_READJUST_POWER_STATE:
1800 ret = smu_adjust_power_state_dynamic(smu, level, true);
1801 break;
1802 default:
1803 break;
1804 }
1805
1806 out:
1807 if (lock_needed)
1808 mutex_unlock(&smu->mutex);
1809
1810 return ret;
1811 }
1812
smu_handle_dpm_task(void * handle,enum amd_pp_task task_id,enum amd_pm_state_type * user_state)1813 static int smu_handle_dpm_task(void *handle,
1814 enum amd_pp_task task_id,
1815 enum amd_pm_state_type *user_state)
1816 {
1817 struct smu_context *smu = handle;
1818 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1819
1820 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true);
1821
1822 }
1823
smu_switch_power_profile(void * handle,enum PP_SMC_POWER_PROFILE type,bool en)1824 static int smu_switch_power_profile(void *handle,
1825 enum PP_SMC_POWER_PROFILE type,
1826 bool en)
1827 {
1828 struct smu_context *smu = handle;
1829 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1830 long workload;
1831 uint32_t index;
1832
1833 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1834 return -EOPNOTSUPP;
1835
1836 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1837 return -EINVAL;
1838
1839 mutex_lock(&smu->mutex);
1840
1841 if (!en) {
1842 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1843 index = fls(smu->workload_mask);
1844 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1845 workload = smu->workload_setting[index];
1846 } else {
1847 smu->workload_mask |= (1 << smu->workload_prority[type]);
1848 index = fls(smu->workload_mask);
1849 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1850 workload = smu->workload_setting[index];
1851 }
1852
1853 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1854 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1855 smu_bump_power_profile_mode(smu, &workload, 0);
1856
1857 mutex_unlock(&smu->mutex);
1858
1859 return 0;
1860 }
1861
smu_get_performance_level(void * handle)1862 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1863 {
1864 struct smu_context *smu = handle;
1865 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1866 enum amd_dpm_forced_level level;
1867
1868 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1869 return -EOPNOTSUPP;
1870
1871 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1872 return -EINVAL;
1873
1874 mutex_lock(&(smu->mutex));
1875 level = smu_dpm_ctx->dpm_level;
1876 mutex_unlock(&(smu->mutex));
1877
1878 return level;
1879 }
1880
smu_force_performance_level(void * handle,enum amd_dpm_forced_level level)1881 static int smu_force_performance_level(void *handle,
1882 enum amd_dpm_forced_level level)
1883 {
1884 struct smu_context *smu = handle;
1885 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1886 int ret = 0;
1887
1888 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1889 return -EOPNOTSUPP;
1890
1891 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1892 return -EINVAL;
1893
1894 mutex_lock(&smu->mutex);
1895
1896 ret = smu_enable_umd_pstate(smu, &level);
1897 if (ret) {
1898 mutex_unlock(&smu->mutex);
1899 return ret;
1900 }
1901
1902 ret = smu_handle_task(smu, level,
1903 AMD_PP_TASK_READJUST_POWER_STATE,
1904 false);
1905
1906 mutex_unlock(&smu->mutex);
1907
1908 /* reset user dpm clock state */
1909 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1910 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1911 smu->user_dpm_profile.clk_dependency = 0;
1912 }
1913
1914 return ret;
1915 }
1916
smu_set_display_count(void * handle,uint32_t count)1917 static int smu_set_display_count(void *handle, uint32_t count)
1918 {
1919 struct smu_context *smu = handle;
1920 int ret = 0;
1921
1922 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1923 return -EOPNOTSUPP;
1924
1925 mutex_lock(&smu->mutex);
1926 ret = smu_init_display_count(smu, count);
1927 mutex_unlock(&smu->mutex);
1928
1929 return ret;
1930 }
1931
smu_force_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1932 static int smu_force_smuclk_levels(struct smu_context *smu,
1933 enum smu_clk_type clk_type,
1934 uint32_t mask)
1935 {
1936 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1937 int ret = 0;
1938
1939 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1940 return -EOPNOTSUPP;
1941
1942 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1943 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1944 return -EINVAL;
1945 }
1946
1947 mutex_lock(&smu->mutex);
1948
1949 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1950 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1951 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
1952 smu->user_dpm_profile.clk_mask[clk_type] = mask;
1953 smu_set_user_clk_dependencies(smu, clk_type);
1954 }
1955 }
1956
1957 mutex_unlock(&smu->mutex);
1958
1959 return ret;
1960 }
1961
smu_force_ppclk_levels(void * handle,enum pp_clock_type type,uint32_t mask)1962 static int smu_force_ppclk_levels(void *handle,
1963 enum pp_clock_type type,
1964 uint32_t mask)
1965 {
1966 struct smu_context *smu = handle;
1967 enum smu_clk_type clk_type;
1968
1969 switch (type) {
1970 case PP_SCLK:
1971 clk_type = SMU_SCLK; break;
1972 case PP_MCLK:
1973 clk_type = SMU_MCLK; break;
1974 case PP_PCIE:
1975 clk_type = SMU_PCIE; break;
1976 case PP_SOCCLK:
1977 clk_type = SMU_SOCCLK; break;
1978 case PP_FCLK:
1979 clk_type = SMU_FCLK; break;
1980 case PP_DCEFCLK:
1981 clk_type = SMU_DCEFCLK; break;
1982 case PP_VCLK:
1983 clk_type = SMU_VCLK; break;
1984 case PP_DCLK:
1985 clk_type = SMU_DCLK; break;
1986 case OD_SCLK:
1987 clk_type = SMU_OD_SCLK; break;
1988 case OD_MCLK:
1989 clk_type = SMU_OD_MCLK; break;
1990 case OD_VDDC_CURVE:
1991 clk_type = SMU_OD_VDDC_CURVE; break;
1992 case OD_RANGE:
1993 clk_type = SMU_OD_RANGE; break;
1994 default:
1995 return -EINVAL;
1996 }
1997
1998 return smu_force_smuclk_levels(smu, clk_type, mask);
1999 }
2000
2001 /*
2002 * On system suspending or resetting, the dpm_enabled
2003 * flag will be cleared. So that those SMU services which
2004 * are not supported will be gated.
2005 * However, the mp1 state setting should still be granted
2006 * even if the dpm_enabled cleared.
2007 */
smu_set_mp1_state(void * handle,enum pp_mp1_state mp1_state)2008 static int smu_set_mp1_state(void *handle,
2009 enum pp_mp1_state mp1_state)
2010 {
2011 struct smu_context *smu = handle;
2012 int ret = 0;
2013
2014 if (!smu->pm_enabled)
2015 return -EOPNOTSUPP;
2016
2017 mutex_lock(&smu->mutex);
2018
2019 if (smu->ppt_funcs &&
2020 smu->ppt_funcs->set_mp1_state)
2021 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2022
2023 mutex_unlock(&smu->mutex);
2024
2025 return ret;
2026 }
2027
smu_set_df_cstate(void * handle,enum pp_df_cstate state)2028 static int smu_set_df_cstate(void *handle,
2029 enum pp_df_cstate state)
2030 {
2031 struct smu_context *smu = handle;
2032 int ret = 0;
2033
2034 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2035 return -EOPNOTSUPP;
2036
2037 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2038 return 0;
2039
2040 mutex_lock(&smu->mutex);
2041
2042 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2043 if (ret)
2044 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2045
2046 mutex_unlock(&smu->mutex);
2047
2048 return ret;
2049 }
2050
smu_allow_xgmi_power_down(struct smu_context * smu,bool en)2051 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2052 {
2053 int ret = 0;
2054
2055 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2056 return -EOPNOTSUPP;
2057
2058 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2059 return 0;
2060
2061 mutex_lock(&smu->mutex);
2062
2063 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2064 if (ret)
2065 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2066
2067 mutex_unlock(&smu->mutex);
2068
2069 return ret;
2070 }
2071
smu_write_watermarks_table(struct smu_context * smu)2072 int smu_write_watermarks_table(struct smu_context *smu)
2073 {
2074 int ret = 0;
2075
2076 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2077 return -EOPNOTSUPP;
2078
2079 mutex_lock(&smu->mutex);
2080
2081 ret = smu_set_watermarks_table(smu, NULL);
2082
2083 mutex_unlock(&smu->mutex);
2084
2085 return ret;
2086 }
2087
smu_set_watermarks_for_clock_ranges(void * handle,struct pp_smu_wm_range_sets * clock_ranges)2088 static int smu_set_watermarks_for_clock_ranges(void *handle,
2089 struct pp_smu_wm_range_sets *clock_ranges)
2090 {
2091 struct smu_context *smu = handle;
2092 int ret = 0;
2093
2094 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2095 return -EOPNOTSUPP;
2096
2097 if (smu->disable_watermark)
2098 return 0;
2099
2100 mutex_lock(&smu->mutex);
2101
2102 ret = smu_set_watermarks_table(smu, clock_ranges);
2103
2104 mutex_unlock(&smu->mutex);
2105
2106 return ret;
2107 }
2108
smu_set_ac_dc(struct smu_context * smu)2109 int smu_set_ac_dc(struct smu_context *smu)
2110 {
2111 int ret = 0;
2112
2113 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2114 return -EOPNOTSUPP;
2115
2116 /* controlled by firmware */
2117 if (smu->dc_controlled_by_gpio)
2118 return 0;
2119
2120 mutex_lock(&smu->mutex);
2121 ret = smu_set_power_source(smu,
2122 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2123 SMU_POWER_SOURCE_DC);
2124 if (ret)
2125 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2126 smu->adev->pm.ac_power ? "AC" : "DC");
2127 mutex_unlock(&smu->mutex);
2128
2129 return ret;
2130 }
2131
2132 const struct amd_ip_funcs smu_ip_funcs = {
2133 .name = "smu",
2134 .early_init = smu_early_init,
2135 .late_init = smu_late_init,
2136 .sw_init = smu_sw_init,
2137 .sw_fini = smu_sw_fini,
2138 .hw_init = smu_hw_init,
2139 .hw_fini = smu_hw_fini,
2140 .suspend = smu_suspend,
2141 .resume = smu_resume,
2142 .is_idle = NULL,
2143 .check_soft_reset = NULL,
2144 .wait_for_idle = NULL,
2145 .soft_reset = NULL,
2146 .set_clockgating_state = smu_set_clockgating_state,
2147 .set_powergating_state = smu_set_powergating_state,
2148 .enable_umd_pstate = smu_enable_umd_pstate,
2149 };
2150
2151 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2152 {
2153 .type = AMD_IP_BLOCK_TYPE_SMC,
2154 .major = 11,
2155 .minor = 0,
2156 .rev = 0,
2157 .funcs = &smu_ip_funcs,
2158 };
2159
2160 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2161 {
2162 .type = AMD_IP_BLOCK_TYPE_SMC,
2163 .major = 12,
2164 .minor = 0,
2165 .rev = 0,
2166 .funcs = &smu_ip_funcs,
2167 };
2168
2169 const struct amdgpu_ip_block_version smu_v13_0_ip_block =
2170 {
2171 .type = AMD_IP_BLOCK_TYPE_SMC,
2172 .major = 13,
2173 .minor = 0,
2174 .rev = 0,
2175 .funcs = &smu_ip_funcs,
2176 };
2177
smu_load_microcode(void * handle)2178 static int smu_load_microcode(void *handle)
2179 {
2180 struct smu_context *smu = handle;
2181 struct amdgpu_device *adev = smu->adev;
2182 int ret = 0;
2183
2184 if (!smu->pm_enabled)
2185 return -EOPNOTSUPP;
2186
2187 /* This should be used for non PSP loading */
2188 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2189 return 0;
2190
2191 if (smu->ppt_funcs->load_microcode) {
2192 ret = smu->ppt_funcs->load_microcode(smu);
2193 if (ret) {
2194 dev_err(adev->dev, "Load microcode failed\n");
2195 return ret;
2196 }
2197 }
2198
2199 if (smu->ppt_funcs->check_fw_status) {
2200 ret = smu->ppt_funcs->check_fw_status(smu);
2201 if (ret) {
2202 dev_err(adev->dev, "SMC is not ready\n");
2203 return ret;
2204 }
2205 }
2206
2207 return ret;
2208 }
2209
smu_set_gfx_cgpg(struct smu_context * smu,bool enabled)2210 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2211 {
2212 int ret = 0;
2213
2214 mutex_lock(&smu->mutex);
2215
2216 if (smu->ppt_funcs->set_gfx_cgpg)
2217 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2218
2219 mutex_unlock(&smu->mutex);
2220
2221 return ret;
2222 }
2223
smu_set_fan_speed_rpm(void * handle,uint32_t speed)2224 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2225 {
2226 struct smu_context *smu = handle;
2227 int ret = 0;
2228
2229 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2230 return -EOPNOTSUPP;
2231
2232 mutex_lock(&smu->mutex);
2233
2234 if (smu->ppt_funcs->set_fan_speed_rpm) {
2235 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2236 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2237 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2238 smu->user_dpm_profile.fan_speed_rpm = speed;
2239
2240 /* Override custom PWM setting as they cannot co-exist */
2241 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2242 smu->user_dpm_profile.fan_speed_pwm = 0;
2243 }
2244 }
2245
2246 mutex_unlock(&smu->mutex);
2247
2248 return ret;
2249 }
2250
2251 /**
2252 * smu_get_power_limit - Request one of the SMU Power Limits
2253 *
2254 * @handle: pointer to smu context
2255 * @limit: requested limit is written back to this variable
2256 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2257 * @pp_power_type: &pp_power_type type of power
2258 * Return: 0 on success, <0 on error
2259 *
2260 */
smu_get_power_limit(void * handle,uint32_t * limit,enum pp_power_limit_level pp_limit_level,enum pp_power_type pp_power_type)2261 int smu_get_power_limit(void *handle,
2262 uint32_t *limit,
2263 enum pp_power_limit_level pp_limit_level,
2264 enum pp_power_type pp_power_type)
2265 {
2266 struct smu_context *smu = handle;
2267 struct amdgpu_device *adev = smu->adev;
2268 enum smu_ppt_limit_level limit_level;
2269 uint32_t limit_type;
2270 int ret = 0;
2271
2272 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2273 return -EOPNOTSUPP;
2274
2275 switch(pp_power_type) {
2276 case PP_PWR_TYPE_SUSTAINED:
2277 limit_type = SMU_DEFAULT_PPT_LIMIT;
2278 break;
2279 case PP_PWR_TYPE_FAST:
2280 limit_type = SMU_FAST_PPT_LIMIT;
2281 break;
2282 default:
2283 return -EOPNOTSUPP;
2284 break;
2285 }
2286
2287 switch(pp_limit_level){
2288 case PP_PWR_LIMIT_CURRENT:
2289 limit_level = SMU_PPT_LIMIT_CURRENT;
2290 break;
2291 case PP_PWR_LIMIT_DEFAULT:
2292 limit_level = SMU_PPT_LIMIT_DEFAULT;
2293 break;
2294 case PP_PWR_LIMIT_MAX:
2295 limit_level = SMU_PPT_LIMIT_MAX;
2296 break;
2297 case PP_PWR_LIMIT_MIN:
2298 default:
2299 return -EOPNOTSUPP;
2300 break;
2301 }
2302
2303 mutex_lock(&smu->mutex);
2304
2305 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2306 if (smu->ppt_funcs->get_ppt_limit)
2307 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2308 } else {
2309 switch (limit_level) {
2310 case SMU_PPT_LIMIT_CURRENT:
2311 switch (adev->ip_versions[MP1_HWIP][0]) {
2312 case IP_VERSION(13, 0, 2):
2313 case IP_VERSION(11, 0, 7):
2314 case IP_VERSION(11, 0, 11):
2315 case IP_VERSION(11, 0, 12):
2316 case IP_VERSION(11, 0, 13):
2317 ret = smu_get_asic_power_limits(smu,
2318 &smu->current_power_limit,
2319 NULL,
2320 NULL);
2321 break;
2322 default:
2323 break;
2324 }
2325 *limit = smu->current_power_limit;
2326 break;
2327 case SMU_PPT_LIMIT_DEFAULT:
2328 *limit = smu->default_power_limit;
2329 break;
2330 case SMU_PPT_LIMIT_MAX:
2331 *limit = smu->max_power_limit;
2332 break;
2333 default:
2334 break;
2335 }
2336 }
2337
2338 mutex_unlock(&smu->mutex);
2339
2340 return ret;
2341 }
2342
smu_set_power_limit(void * handle,uint32_t limit)2343 static int smu_set_power_limit(void *handle, uint32_t limit)
2344 {
2345 struct smu_context *smu = handle;
2346 uint32_t limit_type = limit >> 24;
2347 int ret = 0;
2348
2349 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2350 return -EOPNOTSUPP;
2351
2352 mutex_lock(&smu->mutex);
2353
2354 limit &= (1<<24)-1;
2355 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2356 if (smu->ppt_funcs->set_power_limit) {
2357 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2358 goto out;
2359 }
2360
2361 if (limit > smu->max_power_limit) {
2362 dev_err(smu->adev->dev,
2363 "New power limit (%d) is over the max allowed %d\n",
2364 limit, smu->max_power_limit);
2365 ret = -EINVAL;
2366 goto out;
2367 }
2368
2369 if (!limit)
2370 limit = smu->current_power_limit;
2371
2372 if (smu->ppt_funcs->set_power_limit) {
2373 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2374 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2375 smu->user_dpm_profile.power_limit = limit;
2376 }
2377
2378 out:
2379 mutex_unlock(&smu->mutex);
2380
2381 return ret;
2382 }
2383
smu_print_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)2384 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2385 {
2386 int ret = 0;
2387
2388 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2389 return -EOPNOTSUPP;
2390
2391 mutex_lock(&smu->mutex);
2392
2393 if (smu->ppt_funcs->print_clk_levels)
2394 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2395
2396 mutex_unlock(&smu->mutex);
2397
2398 return ret;
2399 }
2400
smu_print_ppclk_levels(void * handle,enum pp_clock_type type,char * buf)2401 static int smu_print_ppclk_levels(void *handle,
2402 enum pp_clock_type type,
2403 char *buf)
2404 {
2405 struct smu_context *smu = handle;
2406 enum smu_clk_type clk_type;
2407
2408 switch (type) {
2409 case PP_SCLK:
2410 clk_type = SMU_SCLK; break;
2411 case PP_MCLK:
2412 clk_type = SMU_MCLK; break;
2413 case PP_PCIE:
2414 clk_type = SMU_PCIE; break;
2415 case PP_SOCCLK:
2416 clk_type = SMU_SOCCLK; break;
2417 case PP_FCLK:
2418 clk_type = SMU_FCLK; break;
2419 case PP_DCEFCLK:
2420 clk_type = SMU_DCEFCLK; break;
2421 case PP_VCLK:
2422 clk_type = SMU_VCLK; break;
2423 case PP_DCLK:
2424 clk_type = SMU_DCLK; break;
2425 case OD_SCLK:
2426 clk_type = SMU_OD_SCLK; break;
2427 case OD_MCLK:
2428 clk_type = SMU_OD_MCLK; break;
2429 case OD_VDDC_CURVE:
2430 clk_type = SMU_OD_VDDC_CURVE; break;
2431 case OD_RANGE:
2432 clk_type = SMU_OD_RANGE; break;
2433 case OD_VDDGFX_OFFSET:
2434 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2435 case OD_CCLK:
2436 clk_type = SMU_OD_CCLK; break;
2437 default:
2438 return -EINVAL;
2439 }
2440
2441 return smu_print_smuclk_levels(smu, clk_type, buf);
2442 }
2443
smu_od_edit_dpm_table(void * handle,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)2444 static int smu_od_edit_dpm_table(void *handle,
2445 enum PP_OD_DPM_TABLE_COMMAND type,
2446 long *input, uint32_t size)
2447 {
2448 struct smu_context *smu = handle;
2449 int ret = 0;
2450
2451 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2452 return -EOPNOTSUPP;
2453
2454 mutex_lock(&smu->mutex);
2455
2456 if (smu->ppt_funcs->od_edit_dpm_table) {
2457 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2458 }
2459
2460 mutex_unlock(&smu->mutex);
2461
2462 return ret;
2463 }
2464
smu_read_sensor(void * handle,int sensor,void * data,int * size_arg)2465 static int smu_read_sensor(void *handle,
2466 int sensor,
2467 void *data,
2468 int *size_arg)
2469 {
2470 struct smu_context *smu = handle;
2471 struct smu_umd_pstate_table *pstate_table =
2472 &smu->pstate_table;
2473 int ret = 0;
2474 uint32_t *size, size_val;
2475
2476 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2477 return -EOPNOTSUPP;
2478
2479 if (!data || !size_arg)
2480 return -EINVAL;
2481
2482 size_val = *size_arg;
2483 size = &size_val;
2484
2485 mutex_lock(&smu->mutex);
2486
2487 if (smu->ppt_funcs->read_sensor)
2488 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2489 goto unlock;
2490
2491 switch (sensor) {
2492 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2493 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2494 *size = 4;
2495 break;
2496 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2497 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2498 *size = 4;
2499 break;
2500 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2501 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2502 *size = 8;
2503 break;
2504 case AMDGPU_PP_SENSOR_UVD_POWER:
2505 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2506 *size = 4;
2507 break;
2508 case AMDGPU_PP_SENSOR_VCE_POWER:
2509 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2510 *size = 4;
2511 break;
2512 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2513 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2514 *size = 4;
2515 break;
2516 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2517 *(uint32_t *)data = 0;
2518 *size = 4;
2519 break;
2520 default:
2521 *size = 0;
2522 ret = -EOPNOTSUPP;
2523 break;
2524 }
2525
2526 unlock:
2527 mutex_unlock(&smu->mutex);
2528
2529 // assign uint32_t to int
2530 *size_arg = size_val;
2531
2532 return ret;
2533 }
2534
smu_get_power_profile_mode(void * handle,char * buf)2535 static int smu_get_power_profile_mode(void *handle, char *buf)
2536 {
2537 struct smu_context *smu = handle;
2538 int ret = 0;
2539
2540 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2541 !smu->ppt_funcs->get_power_profile_mode)
2542 return -EOPNOTSUPP;
2543 if (!buf)
2544 return -EINVAL;
2545
2546 mutex_lock(&smu->mutex);
2547
2548 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2549
2550 mutex_unlock(&smu->mutex);
2551
2552 return ret;
2553 }
2554
smu_set_power_profile_mode(void * handle,long * param,uint32_t param_size)2555 static int smu_set_power_profile_mode(void *handle,
2556 long *param,
2557 uint32_t param_size)
2558 {
2559 struct smu_context *smu = handle;
2560 int ret = 0;
2561
2562 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2563 !smu->ppt_funcs->set_power_profile_mode)
2564 return -EOPNOTSUPP;
2565
2566 mutex_lock(&smu->mutex);
2567
2568 smu_bump_power_profile_mode(smu, param, param_size);
2569
2570 mutex_unlock(&smu->mutex);
2571
2572 return ret;
2573 }
2574
2575
smu_get_fan_control_mode(void * handle)2576 static u32 smu_get_fan_control_mode(void *handle)
2577 {
2578 struct smu_context *smu = handle;
2579 u32 ret = 0;
2580
2581 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2582 return AMD_FAN_CTRL_NONE;
2583
2584 mutex_lock(&smu->mutex);
2585
2586 if (smu->ppt_funcs->get_fan_control_mode)
2587 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2588
2589 mutex_unlock(&smu->mutex);
2590
2591 return ret;
2592 }
2593
smu_set_fan_control_mode(struct smu_context * smu,int value)2594 static int smu_set_fan_control_mode(struct smu_context *smu, int value)
2595 {
2596 int ret = 0;
2597
2598 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2599 return -EOPNOTSUPP;
2600
2601 mutex_lock(&smu->mutex);
2602
2603 if (smu->ppt_funcs->set_fan_control_mode) {
2604 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2605 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2606 smu->user_dpm_profile.fan_mode = value;
2607 }
2608
2609 mutex_unlock(&smu->mutex);
2610
2611 /* reset user dpm fan speed */
2612 if (!ret && value != AMD_FAN_CTRL_MANUAL &&
2613 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2614 smu->user_dpm_profile.fan_speed_pwm = 0;
2615 smu->user_dpm_profile.fan_speed_rpm = 0;
2616 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
2617 }
2618
2619 return ret;
2620 }
2621
smu_pp_set_fan_control_mode(void * handle,u32 value)2622 static void smu_pp_set_fan_control_mode(void *handle, u32 value)
2623 {
2624 struct smu_context *smu = handle;
2625
2626 smu_set_fan_control_mode(smu, value);
2627 }
2628
2629
smu_get_fan_speed_pwm(void * handle,u32 * speed)2630 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
2631 {
2632 struct smu_context *smu = handle;
2633 int ret = 0;
2634
2635 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2636 return -EOPNOTSUPP;
2637
2638 mutex_lock(&smu->mutex);
2639
2640 if (smu->ppt_funcs->get_fan_speed_pwm)
2641 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
2642
2643 mutex_unlock(&smu->mutex);
2644
2645 return ret;
2646 }
2647
smu_set_fan_speed_pwm(void * handle,u32 speed)2648 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
2649 {
2650 struct smu_context *smu = handle;
2651 int ret = 0;
2652
2653 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2654 return -EOPNOTSUPP;
2655
2656 mutex_lock(&smu->mutex);
2657
2658 if (smu->ppt_funcs->set_fan_speed_pwm) {
2659 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
2660 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2661 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
2662 smu->user_dpm_profile.fan_speed_pwm = speed;
2663
2664 /* Override custom RPM setting as they cannot co-exist */
2665 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
2666 smu->user_dpm_profile.fan_speed_rpm = 0;
2667 }
2668 }
2669
2670 mutex_unlock(&smu->mutex);
2671
2672 return ret;
2673 }
2674
smu_get_fan_speed_rpm(void * handle,uint32_t * speed)2675 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2676 {
2677 struct smu_context *smu = handle;
2678 int ret = 0;
2679
2680 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2681 return -EOPNOTSUPP;
2682
2683 mutex_lock(&smu->mutex);
2684
2685 if (smu->ppt_funcs->get_fan_speed_rpm)
2686 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2687
2688 mutex_unlock(&smu->mutex);
2689
2690 return ret;
2691 }
2692
smu_set_deep_sleep_dcefclk(void * handle,uint32_t clk)2693 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2694 {
2695 struct smu_context *smu = handle;
2696 int ret = 0;
2697
2698 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2699 return -EOPNOTSUPP;
2700
2701 mutex_lock(&smu->mutex);
2702
2703 ret = smu_set_min_dcef_deep_sleep(smu, clk);
2704
2705 mutex_unlock(&smu->mutex);
2706
2707 return ret;
2708 }
2709
smu_get_clock_by_type_with_latency(void * handle,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)2710 static int smu_get_clock_by_type_with_latency(void *handle,
2711 enum amd_pp_clock_type type,
2712 struct pp_clock_levels_with_latency *clocks)
2713 {
2714 struct smu_context *smu = handle;
2715 enum smu_clk_type clk_type;
2716 int ret = 0;
2717
2718 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2719 return -EOPNOTSUPP;
2720
2721 mutex_lock(&smu->mutex);
2722
2723 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2724 switch (type) {
2725 case amd_pp_sys_clock:
2726 clk_type = SMU_GFXCLK;
2727 break;
2728 case amd_pp_mem_clock:
2729 clk_type = SMU_MCLK;
2730 break;
2731 case amd_pp_dcef_clock:
2732 clk_type = SMU_DCEFCLK;
2733 break;
2734 case amd_pp_disp_clock:
2735 clk_type = SMU_DISPCLK;
2736 break;
2737 default:
2738 dev_err(smu->adev->dev, "Invalid clock type!\n");
2739 mutex_unlock(&smu->mutex);
2740 return -EINVAL;
2741 }
2742
2743 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2744 }
2745
2746 mutex_unlock(&smu->mutex);
2747
2748 return ret;
2749 }
2750
smu_display_clock_voltage_request(void * handle,struct pp_display_clock_request * clock_req)2751 static int smu_display_clock_voltage_request(void *handle,
2752 struct pp_display_clock_request *clock_req)
2753 {
2754 struct smu_context *smu = handle;
2755 int ret = 0;
2756
2757 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2758 return -EOPNOTSUPP;
2759
2760 mutex_lock(&smu->mutex);
2761
2762 if (smu->ppt_funcs->display_clock_voltage_request)
2763 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2764
2765 mutex_unlock(&smu->mutex);
2766
2767 return ret;
2768 }
2769
2770
smu_display_disable_memory_clock_switch(void * handle,bool disable_memory_clock_switch)2771 static int smu_display_disable_memory_clock_switch(void *handle,
2772 bool disable_memory_clock_switch)
2773 {
2774 struct smu_context *smu = handle;
2775 int ret = -EINVAL;
2776
2777 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2778 return -EOPNOTSUPP;
2779
2780 mutex_lock(&smu->mutex);
2781
2782 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2783 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2784
2785 mutex_unlock(&smu->mutex);
2786
2787 return ret;
2788 }
2789
smu_set_xgmi_pstate(void * handle,uint32_t pstate)2790 static int smu_set_xgmi_pstate(void *handle,
2791 uint32_t pstate)
2792 {
2793 struct smu_context *smu = handle;
2794 int ret = 0;
2795
2796 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2797 return -EOPNOTSUPP;
2798
2799 mutex_lock(&smu->mutex);
2800
2801 if (smu->ppt_funcs->set_xgmi_pstate)
2802 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2803
2804 mutex_unlock(&smu->mutex);
2805
2806 if(ret)
2807 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2808
2809 return ret;
2810 }
2811
smu_get_baco_capability(void * handle,bool * cap)2812 static int smu_get_baco_capability(void *handle, bool *cap)
2813 {
2814 struct smu_context *smu = handle;
2815 int ret = 0;
2816
2817 *cap = false;
2818
2819 if (!smu->pm_enabled)
2820 return 0;
2821
2822 mutex_lock(&smu->mutex);
2823
2824 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2825 *cap = smu->ppt_funcs->baco_is_support(smu);
2826
2827 mutex_unlock(&smu->mutex);
2828
2829 return ret;
2830 }
2831
smu_baco_set_state(void * handle,int state)2832 static int smu_baco_set_state(void *handle, int state)
2833 {
2834 struct smu_context *smu = handle;
2835 int ret = 0;
2836
2837 if (!smu->pm_enabled)
2838 return -EOPNOTSUPP;
2839
2840 if (state == 0) {
2841 mutex_lock(&smu->mutex);
2842
2843 if (smu->ppt_funcs->baco_exit)
2844 ret = smu->ppt_funcs->baco_exit(smu);
2845
2846 mutex_unlock(&smu->mutex);
2847 } else if (state == 1) {
2848 mutex_lock(&smu->mutex);
2849
2850 if (smu->ppt_funcs->baco_enter)
2851 ret = smu->ppt_funcs->baco_enter(smu);
2852
2853 mutex_unlock(&smu->mutex);
2854
2855 } else {
2856 return -EINVAL;
2857 }
2858
2859 if (ret)
2860 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2861 (state)?"enter":"exit");
2862
2863 return ret;
2864 }
2865
smu_mode1_reset_is_support(struct smu_context * smu)2866 bool smu_mode1_reset_is_support(struct smu_context *smu)
2867 {
2868 bool ret = false;
2869
2870 if (!smu->pm_enabled)
2871 return false;
2872
2873 mutex_lock(&smu->mutex);
2874
2875 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2876 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2877
2878 mutex_unlock(&smu->mutex);
2879
2880 return ret;
2881 }
2882
smu_mode2_reset_is_support(struct smu_context * smu)2883 bool smu_mode2_reset_is_support(struct smu_context *smu)
2884 {
2885 bool ret = false;
2886
2887 if (!smu->pm_enabled)
2888 return false;
2889
2890 mutex_lock(&smu->mutex);
2891
2892 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2893 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2894
2895 mutex_unlock(&smu->mutex);
2896
2897 return ret;
2898 }
2899
smu_mode1_reset(struct smu_context * smu)2900 int smu_mode1_reset(struct smu_context *smu)
2901 {
2902 int ret = 0;
2903
2904 if (!smu->pm_enabled)
2905 return -EOPNOTSUPP;
2906
2907 mutex_lock(&smu->mutex);
2908
2909 if (smu->ppt_funcs->mode1_reset)
2910 ret = smu->ppt_funcs->mode1_reset(smu);
2911
2912 mutex_unlock(&smu->mutex);
2913
2914 return ret;
2915 }
2916
smu_mode2_reset(void * handle)2917 static int smu_mode2_reset(void *handle)
2918 {
2919 struct smu_context *smu = handle;
2920 int ret = 0;
2921
2922 if (!smu->pm_enabled)
2923 return -EOPNOTSUPP;
2924
2925 mutex_lock(&smu->mutex);
2926
2927 if (smu->ppt_funcs->mode2_reset)
2928 ret = smu->ppt_funcs->mode2_reset(smu);
2929
2930 mutex_unlock(&smu->mutex);
2931
2932 if (ret)
2933 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2934
2935 return ret;
2936 }
2937
smu_get_max_sustainable_clocks_by_dc(void * handle,struct pp_smu_nv_clock_table * max_clocks)2938 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2939 struct pp_smu_nv_clock_table *max_clocks)
2940 {
2941 struct smu_context *smu = handle;
2942 int ret = 0;
2943
2944 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2945 return -EOPNOTSUPP;
2946
2947 mutex_lock(&smu->mutex);
2948
2949 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2950 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2951
2952 mutex_unlock(&smu->mutex);
2953
2954 return ret;
2955 }
2956
smu_get_uclk_dpm_states(void * handle,unsigned int * clock_values_in_khz,unsigned int * num_states)2957 static int smu_get_uclk_dpm_states(void *handle,
2958 unsigned int *clock_values_in_khz,
2959 unsigned int *num_states)
2960 {
2961 struct smu_context *smu = handle;
2962 int ret = 0;
2963
2964 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2965 return -EOPNOTSUPP;
2966
2967 mutex_lock(&smu->mutex);
2968
2969 if (smu->ppt_funcs->get_uclk_dpm_states)
2970 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2971
2972 mutex_unlock(&smu->mutex);
2973
2974 return ret;
2975 }
2976
smu_get_current_power_state(void * handle)2977 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
2978 {
2979 struct smu_context *smu = handle;
2980 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2981
2982 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2983 return -EOPNOTSUPP;
2984
2985 mutex_lock(&smu->mutex);
2986
2987 if (smu->ppt_funcs->get_current_power_state)
2988 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2989
2990 mutex_unlock(&smu->mutex);
2991
2992 return pm_state;
2993 }
2994
smu_get_dpm_clock_table(void * handle,struct dpm_clocks * clock_table)2995 static int smu_get_dpm_clock_table(void *handle,
2996 struct dpm_clocks *clock_table)
2997 {
2998 struct smu_context *smu = handle;
2999 int ret = 0;
3000
3001 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3002 return -EOPNOTSUPP;
3003
3004 mutex_lock(&smu->mutex);
3005
3006 if (smu->ppt_funcs->get_dpm_clock_table)
3007 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
3008
3009 mutex_unlock(&smu->mutex);
3010
3011 return ret;
3012 }
3013
smu_sys_get_gpu_metrics(void * handle,void ** table)3014 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
3015 {
3016 struct smu_context *smu = handle;
3017 ssize_t size;
3018
3019 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3020 return -EOPNOTSUPP;
3021
3022 if (!smu->ppt_funcs->get_gpu_metrics)
3023 return -EOPNOTSUPP;
3024
3025 mutex_lock(&smu->mutex);
3026
3027 size = smu->ppt_funcs->get_gpu_metrics(smu, table);
3028
3029 mutex_unlock(&smu->mutex);
3030
3031 return size;
3032 }
3033
smu_enable_mgpu_fan_boost(void * handle)3034 static int smu_enable_mgpu_fan_boost(void *handle)
3035 {
3036 struct smu_context *smu = handle;
3037 int ret = 0;
3038
3039 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3040 return -EOPNOTSUPP;
3041
3042 mutex_lock(&smu->mutex);
3043
3044 if (smu->ppt_funcs->enable_mgpu_fan_boost)
3045 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
3046
3047 mutex_unlock(&smu->mutex);
3048
3049 return ret;
3050 }
3051
smu_gfx_state_change_set(void * handle,uint32_t state)3052 static int smu_gfx_state_change_set(void *handle,
3053 uint32_t state)
3054 {
3055 struct smu_context *smu = handle;
3056 int ret = 0;
3057
3058 mutex_lock(&smu->mutex);
3059 if (smu->ppt_funcs->gfx_state_change_set)
3060 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
3061 mutex_unlock(&smu->mutex);
3062
3063 return ret;
3064 }
3065
smu_set_light_sbr(struct smu_context * smu,bool enable)3066 int smu_set_light_sbr(struct smu_context *smu, bool enable)
3067 {
3068 int ret = 0;
3069
3070 mutex_lock(&smu->mutex);
3071 if (smu->ppt_funcs->set_light_sbr)
3072 ret = smu->ppt_funcs->set_light_sbr(smu, enable);
3073 mutex_unlock(&smu->mutex);
3074
3075 return ret;
3076 }
3077
smu_get_prv_buffer_details(void * handle,void ** addr,size_t * size)3078 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3079 {
3080 struct smu_context *smu = handle;
3081 struct smu_table_context *smu_table = &smu->smu_table;
3082 struct smu_table *memory_pool = &smu_table->memory_pool;
3083
3084 if (!addr || !size)
3085 return -EINVAL;
3086
3087 *addr = NULL;
3088 *size = 0;
3089 mutex_lock(&smu->mutex);
3090 if (memory_pool->bo) {
3091 *addr = memory_pool->cpu_addr;
3092 *size = memory_pool->size;
3093 }
3094 mutex_unlock(&smu->mutex);
3095
3096 return 0;
3097 }
3098
3099 static const struct amd_pm_funcs swsmu_pm_funcs = {
3100 /* export for sysfs */
3101 .set_fan_control_mode = smu_pp_set_fan_control_mode,
3102 .get_fan_control_mode = smu_get_fan_control_mode,
3103 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
3104 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
3105 .force_clock_level = smu_force_ppclk_levels,
3106 .print_clock_levels = smu_print_ppclk_levels,
3107 .force_performance_level = smu_force_performance_level,
3108 .read_sensor = smu_read_sensor,
3109 .get_performance_level = smu_get_performance_level,
3110 .get_current_power_state = smu_get_current_power_state,
3111 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
3112 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
3113 .get_pp_num_states = smu_get_power_num_states,
3114 .get_pp_table = smu_sys_get_pp_table,
3115 .set_pp_table = smu_sys_set_pp_table,
3116 .switch_power_profile = smu_switch_power_profile,
3117 /* export to amdgpu */
3118 .dispatch_tasks = smu_handle_dpm_task,
3119 .load_firmware = smu_load_microcode,
3120 .set_powergating_by_smu = smu_dpm_set_power_gate,
3121 .set_power_limit = smu_set_power_limit,
3122 .get_power_limit = smu_get_power_limit,
3123 .get_power_profile_mode = smu_get_power_profile_mode,
3124 .set_power_profile_mode = smu_set_power_profile_mode,
3125 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3126 .set_mp1_state = smu_set_mp1_state,
3127 .gfx_state_change_set = smu_gfx_state_change_set,
3128 /* export to DC */
3129 .get_sclk = smu_get_sclk,
3130 .get_mclk = smu_get_mclk,
3131 .display_configuration_change = smu_display_configuration_change,
3132 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3133 .display_clock_voltage_request = smu_display_clock_voltage_request,
3134 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3135 .set_active_display_count = smu_set_display_count,
3136 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3137 .get_asic_baco_capability = smu_get_baco_capability,
3138 .set_asic_baco_state = smu_baco_set_state,
3139 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3140 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3141 .asic_reset_mode_2 = smu_mode2_reset,
3142 .set_df_cstate = smu_set_df_cstate,
3143 .set_xgmi_pstate = smu_set_xgmi_pstate,
3144 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3145 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3146 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3147 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3148 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3149 .get_dpm_clock_table = smu_get_dpm_clock_table,
3150 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3151 };
3152
smu_wait_for_event(struct amdgpu_device * adev,enum smu_event_type event,uint64_t event_arg)3153 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
3154 uint64_t event_arg)
3155 {
3156 int ret = -EINVAL;
3157 struct smu_context *smu = &adev->smu;
3158
3159 if (smu->ppt_funcs->wait_for_event) {
3160 mutex_lock(&smu->mutex);
3161 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3162 mutex_unlock(&smu->mutex);
3163 }
3164
3165 return ret;
3166 }
3167