1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "smuio/smuio_11_0_0_offset.h"
25 #include "smuio/smuio_11_0_0_sh_mask.h"
26 
27 #include "smu_v11_0_i2c.h"
28 #include "amdgpu.h"
29 #include "soc15_common.h"
30 #include <drm/drm_fixed.h>
31 #include <drm/drm_drv.h>
32 #include "amdgpu_amdkfd.h"
33 #include <linux/i2c.h>
34 #include <linux/pci.h>
35 
36 /* error codes */
37 #define I2C_OK                0
38 #define I2C_NAK_7B_ADDR_NOACK 1
39 #define I2C_NAK_TXDATA_NOACK  2
40 #define I2C_TIMEOUT           4
41 #define I2C_SW_TIMEOUT        8
42 #define I2C_ABORT             0x10
43 
44 #define I2C_X_RESTART         BIT(31)
45 
46 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
47 
smu_v11_0_i2c_set_clock_gating(struct i2c_adapter * control,bool en)48 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
49 {
50 	struct amdgpu_device *adev = to_amdgpu_device(control);
51 	uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
52 
53 	reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
54 	WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
55 }
56 
57 /* The T_I2C_POLL_US is defined as follows:
58  *
59  * "Define a timer interval (t_i2c_poll) equal to 10 times the
60  *  signalling period for the highest I2C transfer speed used in the
61  *  system and supported by DW_apb_i2c. For instance, if the highest
62  *  I2C data transfer mode is 400 kb/s, then t_i2c_poll is 25 us."  --
63  * DesignWare DW_apb_i2c Databook, Version 1.21a, section 3.8.3.1,
64  * page 56, with grammar and syntax corrections.
65  *
66  * Vcc for our device is at 1.8V which puts it at 400 kHz,
67  * see Atmel AT24CM02 datasheet, section 8.3 DC Characteristics table, page 14.
68  *
69  * The procedure to disable the IP block is described in section
70  * 3.8.3 Disabling DW_apb_i2c on page 56.
71  */
72 #define I2C_SPEED_MODE_FAST     2
73 #define T_I2C_POLL_US           25
74 #define I2C_MAX_T_POLL_COUNT    1000
75 
smu_v11_0_i2c_enable(struct i2c_adapter * control,bool enable)76 static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
77 {
78 	struct amdgpu_device *adev = to_amdgpu_device(control);
79 
80 	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
81 
82 	if (!enable) {
83 		int ii;
84 
85 		for (ii = I2C_MAX_T_POLL_COUNT; ii > 0; ii--) {
86 			u32 en_stat = RREG32_SOC15(SMUIO,
87 						   0,
88 						   mmCKSVII2C_IC_ENABLE_STATUS);
89 			if (REG_GET_FIELD(en_stat, CKSVII2C_IC_ENABLE_STATUS, IC_EN))
90 				udelay(T_I2C_POLL_US);
91 			else
92 				return I2C_OK;
93 		}
94 
95 		return I2C_ABORT;
96 	}
97 
98 	return I2C_OK;
99 }
100 
smu_v11_0_i2c_clear_status(struct i2c_adapter * control)101 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control)
102 {
103 	struct amdgpu_device *adev = to_amdgpu_device(control);
104 	/* do */
105 	{
106 		RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
107 
108 	} /* while (reg_CKSVII2C_ic_clr_intr == 0) */
109 }
110 
smu_v11_0_i2c_configure(struct i2c_adapter * control)111 static void smu_v11_0_i2c_configure(struct i2c_adapter *control)
112 {
113 	struct amdgpu_device *adev = to_amdgpu_device(control);
114 	uint32_t reg = 0;
115 
116 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
117 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
118 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
119 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
120 	/* The values of IC_MAX_SPEED_MODE are,
121 	 * 1: standard mode, 0 - 100 Kb/s,
122 	 * 2: fast mode, <= 400 Kb/s, or fast mode plus, <= 1000 Kb/s,
123 	 * 3: high speed mode, <= 3.4 Mb/s.
124 	 */
125 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE,
126 			    I2C_SPEED_MODE_FAST);
127 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
128 
129 	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg);
130 }
131 
smu_v11_0_i2c_set_clock(struct i2c_adapter * control)132 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control)
133 {
134 	struct amdgpu_device *adev = to_amdgpu_device(control);
135 
136 	/*
137 	 * Standard mode speed, These values are taken from SMUIO MAS,
138 	 * but are different from what is given is
139 	 * Synopsys spec. The values here are based on assumption
140 	 * that refclock is 100MHz
141 	 *
142 	 * Configuration for standard mode; Speed = 100kbps
143 	 * Scale linearly, for now only support standard speed clock
144 	 * This will work only with 100M ref clock
145 	 *
146 	 * TBD:Change the calculation to take into account ref clock values also.
147 	 */
148 
149 	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2);
150 	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120);
151 	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130);
152 	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20);
153 }
154 
smu_v11_0_i2c_set_address(struct i2c_adapter * control,u16 address)155 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, u16 address)
156 {
157 	struct amdgpu_device *adev = to_amdgpu_device(control);
158 
159 	/* The IC_TAR::IC_TAR field is 10-bits wide.
160 	 * It takes a 7-bit or 10-bit addresses as an address,
161 	 * i.e. no read/write bit--no wire format, just the address.
162 	 */
163 	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, address & 0x3FF);
164 }
165 
smu_v11_0_i2c_poll_tx_status(struct i2c_adapter * control)166 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
167 {
168 	struct amdgpu_device *adev = to_amdgpu_device(control);
169 	uint32_t ret = I2C_OK;
170 	uint32_t reg, reg_c_tx_abrt_source;
171 
172 	/*Check if transmission is completed */
173 	unsigned long  timeout_counter = jiffies + msecs_to_jiffies(20);
174 
175 	do {
176 		if (time_after(jiffies, timeout_counter)) {
177 			ret |= I2C_SW_TIMEOUT;
178 			break;
179 		}
180 
181 		reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
182 
183 	} while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
184 
185 	if (ret != I2C_OK)
186 		return ret;
187 
188 	/* This only checks if NAK is received and transaction got aborted */
189 	reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
190 
191 	if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
192 		reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
193 		DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source);
194 
195 		/* Check for stop due to NACK */
196 		if (REG_GET_FIELD(reg_c_tx_abrt_source,
197 				  CKSVII2C_IC_TX_ABRT_SOURCE,
198 				  ABRT_TXDATA_NOACK) == 1) {
199 
200 			ret |= I2C_NAK_TXDATA_NOACK;
201 
202 		} else if (REG_GET_FIELD(reg_c_tx_abrt_source,
203 					 CKSVII2C_IC_TX_ABRT_SOURCE,
204 					 ABRT_7B_ADDR_NOACK) == 1) {
205 
206 			ret |= I2C_NAK_7B_ADDR_NOACK;
207 		} else {
208 			ret |= I2C_ABORT;
209 		}
210 
211 		smu_v11_0_i2c_clear_status(control);
212 	}
213 
214 	return ret;
215 }
216 
smu_v11_0_i2c_poll_rx_status(struct i2c_adapter * control)217 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)
218 {
219 	struct amdgpu_device *adev = to_amdgpu_device(control);
220 	uint32_t ret = I2C_OK;
221 	uint32_t reg_ic_status, reg_c_tx_abrt_source;
222 
223 	reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
224 
225 	/* If slave is not present */
226 	if (REG_GET_FIELD(reg_c_tx_abrt_source,
227 			  CKSVII2C_IC_TX_ABRT_SOURCE,
228 			  ABRT_7B_ADDR_NOACK) == 1) {
229 		ret |= I2C_NAK_7B_ADDR_NOACK;
230 
231 		smu_v11_0_i2c_clear_status(control);
232 	} else {  /* wait till some data is there in RXFIFO */
233 		/* Poll for some byte in RXFIFO */
234 		unsigned long  timeout_counter = jiffies + msecs_to_jiffies(20);
235 
236 		do {
237 			if (time_after(jiffies, timeout_counter)) {
238 				ret |= I2C_SW_TIMEOUT;
239 				break;
240 			}
241 
242 			reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
243 
244 		} while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
245 	}
246 
247 	return ret;
248 }
249 
250 /**
251  * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device.
252  *
253  * @control: I2C adapter reference
254  * @address: The I2C address of the slave device.
255  * @data: The data to transmit over the bus.
256  * @numbytes: The amount of data to transmit.
257  * @i2c_flag: Flags for transmission
258  *
259  * Returns 0 on success or error.
260  */
smu_v11_0_i2c_transmit(struct i2c_adapter * control,u16 address,u8 * data,u32 numbytes,u32 i2c_flag)261 static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,
262 				       u16 address, u8 *data,
263 				       u32 numbytes, u32 i2c_flag)
264 {
265 	struct amdgpu_device *adev = to_amdgpu_device(control);
266 	u32 bytes_sent, reg, ret = I2C_OK;
267 	unsigned long  timeout_counter;
268 
269 	bytes_sent = 0;
270 
271 	DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
272 			 address, numbytes);
273 
274 	if (drm_debug_enabled(DRM_UT_DRIVER)) {
275 		print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
276 			       16, 1, data, numbytes, false);
277 	}
278 
279 	/* Set the I2C slave address */
280 	smu_v11_0_i2c_set_address(control, address);
281 	/* Enable I2C */
282 	smu_v11_0_i2c_enable(control, true);
283 
284 	/* Clear status bits */
285 	smu_v11_0_i2c_clear_status(control);
286 
287 	timeout_counter = jiffies + msecs_to_jiffies(20);
288 
289 	while (numbytes > 0) {
290 		reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
291 		if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
292 			/*
293 			 * We waited for too long for the transmission
294 			 * FIFO to become not-full.  Exit the loop
295 			 * with error.
296 			 */
297 			if (time_after(jiffies, timeout_counter)) {
298 				ret |= I2C_SW_TIMEOUT;
299 				goto Err;
300 			}
301 		} else {
302 			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT,
303 					    data[bytes_sent]);
304 
305 			/* Final message, final byte, must generate a
306 			 * STOP to release the bus, i.e. don't hold
307 			 * SCL low.
308 			 */
309 			if (numbytes == 1 && i2c_flag & I2C_M_STOP)
310 				reg = REG_SET_FIELD(reg,
311 						    CKSVII2C_IC_DATA_CMD,
312 						    STOP, 1);
313 
314 			if (bytes_sent == 0 && i2c_flag & I2C_X_RESTART)
315 				reg = REG_SET_FIELD(reg,
316 						    CKSVII2C_IC_DATA_CMD,
317 						    RESTART, 1);
318 
319 			/* Write */
320 			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
321 			WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
322 
323 			/* Record that the bytes were transmitted */
324 			bytes_sent++;
325 			numbytes--;
326 		}
327 	}
328 
329 	ret = smu_v11_0_i2c_poll_tx_status(control);
330 Err:
331 	/* Any error, no point in proceeding */
332 	if (ret != I2C_OK) {
333 		if (ret & I2C_SW_TIMEOUT)
334 			DRM_ERROR("TIMEOUT ERROR !!!");
335 
336 		if (ret & I2C_NAK_7B_ADDR_NOACK)
337 			DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
338 
339 
340 		if (ret & I2C_NAK_TXDATA_NOACK)
341 			DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
342 	}
343 
344 	return ret;
345 }
346 
347 
348 /**
349  * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device.
350  *
351  * @control: I2C adapter reference
352  * @address: The I2C address of the slave device.
353  * @data: Placeholder to store received data.
354  * @numbytes: The amount of data to transmit.
355  * @i2c_flag: Flags for transmission
356  *
357  * Returns 0 on success or error.
358  */
smu_v11_0_i2c_receive(struct i2c_adapter * control,u16 address,u8 * data,u32 numbytes,u32 i2c_flag)359 static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,
360 				      u16 address, u8 *data,
361 				      u32 numbytes, u32 i2c_flag)
362 {
363 	struct amdgpu_device *adev = to_amdgpu_device(control);
364 	uint32_t bytes_received, ret = I2C_OK;
365 
366 	bytes_received = 0;
367 
368 	/* Set the I2C slave address */
369 	smu_v11_0_i2c_set_address(control, address);
370 
371 	/* Enable I2C */
372 	smu_v11_0_i2c_enable(control, true);
373 
374 	while (numbytes > 0) {
375 		uint32_t reg = 0;
376 
377 		smu_v11_0_i2c_clear_status(control);
378 
379 		/* Prepare transaction */
380 		reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
381 		/* Read */
382 		reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
383 
384 		/* Final message, final byte, must generate a STOP
385 		 * to release the bus, i.e. don't hold SCL low.
386 		 */
387 		if (numbytes == 1 && i2c_flag & I2C_M_STOP)
388 			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,
389 					    STOP, 1);
390 
391 		if (bytes_received == 0 && i2c_flag & I2C_X_RESTART)
392 			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,
393 					    RESTART, 1);
394 
395 		WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
396 
397 		ret = smu_v11_0_i2c_poll_rx_status(control);
398 
399 		/* Any error, no point in proceeding */
400 		if (ret != I2C_OK) {
401 			if (ret & I2C_SW_TIMEOUT)
402 				DRM_ERROR("TIMEOUT ERROR !!!");
403 
404 			if (ret & I2C_NAK_7B_ADDR_NOACK)
405 				DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
406 
407 			if (ret & I2C_NAK_TXDATA_NOACK)
408 				DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
409 
410 			break;
411 		}
412 
413 		reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);
414 		data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
415 
416 		/* Record that the bytes were received */
417 		bytes_received++;
418 		numbytes--;
419 	}
420 
421 	DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
422 		  (uint16_t)address, bytes_received);
423 
424 	if (drm_debug_enabled(DRM_UT_DRIVER)) {
425 		print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
426 			       16, 1, data, bytes_received, false);
427 	}
428 
429 	return ret;
430 }
431 
smu_v11_0_i2c_abort(struct i2c_adapter * control)432 static void smu_v11_0_i2c_abort(struct i2c_adapter *control)
433 {
434 	struct amdgpu_device *adev = to_amdgpu_device(control);
435 	uint32_t reg = 0;
436 
437 	/* Enable I2C engine; */
438 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
439 	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
440 
441 	/* Abort previous transaction */
442 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
443 	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
444 
445 	DRM_DEBUG_DRIVER("I2C_Abort() Done.");
446 }
447 
smu_v11_0_i2c_activity_done(struct i2c_adapter * control)448 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
449 {
450 	struct amdgpu_device *adev = to_amdgpu_device(control);
451 
452 	const uint32_t IDLE_TIMEOUT = 1024;
453 	uint32_t timeout_count = 0;
454 	uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity;
455 
456 	reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
457 	reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
458 
459 	if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
460 	    (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
461 		/*
462 		 * Nobody is using I2C engine, but engine remains active because
463 		 * someone missed to send STOP
464 		 */
465 		smu_v11_0_i2c_abort(control);
466 	} else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
467 		/* Nobody is using I2C engine */
468 		return true;
469 	}
470 
471 	/* Keep reading activity bit until it's cleared */
472 	do {
473 		reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);
474 
475 		if (REG_GET_FIELD(reg_ic_clr_activity,
476 		    CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0)
477 			return true;
478 
479 		++timeout_count;
480 
481 	} while (timeout_count < IDLE_TIMEOUT);
482 
483 	return false;
484 }
485 
smu_v11_0_i2c_init(struct i2c_adapter * control)486 static void smu_v11_0_i2c_init(struct i2c_adapter *control)
487 {
488 	int res;
489 
490 	/* Disable clock gating */
491 	smu_v11_0_i2c_set_clock_gating(control, false);
492 
493 	if (!smu_v11_0_i2c_activity_done(control))
494 		DRM_WARN("I2C busy !");
495 
496 	/* Disable I2C */
497 	res = smu_v11_0_i2c_enable(control, false);
498 	if (res != I2C_OK)
499 		smu_v11_0_i2c_abort(control);
500 
501 	/* Configure I2C to operate as master and in standard mode */
502 	smu_v11_0_i2c_configure(control);
503 
504 	/* Initialize the clock to 50 kHz default */
505 	smu_v11_0_i2c_set_clock(control);
506 
507 }
508 
smu_v11_0_i2c_fini(struct i2c_adapter * control)509 static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
510 {
511 	struct amdgpu_device *adev = to_amdgpu_device(control);
512 	u32 status, enable, en_stat;
513 	int res;
514 
515 	res = smu_v11_0_i2c_enable(control, false);
516 	if (res != I2C_OK) {
517 		status  = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
518 		enable  = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
519 		en_stat = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
520 
521 		/* Nobody is using the I2C engine, yet it remains
522 		 * active, possibly because someone missed to send
523 		 * STOP.
524 		 */
525 		DRM_DEBUG_DRIVER("Aborting from fini: status:0x%08x "
526 				 "enable:0x%08x enable_stat:0x%08x",
527 				 status, enable, en_stat);
528 		smu_v11_0_i2c_abort(control);
529 	}
530 
531 	/* Restore clock gating */
532 
533 	/*
534 	 * TODO Reenabling clock gating seems to break subsequent SMU operation
535 	 *      on the I2C bus. My guess is that SMU doesn't disable clock gating like
536 	 *      we do here before working with the bus. So for now just don't restore
537 	 *      it but later work with SMU to see if they have this issue and can
538 	 *      update their code appropriately
539 	 */
540 	/* smu_v11_0_i2c_set_clock_gating(control, true); */
541 
542 }
543 
smu_v11_0_i2c_bus_lock(struct i2c_adapter * control)544 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
545 {
546 	struct amdgpu_device *adev = to_amdgpu_device(control);
547 
548 	/* Send  PPSMC_MSG_RequestI2CBus */
549 	if (!amdgpu_dpm_smu_i2c_bus_access(adev, true))
550 		return true;
551 
552 	return false;
553 }
554 
smu_v11_0_i2c_bus_unlock(struct i2c_adapter * control)555 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
556 {
557 	struct amdgpu_device *adev = to_amdgpu_device(control);
558 
559 	/* Send  PPSMC_MSG_ReleaseI2CBus */
560 	if (!amdgpu_dpm_smu_i2c_bus_access(adev, false))
561 		return true;
562 
563 	return false;
564 }
565 
566 /***************************** I2C GLUE ****************************/
567 
smu_v11_0_i2c_read_data(struct i2c_adapter * control,struct i2c_msg * msg,uint32_t i2c_flag)568 static uint32_t smu_v11_0_i2c_read_data(struct i2c_adapter *control,
569 					struct i2c_msg *msg, uint32_t i2c_flag)
570 {
571 	uint32_t  ret;
572 
573 	ret = smu_v11_0_i2c_receive(control, msg->addr, msg->buf, msg->len, i2c_flag);
574 
575 	if (ret != I2C_OK)
576 		DRM_ERROR("ReadData() - I2C error occurred :%x", ret);
577 
578 	return ret;
579 }
580 
smu_v11_0_i2c_write_data(struct i2c_adapter * control,struct i2c_msg * msg,uint32_t i2c_flag)581 static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control,
582 					struct i2c_msg *msg, uint32_t i2c_flag)
583 {
584 	uint32_t  ret;
585 
586 	ret = smu_v11_0_i2c_transmit(control, msg->addr, msg->buf, msg->len, i2c_flag);
587 
588 	if (ret != I2C_OK)
589 		DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
590 
591 	return ret;
592 
593 }
594 
lock_bus(struct i2c_adapter * i2c,unsigned int flags)595 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
596 {
597 	struct amdgpu_device *adev = to_amdgpu_device(i2c);
598 
599 	mutex_lock(&adev->pm.smu_i2c_mutex);
600 	if (!smu_v11_0_i2c_bus_lock(i2c))
601 		DRM_ERROR("Failed to lock the bus from SMU");
602 	else
603 		adev->pm.bus_locked = true;
604 }
605 
trylock_bus(struct i2c_adapter * i2c,unsigned int flags)606 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
607 {
608 	WARN_ONCE(1, "This operation not supposed to run in atomic context!");
609 	return false;
610 }
611 
unlock_bus(struct i2c_adapter * i2c,unsigned int flags)612 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
613 {
614 	struct amdgpu_device *adev = to_amdgpu_device(i2c);
615 
616 	if (!smu_v11_0_i2c_bus_unlock(i2c))
617 		DRM_ERROR("Failed to unlock the bus from SMU");
618 	else
619 		adev->pm.bus_locked = false;
620 	mutex_unlock(&adev->pm.smu_i2c_mutex);
621 }
622 
623 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = {
624 	.lock_bus = lock_bus,
625 	.trylock_bus = trylock_bus,
626 	.unlock_bus = unlock_bus,
627 };
628 
smu_v11_0_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num)629 static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap,
630 			      struct i2c_msg *msg, int num)
631 {
632 	int i, ret;
633 	u16 addr, dir;
634 
635 	smu_v11_0_i2c_init(i2c_adap);
636 
637 	/* From the client's point of view, this sequence of
638 	 * messages-- the array i2c_msg *msg, is a single transaction
639 	 * on the bus, starting with START and ending with STOP.
640 	 *
641 	 * The client is welcome to send any sequence of messages in
642 	 * this array, as processing under this function here is
643 	 * striving to be agnostic.
644 	 *
645 	 * Record the first address and direction we see. If either
646 	 * changes for a subsequent message, generate ReSTART. The
647 	 * DW_apb_i2c databook, v1.21a, specifies that ReSTART is
648 	 * generated when the direction changes, with the default IP
649 	 * block parameter settings, but it doesn't specify if ReSTART
650 	 * is generated when the address changes (possibly...). We
651 	 * don't rely on the default IP block parameter settings as
652 	 * the block is shared and they may change.
653 	 */
654 	if (num > 0) {
655 		addr = msg[0].addr;
656 		dir  = msg[0].flags & I2C_M_RD;
657 	}
658 
659 	for (i = 0; i < num; i++) {
660 		u32 i2c_flag = 0;
661 
662 		if (msg[i].addr != addr || (msg[i].flags ^ dir) & I2C_M_RD) {
663 			addr = msg[i].addr;
664 			dir  = msg[i].flags & I2C_M_RD;
665 			i2c_flag |= I2C_X_RESTART;
666 		}
667 
668 		if (i == num - 1) {
669 			/* Set the STOP bit on the last message, so
670 			 * that the IP block generates a STOP after
671 			 * the last byte of the message.
672 			 */
673 			i2c_flag |= I2C_M_STOP;
674 		}
675 
676 		if (msg[i].flags & I2C_M_RD)
677 			ret = smu_v11_0_i2c_read_data(i2c_adap,
678 						      msg + i,
679 						      i2c_flag);
680 		else
681 			ret = smu_v11_0_i2c_write_data(i2c_adap,
682 						       msg + i,
683 						       i2c_flag);
684 
685 		if (ret != I2C_OK) {
686 			num = -EIO;
687 			break;
688 		}
689 	}
690 
691 	smu_v11_0_i2c_fini(i2c_adap);
692 	return num;
693 }
694 
smu_v11_0_i2c_func(struct i2c_adapter * adap)695 static u32 smu_v11_0_i2c_func(struct i2c_adapter *adap)
696 {
697 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
698 }
699 
700 static const struct i2c_algorithm smu_v11_0_i2c_algo = {
701 	.master_xfer = smu_v11_0_i2c_xfer,
702 	.functionality = smu_v11_0_i2c_func,
703 };
704 
705 static const struct i2c_adapter_quirks smu_v11_0_i2c_control_quirks = {
706 	.flags = I2C_AQ_NO_ZERO_LEN,
707 };
708 
smu_v11_0_i2c_control_init(struct i2c_adapter * control)709 int smu_v11_0_i2c_control_init(struct i2c_adapter *control)
710 {
711 	struct amdgpu_device *adev = to_amdgpu_device(control);
712 	int res;
713 
714 	mutex_init(&adev->pm.smu_i2c_mutex);
715 	control->owner = THIS_MODULE;
716 	control->class = I2C_CLASS_HWMON;
717 	control->dev.parent = &adev->pdev->dev;
718 	control->algo = &smu_v11_0_i2c_algo;
719 	snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
720 	control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops;
721 	control->quirks = &smu_v11_0_i2c_control_quirks;
722 
723 	res = i2c_add_adapter(control);
724 	if (res)
725 		DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
726 
727 	return res;
728 }
729 
smu_v11_0_i2c_control_fini(struct i2c_adapter * control)730 void smu_v11_0_i2c_control_fini(struct i2c_adapter *control)
731 {
732 	i2c_del_adapter(control);
733 }
734 
735 /*
736  * Keep this for future unit test if bugs arise
737  */
738 #if 0
739 #define I2C_TARGET_ADDR 0xA0
740 
741 bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control)
742 {
743 
744 	uint32_t ret = I2C_OK;
745 	uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef};
746 
747 
748 	DRM_INFO("Begin");
749 
750 	if (!smu_v11_0_i2c_bus_lock(control)) {
751 		DRM_ERROR("Failed to lock the bus!.");
752 		return false;
753 	}
754 
755 	smu_v11_0_i2c_init(control);
756 
757 	/* Write 0xde to address 0x0000 on the EEPROM */
758 	ret = smu_v11_0_i2c_write_data(control, I2C_TARGET_ADDR, data, 6);
759 
760 	ret = smu_v11_0_i2c_read_data(control, I2C_TARGET_ADDR, data, 6);
761 
762 	smu_v11_0_i2c_fini(control);
763 
764 	smu_v11_0_i2c_bus_unlock(control);
765 
766 
767 	DRM_INFO("End");
768 	return true;
769 }
770 #endif
771