1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright 2020 NXP
4 //
5 // Author: Daniel Baluta <daniel.baluta@nxp.com>
6 //
7 // Hardware interface for audio DSP on i.MX8M
8
9 #include <linux/firmware.h>
10 #include <linux/of_platform.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13
14 #include <linux/module.h>
15 #include <sound/sof.h>
16 #include <sound/sof/xtensa.h>
17 #include <linux/firmware/imx/dsp.h>
18
19 #include "../ops.h"
20 #include "imx-common.h"
21 #include "imx-ops.h"
22
23 #define MBOX_OFFSET 0x800000
24 #define MBOX_SIZE 0x1000
25
26 struct imx8m_priv {
27 struct device *dev;
28 struct snd_sof_dev *sdev;
29
30 /* DSP IPC handler */
31 struct imx_dsp_ipc *dsp_ipc;
32 struct platform_device *ipc_dev;
33 };
34
imx8m_get_reply(struct snd_sof_dev * sdev)35 static void imx8m_get_reply(struct snd_sof_dev *sdev)
36 {
37 struct snd_sof_ipc_msg *msg = sdev->msg;
38 struct sof_ipc_reply reply;
39 int ret = 0;
40
41 if (!msg) {
42 dev_warn(sdev->dev, "unexpected ipc interrupt\n");
43 return;
44 }
45
46 /* get reply */
47 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
48
49 if (reply.error < 0) {
50 memcpy(msg->reply_data, &reply, sizeof(reply));
51 ret = reply.error;
52 } else {
53 /* reply has correct size? */
54 if (reply.hdr.size != msg->reply_size) {
55 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
56 msg->reply_size, reply.hdr.size);
57 ret = -EINVAL;
58 }
59
60 /* read the message */
61 if (msg->reply_size > 0)
62 sof_mailbox_read(sdev, sdev->host_box.offset,
63 msg->reply_data, msg->reply_size);
64 }
65
66 msg->reply_error = ret;
67 }
68
imx8m_get_mailbox_offset(struct snd_sof_dev * sdev)69 static int imx8m_get_mailbox_offset(struct snd_sof_dev *sdev)
70 {
71 return MBOX_OFFSET;
72 }
73
imx8m_get_window_offset(struct snd_sof_dev * sdev,u32 id)74 static int imx8m_get_window_offset(struct snd_sof_dev *sdev, u32 id)
75 {
76 return MBOX_OFFSET;
77 }
78
imx8m_dsp_handle_reply(struct imx_dsp_ipc * ipc)79 static void imx8m_dsp_handle_reply(struct imx_dsp_ipc *ipc)
80 {
81 struct imx8m_priv *priv = imx_dsp_get_data(ipc);
82 unsigned long flags;
83
84 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
85 imx8m_get_reply(priv->sdev);
86 snd_sof_ipc_reply(priv->sdev, 0);
87 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
88 }
89
imx8m_dsp_handle_request(struct imx_dsp_ipc * ipc)90 static void imx8m_dsp_handle_request(struct imx_dsp_ipc *ipc)
91 {
92 struct imx8m_priv *priv = imx_dsp_get_data(ipc);
93 u32 p; /* Panic code */
94
95 /* Read the message from the debug box. */
96 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
97
98 /* Check to see if the message is a panic code (0x0dead***) */
99 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
100 snd_sof_dsp_panic(priv->sdev, p);
101 else
102 snd_sof_ipc_msgs_rx(priv->sdev);
103 }
104
105 static struct imx_dsp_ops imx8m_dsp_ops = {
106 .handle_reply = imx8m_dsp_handle_reply,
107 .handle_request = imx8m_dsp_handle_request,
108 };
109
imx8m_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)110 static int imx8m_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
111 {
112 struct imx8m_priv *priv = sdev->pdata->hw_pdata;
113
114 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
115 msg->msg_size);
116 imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
117
118 return 0;
119 }
120
121 /*
122 * DSP control.
123 */
imx8m_run(struct snd_sof_dev * sdev)124 static int imx8m_run(struct snd_sof_dev *sdev)
125 {
126 /* TODO: start DSP using Audio MIX bits */
127 return 0;
128 }
129
imx8m_probe(struct snd_sof_dev * sdev)130 static int imx8m_probe(struct snd_sof_dev *sdev)
131 {
132 struct platform_device *pdev =
133 container_of(sdev->dev, struct platform_device, dev);
134 struct device_node *np = pdev->dev.of_node;
135 struct device_node *res_node;
136 struct resource *mmio;
137 struct imx8m_priv *priv;
138 struct resource res;
139 u32 base, size;
140 int ret = 0;
141
142 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
143 if (!priv)
144 return -ENOMEM;
145
146 sdev->pdata->hw_pdata = priv;
147 priv->dev = sdev->dev;
148 priv->sdev = sdev;
149
150 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
151 PLATFORM_DEVID_NONE,
152 pdev, sizeof(*pdev));
153 if (IS_ERR(priv->ipc_dev))
154 return PTR_ERR(priv->ipc_dev);
155
156 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
157 if (!priv->dsp_ipc) {
158 /* DSP IPC driver not probed yet, try later */
159 ret = -EPROBE_DEFER;
160 dev_err(sdev->dev, "Failed to get drvdata\n");
161 goto exit_pdev_unregister;
162 }
163
164 imx_dsp_set_data(priv->dsp_ipc, priv);
165 priv->dsp_ipc->ops = &imx8m_dsp_ops;
166
167 /* DSP base */
168 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
169 if (mmio) {
170 base = mmio->start;
171 size = resource_size(mmio);
172 } else {
173 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
174 ret = -EINVAL;
175 goto exit_pdev_unregister;
176 }
177
178 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
179 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
180 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
181 base, size);
182 ret = -ENODEV;
183 goto exit_pdev_unregister;
184 }
185 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
186
187 res_node = of_parse_phandle(np, "memory-region", 0);
188 if (!res_node) {
189 dev_err(&pdev->dev, "failed to get memory region node\n");
190 ret = -ENODEV;
191 goto exit_pdev_unregister;
192 }
193
194 ret = of_address_to_resource(res_node, 0, &res);
195 if (ret) {
196 dev_err(&pdev->dev, "failed to get reserved region address\n");
197 goto exit_pdev_unregister;
198 }
199
200 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
201 resource_size(&res));
202 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
203 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
204 base, size);
205 ret = -ENOMEM;
206 goto exit_pdev_unregister;
207 }
208 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
209
210 /* set default mailbox offset for FW ready message */
211 sdev->dsp_box.offset = MBOX_OFFSET;
212
213 return 0;
214
215 exit_pdev_unregister:
216 platform_device_unregister(priv->ipc_dev);
217 return ret;
218 }
219
imx8m_remove(struct snd_sof_dev * sdev)220 static int imx8m_remove(struct snd_sof_dev *sdev)
221 {
222 struct imx8m_priv *priv = sdev->pdata->hw_pdata;
223
224 platform_device_unregister(priv->ipc_dev);
225
226 return 0;
227 }
228
229 /* on i.MX8 there is 1 to 1 match between type and BAR idx */
imx8m_get_bar_index(struct snd_sof_dev * sdev,u32 type)230 static int imx8m_get_bar_index(struct snd_sof_dev *sdev, u32 type)
231 {
232 /* Only IRAM and SRAM bars are valid */
233 switch (type) {
234 case SOF_FW_BLK_TYPE_IRAM:
235 case SOF_FW_BLK_TYPE_SRAM:
236 return type;
237 default:
238 return -EINVAL;
239 }
240 }
241
242 static struct snd_soc_dai_driver imx8m_dai[] = {
243 {
244 .name = "sai1",
245 .playback = {
246 .channels_min = 1,
247 .channels_max = 32,
248 },
249 .capture = {
250 .channels_min = 1,
251 .channels_max = 32,
252 },
253 },
254 {
255 .name = "sai3",
256 .playback = {
257 .channels_min = 1,
258 .channels_max = 32,
259 },
260 .capture = {
261 .channels_min = 1,
262 .channels_max = 32,
263 },
264 },
265 };
266
267 /* i.MX8 ops */
268 struct snd_sof_dsp_ops sof_imx8m_ops = {
269 /* probe and remove */
270 .probe = imx8m_probe,
271 .remove = imx8m_remove,
272 /* DSP core boot */
273 .run = imx8m_run,
274
275 /* Block IO */
276 .block_read = sof_block_read,
277 .block_write = sof_block_write,
278
279 /* Mailbox IO */
280 .mailbox_read = sof_mailbox_read,
281 .mailbox_write = sof_mailbox_write,
282
283 /* ipc */
284 .send_msg = imx8m_send_msg,
285 .fw_ready = sof_fw_ready,
286 .get_mailbox_offset = imx8m_get_mailbox_offset,
287 .get_window_offset = imx8m_get_window_offset,
288
289 .ipc_msg_data = sof_ipc_msg_data,
290 .ipc_pcm_params = sof_ipc_pcm_params,
291
292 /* module loading */
293 .load_module = snd_sof_parse_module_memcpy,
294 .get_bar_index = imx8m_get_bar_index,
295 /* firmware loading */
296 .load_firmware = snd_sof_load_firmware_memcpy,
297
298 /* Debug information */
299 .dbg_dump = imx8_dump,
300 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
301
302 /* stream callbacks */
303 .pcm_open = sof_stream_pcm_open,
304 .pcm_close = sof_stream_pcm_close,
305 /* Firmware ops */
306 .dsp_arch_ops = &sof_xtensa_arch_ops,
307
308 /* DAI drivers */
309 .drv = imx8m_dai,
310 .num_drv = ARRAY_SIZE(imx8m_dai),
311
312 .hw_info = SNDRV_PCM_INFO_MMAP |
313 SNDRV_PCM_INFO_MMAP_VALID |
314 SNDRV_PCM_INFO_INTERLEAVED |
315 SNDRV_PCM_INFO_PAUSE |
316 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
317 };
318 EXPORT_SYMBOL(sof_imx8m_ops);
319
320 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
321 MODULE_LICENSE("Dual BSD/GPL");
322