1 /* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2018 Marvell International Ltd.
4 */
5
6 #ifndef __RVU_H__
7 #define __RVU_H__
8
9 #include <asm/arch/csrs/csrs-rvu.h>
10
11 #define ALIGNED __aligned(CONFIG_SYS_CACHELINE_SIZE)
12
13 #define Q_SIZE_16 0ULL /* 16 entries */
14 #define Q_SIZE_64 1ULL /* 64 entries */
15 #define Q_SIZE_256 2ULL
16 #define Q_SIZE_1K 3ULL
17 #define Q_SIZE_4K 4ULL
18 #define Q_SIZE_16K 5ULL
19 #define Q_SIZE_64K 6ULL
20 #define Q_SIZE_256K 7ULL
21 #define Q_SIZE_1M 8ULL /* Million entries */
22 #define Q_SIZE_MIN Q_SIZE_16
23 #define Q_SIZE_MAX Q_SIZE_1M
24
25 #define Q_COUNT(x) (16ULL << (2 * (x)))
26 #define Q_SIZE(x, n) ((ilog2(x) - (n)) / 2)
27
28 /* Admin queue info */
29
30 /* Since we intend to add only one instruction at a time,
31 * keep queue size to it's minimum.
32 */
33 #define AQ_SIZE Q_SIZE_16
34 /* HW head & tail pointer mask */
35 #define AQ_PTR_MASK 0xFFFFF
36
37 struct qmem {
38 void *base;
39 dma_addr_t iova;
40 size_t alloc_sz;
41 u32 qsize;
42 u8 entry_sz;
43 };
44
45 struct admin_queue {
46 struct qmem inst;
47 struct qmem res;
48 };
49
50 struct rvu_af {
51 struct udevice *dev;
52 void __iomem *af_base;
53 struct nix_af *nix_af;
54 };
55
56 struct rvu_pf {
57 struct udevice *dev;
58 struct udevice *afdev;
59 void __iomem *pf_base;
60 struct nix *nix;
61 u8 pfid;
62 int nix_lfid;
63 int npa_lfid;
64 };
65
66 /**
67 * Store 128 bit value
68 *
69 * @param[out] dest pointer to destination address
70 * @param val0 first 64 bits to write
71 * @param val1 second 64 bits to write
72 */
st128(void * dest,u64 val0,u64 val1)73 static inline void st128(void *dest, u64 val0, u64 val1)
74 {
75 __asm__ __volatile__("stp %x[x0], %x[x1], [%[pm]]" :
76 : [x0]"r"(val0), [x1]"r"(val1), [pm]"r"(dest)
77 : "memory");
78 }
79
80 /**
81 * Load 128 bit value
82 *
83 * @param[in] source pointer to 128 bits of data to load
84 * @param[out] val0 first 64 bits of data
85 * @param[out] val1 second 64 bits of data
86 */
ld128(const u64 * src,u64 * val0,u64 * val1)87 static inline void ld128(const u64 *src, u64 *val0, u64 *val1)
88 {
89 __asm__ __volatile__ ("ldp %x[x0], %x[x1], [%[pm]]" :
90 : [x0]"r"(*val0), [x1]"r"(*val1), [pm]"r"(src));
91 }
92
93 void qmem_free(struct qmem *q);
94 int qmem_alloc(struct qmem *q, u32 qsize, size_t entry_sz);
95
96 /**
97 * Allocates an admin queue for instructions and results
98 *
99 * @param aq admin queue to allocate for
100 * @param qsize Number of entries in the queue
101 * @param inst_size Size of each instruction
102 * @param res_size Size of each result
103 *
104 * @return -ENOMEM on error, 0 on success
105 */
106 int rvu_aq_alloc(struct admin_queue *aq, unsigned int qsize,
107 size_t inst_size, size_t res_size);
108
109 /**
110 * Frees an admin queue
111 *
112 * @param aq Admin queue to free
113 */
114 void rvu_aq_free(struct admin_queue *aq);
115
116 void rvu_get_lfid_for_pf(int pf, int *nixid, int *npaid);
117
118 #endif /* __RVU_H__ */
119
120