1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
4 */
5
6 #ifndef _STM32PROG_H_
7 #define _STM32PROG_H_
8
9 /* - phase defines ------------------------------------------------*/
10 #define PHASE_FLASHLAYOUT 0x00
11 #define PHASE_FIRST_USER 0x10
12 #define PHASE_LAST_USER 0xF0
13 #define PHASE_CMD 0xF1
14 #define PHASE_OTP 0xF2
15 #define PHASE_PMIC 0xF4
16 #define PHASE_END 0xFE
17 #define PHASE_RESET 0xFF
18 #define PHASE_DO_RESET 0x1FF
19
20 #define DEFAULT_ADDRESS 0xFFFFFFFF
21
22 #define OTP_SIZE 1024
23 #define PMIC_SIZE 8
24
25 enum stm32prog_target {
26 STM32PROG_NONE,
27 STM32PROG_MMC,
28 STM32PROG_NAND,
29 STM32PROG_NOR,
30 STM32PROG_SPI_NAND,
31 STM32PROG_RAM
32 };
33
34 enum stm32prog_link_t {
35 LINK_SERIAL,
36 LINK_USB,
37 LINK_UNDEFINED,
38 };
39
40 struct image_header_s {
41 bool present;
42 u32 image_checksum;
43 u32 image_length;
44 };
45
46 struct raw_header_s {
47 u32 magic_number;
48 u32 image_signature[64 / 4];
49 u32 image_checksum;
50 u32 header_version;
51 u32 image_length;
52 u32 image_entry_point;
53 u32 reserved1;
54 u32 load_address;
55 u32 reserved2;
56 u32 version_number;
57 u32 option_flags;
58 u32 ecdsa_algorithm;
59 u32 ecdsa_public_key[64 / 4];
60 u32 padding[83 / 4];
61 u32 binary_type;
62 };
63
64 #define BL_HEADER_SIZE sizeof(struct raw_header_s)
65
66 /* partition type in flashlayout file */
67 enum stm32prog_part_type {
68 PART_BINARY,
69 PART_SYSTEM,
70 PART_FILESYSTEM,
71 RAW_IMAGE
72 };
73
74 /* device information */
75 struct stm32prog_dev_t {
76 enum stm32prog_target target;
77 char dev_id;
78 u32 erase_size;
79 struct mmc *mmc;
80 struct mtd_info *mtd;
81 /* list of partition for this device / ordered in offset */
82 struct list_head part_list;
83 bool full_update;
84 };
85
86 /* partition information build from FlashLayout and device */
87 struct stm32prog_part_t {
88 /* FlashLayout information */
89 int option;
90 int id;
91 enum stm32prog_part_type part_type;
92 enum stm32prog_target target;
93 char dev_id;
94
95 /* partition name
96 * (16 char in gpt, + 1 for null terminated string
97 */
98 char name[16 + 1];
99 u64 addr;
100 u64 size;
101 enum stm32prog_part_type bin_nb; /* SSBL repeatition */
102
103 /* information on associated device */
104 struct stm32prog_dev_t *dev; /* pointer to device */
105 s16 part_id; /* partition id in device */
106 int alt_id; /* alt id in usb/dfu */
107
108 struct list_head list;
109 };
110
111 #define STM32PROG_MAX_DEV 5
112 struct stm32prog_data {
113 /* Layout information */
114 int dev_nb; /* device number*/
115 struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */
116 int part_nb; /* nb of partition */
117 struct stm32prog_part_t *part_array; /* array of partition */
118 bool tee_detected;
119 bool fsbl_nor_detected;
120
121 /* command internal information */
122 unsigned int phase;
123 u32 offset;
124 char error[255];
125 struct stm32prog_part_t *cur_part;
126 u32 *otp_part;
127 u8 pmic_part[PMIC_SIZE];
128
129 /* STM32 header information */
130 struct raw_header_s *header_data;
131 struct image_header_s header;
132
133 /* SERIAL information */
134 u32 cursor;
135 u32 packet_number;
136 u32 checksum;
137 u8 *buffer; /* size = USART_RAM_BUFFER_SIZE*/
138 int dfu_seq;
139 u8 read_phase;
140
141 /* bootm information */
142 u32 uimage;
143 u32 dtb;
144 };
145
146 extern struct stm32prog_data *stm32prog_data;
147
148 /* OTP access */
149 int stm32prog_otp_write(struct stm32prog_data *data, u32 offset,
150 u8 *buffer, long *size);
151 int stm32prog_otp_read(struct stm32prog_data *data, u32 offset,
152 u8 *buffer, long *size);
153 int stm32prog_otp_start(struct stm32prog_data *data);
154
155 /* PMIC access */
156 int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset,
157 u8 *buffer, long *size);
158 int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset,
159 u8 *buffer, long *size);
160 int stm32prog_pmic_start(struct stm32prog_data *data);
161
162 /* generic part*/
163 u8 stm32prog_header_check(struct raw_header_s *raw_header,
164 struct image_header_s *header);
165 int stm32prog_dfu_init(struct stm32prog_data *data);
166 void stm32prog_next_phase(struct stm32prog_data *data);
167 void stm32prog_do_reset(struct stm32prog_data *data);
168
169 char *stm32prog_get_error(struct stm32prog_data *data);
170
171 #define stm32prog_err(args...) {\
172 if (data->phase != PHASE_RESET) { \
173 sprintf(data->error, args); \
174 data->phase = PHASE_RESET; \
175 log_err("Error: %s\n", data->error); } \
176 }
177
178 /* Main function */
179 int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size);
180 void stm32prog_clean(struct stm32prog_data *data);
181
182 #ifdef CONFIG_CMD_STM32PROG_SERIAL
183 int stm32prog_serial_init(struct stm32prog_data *data, int link_dev);
184 bool stm32prog_serial_loop(struct stm32prog_data *data);
185 #else
stm32prog_serial_init(struct stm32prog_data * data,int link_dev)186 static inline int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
187 {
188 return -ENOSYS;
189 }
190
stm32prog_serial_loop(struct stm32prog_data * data)191 static inline bool stm32prog_serial_loop(struct stm32prog_data *data)
192 {
193 return false;
194 }
195 #endif
196
197 #ifdef CONFIG_CMD_STM32PROG_USB
198 bool stm32prog_usb_loop(struct stm32prog_data *data, int dev);
199 #else
stm32prog_usb_loop(struct stm32prog_data * data,int dev)200 static inline bool stm32prog_usb_loop(struct stm32prog_data *data, int dev)
201 {
202 return false;
203 }
204 #endif
205
206 #endif
207