1 /*
2  * Allwinner sun4i USB PHY driver
3  *
4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
7  *
8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #include <common.h>
14 #include <clk.h>
15 #include <dm.h>
16 #include <log.h>
17 #include <dm/device.h>
18 #include <generic-phy.h>
19 #include <phy-sun4i-usb.h>
20 #include <reset.h>
21 #include <asm/gpio.h>
22 #include <asm/io.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/cpu.h>
25 #include <dm/device_compat.h>
26 #include <linux/bitops.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 
30 #define REG_ISCR			0x00
31 #define REG_PHYCTL_A10			0x04
32 #define REG_PHYBIST			0x08
33 #define REG_PHYTUNE			0x0c
34 #define REG_PHYCTL_A33			0x10
35 #define REG_PHY_OTGCTL			0x20
36 #define REG_PMU_UNK1			0x10
37 
38 /* Common Control Bits for Both PHYs */
39 #define PHY_PLL_BW			0x03
40 #define PHY_RES45_CAL_EN		0x0c
41 
42 /* Private Control Bits for Each PHY */
43 #define PHY_TX_AMPLITUDE_TUNE		0x20
44 #define PHY_TX_SLEWRATE_TUNE		0x22
45 #define PHY_DISCON_TH_SEL		0x2a
46 #define PHY_SQUELCH_DETECT		0x3c
47 
48 #define PHYCTL_DATA			BIT(7)
49 #define OTGCTL_ROUTE_MUSB		BIT(0)
50 
51 #define PHY_TX_RATE			BIT(4)
52 #define PHY_TX_MAGNITUDE		BIT(2)
53 #define PHY_TX_AMPLITUDE_LEN		5
54 
55 #define PHY_RES45_CAL_DATA		BIT(0)
56 #define PHY_RES45_CAL_LEN		1
57 #define PHY_DISCON_TH_LEN		2
58 
59 #define SUNXI_AHB_ICHR8_EN		BIT(10)
60 #define SUNXI_AHB_INCR4_BURST_EN	BIT(9)
61 #define SUNXI_AHB_INCRX_ALIGN_EN	BIT(8)
62 #define SUNXI_ULPI_BYPASS_EN		BIT(0)
63 
64 /* A83T specific control bits for PHY0 */
65 #define PHY_CTL_VBUSVLDEXT		BIT(5)
66 #define PHY_CTL_SIDDQ			BIT(3)
67 
68 /* A83T specific control bits for PHY2 HSIC */
69 #define SUNXI_EHCI_HS_FORCE		BIT(20)
70 #define SUNXI_HSIC_CONNECT_INT		BIT(16)
71 #define SUNXI_HSIC			BIT(1)
72 
73 #define MAX_PHYS			4
74 
75 enum sun4i_usb_phy_type {
76 	sun4i_a10_phy,
77 	sun6i_a31_phy,
78 	sun8i_a33_phy,
79 	sun8i_a83t_phy,
80 	sun8i_h3_phy,
81 	sun8i_r40_phy,
82 	sun8i_v3s_phy,
83 	sun50i_a64_phy,
84 	sun50i_h6_phy,
85 };
86 
87 struct sun4i_usb_phy_cfg {
88 	int num_phys;
89 	enum sun4i_usb_phy_type type;
90 	u32 disc_thresh;
91 	u8 phyctl_offset;
92 	bool dedicated_clocks;
93 	bool enable_pmu_unk1;
94 	bool phy0_dual_route;
95 	int missing_phys;
96 };
97 
98 struct sun4i_usb_phy_info {
99 	const char *gpio_vbus;
100 	const char *gpio_vbus_det;
101 	const char *gpio_id_det;
102 } phy_info[] = {
103 	{
104 		.gpio_vbus = CONFIG_USB0_VBUS_PIN,
105 		.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
106 		.gpio_id_det = CONFIG_USB0_ID_DET,
107 	},
108 	{
109 		.gpio_vbus = CONFIG_USB1_VBUS_PIN,
110 		.gpio_vbus_det = NULL,
111 		.gpio_id_det = NULL,
112 	},
113 	{
114 		.gpio_vbus = CONFIG_USB2_VBUS_PIN,
115 		.gpio_vbus_det = NULL,
116 		.gpio_id_det = NULL,
117 	},
118 	{
119 		.gpio_vbus = CONFIG_USB3_VBUS_PIN,
120 		.gpio_vbus_det = NULL,
121 		.gpio_id_det = NULL,
122 	},
123 };
124 
125 struct sun4i_usb_phy_plat {
126 	void __iomem *pmu;
127 	int power_on_count;
128 	int gpio_vbus;
129 	int gpio_vbus_det;
130 	int gpio_id_det;
131 	struct clk clocks;
132 	struct reset_ctl resets;
133 	int id;
134 };
135 
136 struct sun4i_usb_phy_data {
137 	void __iomem *base;
138 	const struct sun4i_usb_phy_cfg *cfg;
139 	struct sun4i_usb_phy_plat *usb_phy;
140 };
141 
142 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
143 
sun4i_usb_phy_write(struct phy * phy,u32 addr,u32 data,int len)144 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
145 {
146 	struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
147 	struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
148 	u32 temp, usbc_bit = BIT(usb_phy->id * 2);
149 	void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
150 	int i;
151 
152 	if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
153 		/* SoCs newer than A33 need us to set phyctl to 0 explicitly */
154 		writel(0, phyctl);
155 	}
156 
157 	for (i = 0; i < len; i++) {
158 		temp = readl(phyctl);
159 
160 		/* clear the address portion */
161 		temp &= ~(0xff << 8);
162 
163 		/* set the address */
164 		temp |= ((addr + i) << 8);
165 		writel(temp, phyctl);
166 
167 		/* set the data bit and clear usbc bit*/
168 		temp = readb(phyctl);
169 		if (data & 0x1)
170 			temp |= PHYCTL_DATA;
171 		else
172 			temp &= ~PHYCTL_DATA;
173 		temp &= ~usbc_bit;
174 		writeb(temp, phyctl);
175 
176 		/* pulse usbc_bit */
177 		temp = readb(phyctl);
178 		temp |= usbc_bit;
179 		writeb(temp, phyctl);
180 
181 		temp = readb(phyctl);
182 		temp &= ~usbc_bit;
183 		writeb(temp, phyctl);
184 
185 		data >>= 1;
186 	}
187 }
188 
sun4i_usb_phy_passby(struct phy * phy,bool enable)189 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
190 {
191 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
192 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
193 	u32 bits, reg_value;
194 
195 	if (!usb_phy->pmu)
196 		return;
197 
198 	bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
199 		SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
200 
201 	/* A83T USB2 is HSIC */
202 	if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
203 		bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
204 			SUNXI_HSIC;
205 
206 	reg_value = readl(usb_phy->pmu);
207 
208 	if (enable)
209 		reg_value |= bits;
210 	else
211 		reg_value &= ~bits;
212 
213 	writel(reg_value, usb_phy->pmu);
214 }
215 
sun4i_usb_phy_power_on(struct phy * phy)216 static int sun4i_usb_phy_power_on(struct phy *phy)
217 {
218 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
219 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
220 
221 	if (initial_usb_scan_delay) {
222 		mdelay(initial_usb_scan_delay);
223 		initial_usb_scan_delay = 0;
224 	}
225 
226 	usb_phy->power_on_count++;
227 	if (usb_phy->power_on_count != 1)
228 		return 0;
229 
230 	if (usb_phy->gpio_vbus >= 0)
231 		gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
232 
233 	return 0;
234 }
235 
sun4i_usb_phy_power_off(struct phy * phy)236 static int sun4i_usb_phy_power_off(struct phy *phy)
237 {
238 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
239 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
240 
241 	usb_phy->power_on_count--;
242 	if (usb_phy->power_on_count != 0)
243 		return 0;
244 
245 	if (usb_phy->gpio_vbus >= 0)
246 		gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
247 
248 	return 0;
249 }
250 
sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data * data,bool id_det)251 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
252 {
253 	u32 regval;
254 
255 	regval = readl(data->base + REG_PHY_OTGCTL);
256 	if (!id_det) {
257 		/* Host mode. Route phy0 to EHCI/OHCI */
258 		regval &= ~OTGCTL_ROUTE_MUSB;
259 	} else {
260 		/* Peripheral mode. Route phy0 to MUSB */
261 		regval |= OTGCTL_ROUTE_MUSB;
262 	}
263 	writel(regval, data->base + REG_PHY_OTGCTL);
264 }
265 
sun4i_usb_phy_init(struct phy * phy)266 static int sun4i_usb_phy_init(struct phy *phy)
267 {
268 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
269 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
270 	u32 val;
271 	int ret;
272 
273 	ret = clk_enable(&usb_phy->clocks);
274 	if (ret) {
275 		dev_err(phy->dev, "failed to enable usb_%ldphy clock\n",
276 			phy->id);
277 		return ret;
278 	}
279 
280 	ret = reset_deassert(&usb_phy->resets);
281 	if (ret) {
282 		dev_err(phy->dev, "failed to deassert usb_%ldreset reset\n",
283 			phy->id);
284 		return ret;
285 	}
286 
287 	if (data->cfg->type == sun8i_a83t_phy ||
288 	    data->cfg->type == sun50i_h6_phy) {
289 		if (phy->id == 0) {
290 			val = readl(data->base + data->cfg->phyctl_offset);
291 			val |= PHY_CTL_VBUSVLDEXT;
292 			val &= ~PHY_CTL_SIDDQ;
293 			writel(val, data->base + data->cfg->phyctl_offset);
294 		}
295 	} else {
296 		if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
297 			val = readl(usb_phy->pmu + REG_PMU_UNK1);
298 			writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
299 		}
300 
301 		if (usb_phy->id == 0)
302 			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
303 					    PHY_RES45_CAL_DATA,
304 					    PHY_RES45_CAL_LEN);
305 
306 		/* Adjust PHY's magnitude and rate */
307 		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
308 				    PHY_TX_MAGNITUDE | PHY_TX_RATE,
309 				    PHY_TX_AMPLITUDE_LEN);
310 
311 		/* Disconnect threshold adjustment */
312 		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
313 				    data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
314 	}
315 
316 	sun4i_usb_phy_passby(phy, true);
317 
318 	sun4i_usb_phy0_reroute(data, true);
319 
320 	return 0;
321 }
322 
sun4i_usb_phy_exit(struct phy * phy)323 static int sun4i_usb_phy_exit(struct phy *phy)
324 {
325 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
326 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
327 	int ret;
328 
329 	if (phy->id == 0) {
330 		if (data->cfg->type == sun8i_a83t_phy ||
331 		    data->cfg->type == sun50i_h6_phy) {
332 			void __iomem *phyctl = data->base +
333 				data->cfg->phyctl_offset;
334 
335 			writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
336 		}
337 	}
338 
339 	sun4i_usb_phy_passby(phy, false);
340 
341 	ret = clk_disable(&usb_phy->clocks);
342 	if (ret) {
343 		dev_err(phy->dev, "failed to disable usb_%ldphy clock\n",
344 			phy->id);
345 		return ret;
346 	}
347 
348 	ret = reset_assert(&usb_phy->resets);
349 	if (ret) {
350 		dev_err(phy->dev, "failed to assert usb_%ldreset reset\n",
351 			phy->id);
352 		return ret;
353 	}
354 
355 	return 0;
356 }
357 
sun4i_usb_phy_xlate(struct phy * phy,struct ofnode_phandle_args * args)358 static int sun4i_usb_phy_xlate(struct phy *phy,
359 			       struct ofnode_phandle_args *args)
360 {
361 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
362 
363 	if (args->args_count >= data->cfg->num_phys)
364 		return -EINVAL;
365 
366 	if (data->cfg->missing_phys & BIT(args->args[0]))
367 		return -ENODEV;
368 
369 	if (args->args_count)
370 		phy->id = args->args[0];
371 	else
372 		phy->id = 0;
373 
374 	debug("%s: phy_id = %ld\n", __func__, phy->id);
375 	return 0;
376 }
377 
sun4i_usb_phy_vbus_detect(struct phy * phy)378 int sun4i_usb_phy_vbus_detect(struct phy *phy)
379 {
380 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
381 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
382 	int err, retries = 3;
383 
384 	debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
385 
386 	if (usb_phy->gpio_vbus_det < 0)
387 		return usb_phy->gpio_vbus_det;
388 
389 	err = gpio_get_value(usb_phy->gpio_vbus_det);
390 	/*
391 	 * Vbus may have been provided by the board and just been turned of
392 	 * some milliseconds ago on reset, what we're measuring then is a
393 	 * residual charge on Vbus, sleep a bit and try again.
394 	 */
395 	while (err > 0 && retries--) {
396 		mdelay(100);
397 		err = gpio_get_value(usb_phy->gpio_vbus_det);
398 	}
399 
400 	return err;
401 }
402 
sun4i_usb_phy_id_detect(struct phy * phy)403 int sun4i_usb_phy_id_detect(struct phy *phy)
404 {
405 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
406 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
407 
408 	debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
409 
410 	if (usb_phy->gpio_id_det < 0)
411 		return usb_phy->gpio_id_det;
412 
413 	return gpio_get_value(usb_phy->gpio_id_det);
414 }
415 
sun4i_usb_phy_set_squelch_detect(struct phy * phy,bool enabled)416 void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
417 {
418 	sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
419 }
420 
421 static struct phy_ops sun4i_usb_phy_ops = {
422 	.of_xlate = sun4i_usb_phy_xlate,
423 	.init = sun4i_usb_phy_init,
424 	.power_on = sun4i_usb_phy_power_on,
425 	.power_off = sun4i_usb_phy_power_off,
426 	.exit = sun4i_usb_phy_exit,
427 };
428 
sun4i_usb_phy_probe(struct udevice * dev)429 static int sun4i_usb_phy_probe(struct udevice *dev)
430 {
431 	struct sun4i_usb_phy_plat *plat = dev_get_plat(dev);
432 	struct sun4i_usb_phy_data *data = dev_get_priv(dev);
433 	int i, ret;
434 
435 	data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
436 	if (!data->cfg)
437 		return -EINVAL;
438 
439 	data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
440 	if (IS_ERR(data->base))
441 		return PTR_ERR(data->base);
442 
443 	data->usb_phy = plat;
444 	for (i = 0; i < data->cfg->num_phys; i++) {
445 		struct sun4i_usb_phy_plat *phy = &plat[i];
446 		struct sun4i_usb_phy_info *info = &phy_info[i];
447 		char name[16];
448 
449 		if (data->cfg->missing_phys & BIT(i))
450 			continue;
451 
452 		phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
453 		if (phy->gpio_vbus >= 0) {
454 			ret = gpio_request(phy->gpio_vbus, "usb_vbus");
455 			if (ret)
456 				return ret;
457 			ret = gpio_direction_output(phy->gpio_vbus, 0);
458 			if (ret)
459 				return ret;
460 		}
461 
462 		phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
463 		if (phy->gpio_vbus_det >= 0) {
464 			ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
465 			if (ret)
466 				return ret;
467 			ret = gpio_direction_input(phy->gpio_vbus_det);
468 			if (ret)
469 				return ret;
470 		}
471 
472 		phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
473 		if (phy->gpio_id_det >= 0) {
474 			ret = gpio_request(phy->gpio_id_det, "usb_id_det");
475 			if (ret)
476 				return ret;
477 			ret = gpio_direction_input(phy->gpio_id_det);
478 			if (ret)
479 				return ret;
480 			sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
481 		}
482 
483 		if (data->cfg->dedicated_clocks)
484 			snprintf(name, sizeof(name), "usb%d_phy", i);
485 		else
486 			strlcpy(name, "usb_phy", sizeof(name));
487 
488 		ret = clk_get_by_name(dev, name, &phy->clocks);
489 		if (ret) {
490 			dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
491 			return ret;
492 		}
493 
494 		snprintf(name, sizeof(name), "usb%d_reset", i);
495 		ret = reset_get_by_name(dev, name, &phy->resets);
496 		if (ret) {
497 			dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
498 			return ret;
499 		}
500 
501 		if (i || data->cfg->phy0_dual_route) {
502 			snprintf(name, sizeof(name), "pmu%d", i);
503 			phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
504 			if (IS_ERR(phy->pmu))
505 				return PTR_ERR(phy->pmu);
506 		}
507 
508 		phy->id = i;
509 	};
510 
511 	debug("Allwinner Sun4I USB PHY driver loaded\n");
512 	return 0;
513 }
514 
515 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
516 	.num_phys = 3,
517 	.type = sun4i_a10_phy,
518 	.disc_thresh = 3,
519 	.phyctl_offset = REG_PHYCTL_A10,
520 	.dedicated_clocks = false,
521 	.enable_pmu_unk1 = false,
522 };
523 
524 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
525 	.num_phys = 2,
526 	.type = sun4i_a10_phy,
527 	.disc_thresh = 2,
528 	.phyctl_offset = REG_PHYCTL_A10,
529 	.dedicated_clocks = false,
530 	.enable_pmu_unk1 = false,
531 };
532 
533 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
534 	.num_phys = 3,
535 	.type = sun6i_a31_phy,
536 	.disc_thresh = 3,
537 	.phyctl_offset = REG_PHYCTL_A10,
538 	.dedicated_clocks = true,
539 	.enable_pmu_unk1 = false,
540 };
541 
542 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
543 	.num_phys = 3,
544 	.type = sun4i_a10_phy,
545 	.disc_thresh = 2,
546 	.phyctl_offset = REG_PHYCTL_A10,
547 	.dedicated_clocks = false,
548 	.enable_pmu_unk1 = false,
549 };
550 
551 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
552 	.num_phys = 2,
553 	.type = sun4i_a10_phy,
554 	.disc_thresh = 3,
555 	.phyctl_offset = REG_PHYCTL_A10,
556 	.dedicated_clocks = true,
557 	.enable_pmu_unk1 = false,
558 };
559 
560 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
561 	.num_phys = 2,
562 	.type = sun8i_a33_phy,
563 	.disc_thresh = 3,
564 	.phyctl_offset = REG_PHYCTL_A33,
565 	.dedicated_clocks = true,
566 	.enable_pmu_unk1 = false,
567 };
568 
569 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
570 	.num_phys = 3,
571 	.type = sun8i_a83t_phy,
572 	.phyctl_offset = REG_PHYCTL_A33,
573 	.dedicated_clocks = true,
574 };
575 
576 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
577 	.num_phys = 4,
578 	.type = sun8i_h3_phy,
579 	.disc_thresh = 3,
580 	.phyctl_offset = REG_PHYCTL_A33,
581 	.dedicated_clocks = true,
582 	.enable_pmu_unk1 = true,
583 	.phy0_dual_route = true,
584 };
585 
586 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
587 	.num_phys = 3,
588 	.type = sun8i_r40_phy,
589 	.disc_thresh = 3,
590 	.phyctl_offset = REG_PHYCTL_A33,
591 	.dedicated_clocks = true,
592 	.enable_pmu_unk1 = true,
593 	.phy0_dual_route = true,
594 };
595 
596 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
597 	.num_phys = 1,
598 	.type = sun8i_v3s_phy,
599 	.disc_thresh = 3,
600 	.phyctl_offset = REG_PHYCTL_A33,
601 	.dedicated_clocks = true,
602 	.enable_pmu_unk1 = true,
603 	.phy0_dual_route = true,
604 };
605 
606 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
607 	.num_phys = 2,
608 	.type = sun50i_a64_phy,
609 	.disc_thresh = 3,
610 	.phyctl_offset = REG_PHYCTL_A33,
611 	.dedicated_clocks = true,
612 	.enable_pmu_unk1 = true,
613 	.phy0_dual_route = true,
614 };
615 
616 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
617 	.num_phys = 4,
618 	.type = sun50i_h6_phy,
619 	.disc_thresh = 3,
620 	.phyctl_offset = REG_PHYCTL_A33,
621 	.dedicated_clocks = true,
622 	.enable_pmu_unk1 = true,
623 	.phy0_dual_route = true,
624 	.missing_phys = BIT(1) | BIT(2),
625 };
626 
627 static const struct udevice_id sun4i_usb_phy_ids[] = {
628 	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
629 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
630 	{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
631 	{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
632 	{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
633 	{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
634 	{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
635 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
636 	{ .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
637 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
638 	{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
639 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
640 	{ }
641 };
642 
643 U_BOOT_DRIVER(sun4i_usb_phy) = {
644 	.name	= "sun4i_usb_phy",
645 	.id	= UCLASS_PHY,
646 	.of_match = sun4i_usb_phy_ids,
647 	.ops = &sun4i_usb_phy_ops,
648 	.probe = sun4i_usb_phy_probe,
649 	.plat_auto	= sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
650 	.priv_auto	= sizeof(struct sun4i_usb_phy_data),
651 };
652