Searched defs:sunxi_mctl_phy_reg (Results 1 – 4 of 4) sorted by relevance
164 u32 pir; /* 0x04 */167 u32 pgsr0; /* 0x10 */168 u32 pgsr1; /* 0x14 */170 u32 ptr0; /* 0x1c */171 u32 ptr1; /* 0x20 */172 u32 ptr2; /* 0x24 */173 u32 ptr3; /* 0x28 */174 u32 ptr4; /* 0x2c */180 u32 dcr; /* 0x44 */188 u32 odtcr; /* 0x64 */[all …]
152 u32 pir; /* 0x004 */176 u32 dxccr; /* 0x088 */178 u32 dsgcr; /* 0x090 */180 u32 odtcr; /* 0x098 */182 u32 aacr; /* 0x0a0 */184 u32 gpr1; /* 0x0c4 */186 u32 dcr; /* 0x100 */209 u32 vtdr; /* 0x23c */211 u8 reserved_0x248[8];236 struct {[all …]
162 u32 pir; /* 0x04 */164 u32 pgsr; /* 0x0c */167 u32 ptr0; /* 0x18 */168 u32 ptr1; /* 0x1c */169 u32 ptr2; /* 0x20 */173 u32 dcr; /* 0x30 */181 u32 odtcr; /* 0x50 */183 u32 dtd0; /* 0x58 */184 u32 dtd1; /* 0x5c */186 u32 dcuar; /* 0xc0 */[all …]
96 struct sunxi_mctl_phy_reg { struct97 u8 res0[0x04]; /* 0x00 revision id ??? */111 u32 mr0; /* 0x9c mode register 0 */112 u32 mr1; /* 0xa0 mode register 1 */113 u32 mr2; /* 0xa4 mode register 2 */114 u32 mr3; /* 0xa8 mode register 3 */124 u32 dqdsr; /* 0xf4 DQS drift register */125 u8 res1[0xc8]; /* 0xf8 */137 u8 res2[0x28]; /* 0x210 */139 struct ddrphy_zq {[all …]
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