1 /*
2  * Allwinner SoCs SRAM Controller Driver
3  *
4  * Copyright (C) 2015 Maxime Ripard
5  *
6  * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 
13 #include <linux/debugfs.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 
22 #include <linux/soc/sunxi/sunxi_sram.h>
23 
24 struct sunxi_sram_func {
25 	char	*func;
26 	u8	val;
27 	u32	reg_val;
28 };
29 
30 struct sunxi_sram_data {
31 	char			*name;
32 	u8			reg;
33 	u8			offset;
34 	u8			width;
35 	struct sunxi_sram_func	*func;
36 	struct list_head	list;
37 };
38 
39 struct sunxi_sram_desc {
40 	struct sunxi_sram_data	data;
41 	bool			claimed;
42 };
43 
44 #define SUNXI_SRAM_MAP(_reg_val, _val, _func)			\
45 	{							\
46 		.func = _func,					\
47 		.val = _val,					\
48 		.reg_val = _reg_val,				\
49 	}
50 
51 #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...)		\
52 	{							\
53 		.name = _name,					\
54 		.reg = _reg,					\
55 		.offset = _off,					\
56 		.width = _width,				\
57 		.func = (struct sunxi_sram_func[]){		\
58 			__VA_ARGS__, { } },			\
59 	}
60 
61 static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
62 	.data	= SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
63 				  SUNXI_SRAM_MAP(0, 0, "cpu"),
64 				  SUNXI_SRAM_MAP(1, 1, "emac")),
65 };
66 
67 static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
68 	.data	= SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
69 				  SUNXI_SRAM_MAP(0, 0, "cpu"),
70 				  SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
71 };
72 
73 static struct sunxi_sram_desc sun4i_a10_sram_d = {
74 	.data	= SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
75 				  SUNXI_SRAM_MAP(0, 0, "cpu"),
76 				  SUNXI_SRAM_MAP(1, 1, "usb-otg")),
77 };
78 
79 static struct sunxi_sram_desc sun50i_a64_sram_c = {
80 	.data	= SUNXI_SRAM_DATA("C", 0x4, 24, 1,
81 				  SUNXI_SRAM_MAP(0, 1, "cpu"),
82 				  SUNXI_SRAM_MAP(1, 0, "de2")),
83 };
84 
85 static const struct of_device_id sunxi_sram_dt_ids[] = {
86 	{
87 		.compatible	= "allwinner,sun4i-a10-sram-a3-a4",
88 		.data		= &sun4i_a10_sram_a3_a4.data,
89 	},
90 	{
91 		.compatible	= "allwinner,sun4i-a10-sram-c1",
92 		.data		= &sun4i_a10_sram_c1.data,
93 	},
94 	{
95 		.compatible	= "allwinner,sun4i-a10-sram-d",
96 		.data		= &sun4i_a10_sram_d.data,
97 	},
98 	{
99 		.compatible	= "allwinner,sun50i-a64-sram-c",
100 		.data		= &sun50i_a64_sram_c.data,
101 	},
102 	{}
103 };
104 
105 static struct device *sram_dev;
106 static LIST_HEAD(claimed_sram);
107 static DEFINE_SPINLOCK(sram_lock);
108 static void __iomem *base;
109 
sunxi_sram_show(struct seq_file * s,void * data)110 static int sunxi_sram_show(struct seq_file *s, void *data)
111 {
112 	struct device_node *sram_node, *section_node;
113 	const struct sunxi_sram_data *sram_data;
114 	const struct of_device_id *match;
115 	struct sunxi_sram_func *func;
116 	const __be32 *sram_addr_p, *section_addr_p;
117 	u32 val;
118 
119 	seq_puts(s, "Allwinner sunXi SRAM\n");
120 	seq_puts(s, "--------------------\n\n");
121 
122 	for_each_child_of_node(sram_dev->of_node, sram_node) {
123 		sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
124 
125 		seq_printf(s, "sram@%08x\n",
126 			   be32_to_cpu(*sram_addr_p));
127 
128 		for_each_child_of_node(sram_node, section_node) {
129 			match = of_match_node(sunxi_sram_dt_ids, section_node);
130 			if (!match)
131 				continue;
132 			sram_data = match->data;
133 
134 			section_addr_p = of_get_address(section_node, 0,
135 							NULL, NULL);
136 
137 			seq_printf(s, "\tsection@%04x\t(%s)\n",
138 				   be32_to_cpu(*section_addr_p),
139 				   sram_data->name);
140 
141 			val = readl(base + sram_data->reg);
142 			val >>= sram_data->offset;
143 			val &= GENMASK(sram_data->width - 1, 0);
144 
145 			for (func = sram_data->func; func->func; func++) {
146 				seq_printf(s, "\t\t%s%c\n", func->func,
147 					   func->reg_val == val ?
148 					   '*' : ' ');
149 			}
150 		}
151 
152 		seq_puts(s, "\n");
153 	}
154 
155 	return 0;
156 }
157 
158 DEFINE_SHOW_ATTRIBUTE(sunxi_sram);
159 
to_sram_desc(const struct sunxi_sram_data * data)160 static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data)
161 {
162 	return container_of(data, struct sunxi_sram_desc, data);
163 }
164 
sunxi_sram_of_parse(struct device_node * node,unsigned int * reg_value)165 static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node,
166 							 unsigned int *reg_value)
167 {
168 	const struct of_device_id *match;
169 	const struct sunxi_sram_data *data;
170 	struct sunxi_sram_func *func;
171 	struct of_phandle_args args;
172 	u8 val;
173 	int ret;
174 
175 	ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
176 					       &args);
177 	if (ret)
178 		return ERR_PTR(ret);
179 
180 	if (!of_device_is_available(args.np)) {
181 		ret = -EBUSY;
182 		goto err;
183 	}
184 
185 	val = args.args[0];
186 
187 	match = of_match_node(sunxi_sram_dt_ids, args.np);
188 	if (!match) {
189 		ret = -EINVAL;
190 		goto err;
191 	}
192 
193 	data = match->data;
194 	if (!data) {
195 		ret = -EINVAL;
196 		goto err;
197 	}
198 
199 	for (func = data->func; func->func; func++) {
200 		if (val == func->val) {
201 			if (reg_value)
202 				*reg_value = func->reg_val;
203 
204 			break;
205 		}
206 	}
207 
208 	if (!func->func) {
209 		ret = -EINVAL;
210 		goto err;
211 	}
212 
213 	of_node_put(args.np);
214 	return match->data;
215 
216 err:
217 	of_node_put(args.np);
218 	return ERR_PTR(ret);
219 }
220 
sunxi_sram_claim(struct device * dev)221 int sunxi_sram_claim(struct device *dev)
222 {
223 	const struct sunxi_sram_data *sram_data;
224 	struct sunxi_sram_desc *sram_desc;
225 	unsigned int device;
226 	u32 val, mask;
227 
228 	if (IS_ERR(base))
229 		return PTR_ERR(base);
230 
231 	if (!base)
232 		return -EPROBE_DEFER;
233 
234 	if (!dev || !dev->of_node)
235 		return -EINVAL;
236 
237 	sram_data = sunxi_sram_of_parse(dev->of_node, &device);
238 	if (IS_ERR(sram_data))
239 		return PTR_ERR(sram_data);
240 
241 	sram_desc = to_sram_desc(sram_data);
242 
243 	spin_lock(&sram_lock);
244 
245 	if (sram_desc->claimed) {
246 		spin_unlock(&sram_lock);
247 		return -EBUSY;
248 	}
249 
250 	mask = GENMASK(sram_data->offset + sram_data->width - 1,
251 		       sram_data->offset);
252 	val = readl(base + sram_data->reg);
253 	val &= ~mask;
254 	writel(val | ((device << sram_data->offset) & mask),
255 	       base + sram_data->reg);
256 
257 	spin_unlock(&sram_lock);
258 
259 	return 0;
260 }
261 EXPORT_SYMBOL(sunxi_sram_claim);
262 
sunxi_sram_release(struct device * dev)263 int sunxi_sram_release(struct device *dev)
264 {
265 	const struct sunxi_sram_data *sram_data;
266 	struct sunxi_sram_desc *sram_desc;
267 
268 	if (!dev || !dev->of_node)
269 		return -EINVAL;
270 
271 	sram_data = sunxi_sram_of_parse(dev->of_node, NULL);
272 	if (IS_ERR(sram_data))
273 		return -EINVAL;
274 
275 	sram_desc = to_sram_desc(sram_data);
276 
277 	spin_lock(&sram_lock);
278 	sram_desc->claimed = false;
279 	spin_unlock(&sram_lock);
280 
281 	return 0;
282 }
283 EXPORT_SYMBOL(sunxi_sram_release);
284 
285 struct sunxi_sramc_variant {
286 	int num_emac_clocks;
287 };
288 
289 static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
290 	/* Nothing special */
291 };
292 
293 static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
294 	.num_emac_clocks = 1,
295 };
296 
297 static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
298 	.num_emac_clocks = 1,
299 };
300 
301 static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
302 	.num_emac_clocks = 2,
303 };
304 
305 #define SUNXI_SRAM_EMAC_CLOCK_REG	0x30
sunxi_sram_regmap_accessible_reg(struct device * dev,unsigned int reg)306 static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
307 					     unsigned int reg)
308 {
309 	const struct sunxi_sramc_variant *variant;
310 
311 	variant = of_device_get_match_data(dev);
312 
313 	if (reg < SUNXI_SRAM_EMAC_CLOCK_REG)
314 		return false;
315 	if (reg > SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
316 		return false;
317 
318 	return true;
319 }
320 
321 static struct regmap_config sunxi_sram_emac_clock_regmap = {
322 	.reg_bits       = 32,
323 	.val_bits       = 32,
324 	.reg_stride     = 4,
325 	/* last defined register */
326 	.max_register   = SUNXI_SRAM_EMAC_CLOCK_REG + 4,
327 	/* other devices have no business accessing other registers */
328 	.readable_reg	= sunxi_sram_regmap_accessible_reg,
329 	.writeable_reg	= sunxi_sram_regmap_accessible_reg,
330 };
331 
sunxi_sram_probe(struct platform_device * pdev)332 static int sunxi_sram_probe(struct platform_device *pdev)
333 {
334 	struct dentry *d;
335 	struct regmap *emac_clock;
336 	const struct sunxi_sramc_variant *variant;
337 
338 	sram_dev = &pdev->dev;
339 
340 	variant = of_device_get_match_data(&pdev->dev);
341 	if (!variant)
342 		return -EINVAL;
343 
344 	base = devm_platform_ioremap_resource(pdev, 0);
345 	if (IS_ERR(base))
346 		return PTR_ERR(base);
347 
348 	of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
349 
350 	d = debugfs_create_file("sram", S_IRUGO, NULL, NULL,
351 				&sunxi_sram_fops);
352 	if (!d)
353 		return -ENOMEM;
354 
355 	if (variant->num_emac_clocks > 0) {
356 		emac_clock = devm_regmap_init_mmio(&pdev->dev, base,
357 						   &sunxi_sram_emac_clock_regmap);
358 
359 		if (IS_ERR(emac_clock))
360 			return PTR_ERR(emac_clock);
361 	}
362 
363 	return 0;
364 }
365 
366 static const struct of_device_id sunxi_sram_dt_match[] = {
367 	{
368 		.compatible = "allwinner,sun4i-a10-sram-controller",
369 		.data = &sun4i_a10_sramc_variant,
370 	},
371 	{
372 		.compatible = "allwinner,sun4i-a10-system-control",
373 		.data = &sun4i_a10_sramc_variant,
374 	},
375 	{
376 		.compatible = "allwinner,sun5i-a13-system-control",
377 		.data = &sun4i_a10_sramc_variant,
378 	},
379 	{
380 		.compatible = "allwinner,sun8i-a23-system-control",
381 		.data = &sun4i_a10_sramc_variant,
382 	},
383 	{
384 		.compatible = "allwinner,sun8i-h3-system-control",
385 		.data = &sun8i_h3_sramc_variant,
386 	},
387 	{
388 		.compatible = "allwinner,sun50i-a64-sram-controller",
389 		.data = &sun50i_a64_sramc_variant,
390 	},
391 	{
392 		.compatible = "allwinner,sun50i-a64-system-control",
393 		.data = &sun50i_a64_sramc_variant,
394 	},
395 	{
396 		.compatible = "allwinner,sun50i-h5-system-control",
397 		.data = &sun50i_a64_sramc_variant,
398 	},
399 	{
400 		.compatible = "allwinner,sun50i-h616-system-control",
401 		.data = &sun50i_h616_sramc_variant,
402 	},
403 	{ },
404 };
405 MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
406 
407 static struct platform_driver sunxi_sram_driver = {
408 	.driver = {
409 		.name		= "sunxi-sram",
410 		.of_match_table	= sunxi_sram_dt_match,
411 	},
412 	.probe	= sunxi_sram_probe,
413 };
414 module_platform_driver(sunxi_sram_driver);
415 
416 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
417 MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");
418 MODULE_LICENSE("GPL");
419