1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3
4 #ifndef _ICE_H_
5 #define _ICE_H_
6
7 #include <linux/types.h>
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/firmware.h>
12 #include <linux/netdevice.h>
13 #include <linux/compiler.h>
14 #include <linux/etherdevice.h>
15 #include <linux/skbuff.h>
16 #include <linux/cpumask.h>
17 #include <linux/rtnetlink.h>
18 #include <linux/if_vlan.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/pci.h>
21 #include <linux/workqueue.h>
22 #include <linux/wait.h>
23 #include <linux/aer.h>
24 #include <linux/interrupt.h>
25 #include <linux/ethtool.h>
26 #include <linux/timer.h>
27 #include <linux/delay.h>
28 #include <linux/bitmap.h>
29 #include <linux/log2.h>
30 #include <linux/ip.h>
31 #include <linux/sctp.h>
32 #include <linux/ipv6.h>
33 #include <linux/pkt_sched.h>
34 #include <linux/if_bridge.h>
35 #include <linux/ctype.h>
36 #include <linux/bpf.h>
37 #include <linux/btf.h>
38 #include <linux/auxiliary_bus.h>
39 #include <linux/avf/virtchnl.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/dim.h>
42 #include <net/pkt_cls.h>
43 #include <net/tc_act/tc_mirred.h>
44 #include <net/tc_act/tc_gact.h>
45 #include <net/ip.h>
46 #include <net/devlink.h>
47 #include <net/ipv6.h>
48 #include <net/xdp_sock.h>
49 #include <net/xdp_sock_drv.h>
50 #include <net/geneve.h>
51 #include <net/gre.h>
52 #include <net/udp_tunnel.h>
53 #include <net/vxlan.h>
54 #if IS_ENABLED(CONFIG_DCB)
55 #include <scsi/iscsi_proto.h>
56 #endif /* CONFIG_DCB */
57 #include "ice_devids.h"
58 #include "ice_type.h"
59 #include "ice_txrx.h"
60 #include "ice_dcb.h"
61 #include "ice_switch.h"
62 #include "ice_common.h"
63 #include "ice_flow.h"
64 #include "ice_sched.h"
65 #include "ice_idc_int.h"
66 #include "ice_virtchnl_pf.h"
67 #include "ice_sriov.h"
68 #include "ice_ptp.h"
69 #include "ice_fdir.h"
70 #include "ice_xsk.h"
71 #include "ice_arfs.h"
72 #include "ice_repr.h"
73 #include "ice_eswitch.h"
74 #include "ice_lag.h"
75
76 #define ICE_BAR0 0
77 #define ICE_REQ_DESC_MULTIPLE 32
78 #define ICE_MIN_NUM_DESC 64
79 #define ICE_MAX_NUM_DESC 8160
80 #define ICE_DFLT_MIN_RX_DESC 512
81 #define ICE_DFLT_NUM_TX_DESC 256
82 #define ICE_DFLT_NUM_RX_DESC 2048
83
84 #define ICE_DFLT_TRAFFIC_CLASS BIT(0)
85 #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16)
86 #define ICE_AQ_LEN 192
87 #define ICE_MBXSQ_LEN 64
88 #define ICE_SBQ_LEN 64
89 #define ICE_MIN_LAN_TXRX_MSIX 1
90 #define ICE_MIN_LAN_OICR_MSIX 1
91 #define ICE_MIN_MSIX (ICE_MIN_LAN_TXRX_MSIX + ICE_MIN_LAN_OICR_MSIX)
92 #define ICE_FDIR_MSIX 2
93 #define ICE_RDMA_NUM_AEQ_MSIX 4
94 #define ICE_MIN_RDMA_MSIX 2
95 #define ICE_ESWITCH_MSIX 1
96 #define ICE_NO_VSI 0xffff
97 #define ICE_VSI_MAP_CONTIG 0
98 #define ICE_VSI_MAP_SCATTER 1
99 #define ICE_MAX_SCATTER_TXQS 16
100 #define ICE_MAX_SCATTER_RXQS 16
101 #define ICE_Q_WAIT_RETRY_LIMIT 10
102 #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT)
103 #define ICE_MAX_LG_RSS_QS 256
104 #define ICE_RES_VALID_BIT 0x8000
105 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1)
106 #define ICE_RES_RDMA_VEC_ID (ICE_RES_MISC_VEC_ID - 1)
107 /* All VF control VSIs share the same IRQ, so assign a unique ID for them */
108 #define ICE_RES_VF_CTRL_VEC_ID (ICE_RES_RDMA_VEC_ID - 1)
109 #define ICE_INVAL_Q_INDEX 0xffff
110 #define ICE_INVAL_VFID 256
111
112 #define ICE_MAX_RXQS_PER_TC 256 /* Used when setting VSI context per TC Rx queues */
113
114 #define ICE_CHNL_START_TC 1
115 #define ICE_CHNL_MAX_TC 16
116
117 #define ICE_MAX_RESET_WAIT 20
118
119 #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4)
120
121 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
122
123 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD)
124
125 #define ICE_UP_TABLE_TRANSLATE(val, i) \
126 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
127 ICE_AQ_VSI_UP_TABLE_UP##i##_M)
128
129 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
130 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
131 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
132 #define ICE_TX_FDIRDESC(R, i) (&(((struct ice_fltr_desc *)((R)->desc))[i]))
133
134 /* Minimum BW limit is 500 Kbps for any scheduler node */
135 #define ICE_MIN_BW_LIMIT 500
136 /* User can specify BW in either Kbit/Mbit/Gbit and OS converts it in bytes.
137 * use it to convert user specified BW limit into Kbps
138 */
139 #define ICE_BW_KBPS_DIVISOR 125
140
141 /* Macro for each VSI in a PF */
142 #define ice_for_each_vsi(pf, i) \
143 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
144
145 /* Macros for each Tx/Xdp/Rx ring in a VSI */
146 #define ice_for_each_txq(vsi, i) \
147 for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
148
149 #define ice_for_each_xdp_txq(vsi, i) \
150 for ((i) = 0; (i) < (vsi)->num_xdp_txq; (i)++)
151
152 #define ice_for_each_rxq(vsi, i) \
153 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
154
155 /* Macros for each allocated Tx/Rx ring whether used or not in a VSI */
156 #define ice_for_each_alloc_txq(vsi, i) \
157 for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++)
158
159 #define ice_for_each_alloc_rxq(vsi, i) \
160 for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)
161
162 #define ice_for_each_q_vector(vsi, i) \
163 for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++)
164
165 #define ice_for_each_chnl_tc(i) \
166 for ((i) = ICE_CHNL_START_TC; (i) < ICE_CHNL_MAX_TC; (i)++)
167
168 #define ICE_UCAST_PROMISC_BITS (ICE_PROMISC_UCAST_TX | ICE_PROMISC_UCAST_RX)
169
170 #define ICE_UCAST_VLAN_PROMISC_BITS (ICE_PROMISC_UCAST_TX | \
171 ICE_PROMISC_UCAST_RX | \
172 ICE_PROMISC_VLAN_TX | \
173 ICE_PROMISC_VLAN_RX)
174
175 #define ICE_MCAST_PROMISC_BITS (ICE_PROMISC_MCAST_TX | ICE_PROMISC_MCAST_RX)
176
177 #define ICE_MCAST_VLAN_PROMISC_BITS (ICE_PROMISC_MCAST_TX | \
178 ICE_PROMISC_MCAST_RX | \
179 ICE_PROMISC_VLAN_TX | \
180 ICE_PROMISC_VLAN_RX)
181
182 #define ice_pf_to_dev(pf) (&((pf)->pdev->dev))
183
184 enum ice_feature {
185 ICE_F_DSCP,
186 ICE_F_SMA_CTRL,
187 ICE_F_MAX
188 };
189
190 DECLARE_STATIC_KEY_FALSE(ice_xdp_locking_key);
191
192 struct ice_channel {
193 struct list_head list;
194 u8 type;
195 u16 sw_id;
196 u16 base_q;
197 u16 num_rxq;
198 u16 num_txq;
199 u16 vsi_num;
200 u8 ena_tc;
201 struct ice_aqc_vsi_props info;
202 u64 max_tx_rate;
203 u64 min_tx_rate;
204 struct ice_vsi *ch_vsi;
205 };
206
207 struct ice_txq_meta {
208 u32 q_teid; /* Tx-scheduler element identifier */
209 u16 q_id; /* Entry in VSI's txq_map bitmap */
210 u16 q_handle; /* Relative index of Tx queue within TC */
211 u16 vsi_idx; /* VSI index that Tx queue belongs to */
212 u8 tc; /* TC number that Tx queue belongs to */
213 };
214
215 struct ice_tc_info {
216 u16 qoffset;
217 u16 qcount_tx;
218 u16 qcount_rx;
219 u8 netdev_tc;
220 };
221
222 struct ice_tc_cfg {
223 u8 numtc; /* Total number of enabled TCs */
224 u16 ena_tc; /* Tx map */
225 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
226 };
227
228 struct ice_res_tracker {
229 u16 num_entries;
230 u16 end;
231 u16 list[];
232 };
233
234 struct ice_qs_cfg {
235 struct mutex *qs_mutex; /* will be assigned to &pf->avail_q_mutex */
236 unsigned long *pf_map;
237 unsigned long pf_map_size;
238 unsigned int q_count;
239 unsigned int scatter_count;
240 u16 *vsi_map;
241 u16 vsi_map_offset;
242 u8 mapping_mode;
243 };
244
245 struct ice_sw {
246 struct ice_pf *pf;
247 u16 sw_id; /* switch ID for this switch */
248 u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */
249 struct ice_vsi *dflt_vsi; /* default VSI for this switch */
250 u8 dflt_vsi_ena:1; /* true if above dflt_vsi is enabled */
251 };
252
253 enum ice_pf_state {
254 ICE_TESTING,
255 ICE_DOWN,
256 ICE_NEEDS_RESTART,
257 ICE_PREPARED_FOR_RESET, /* set by driver when prepared */
258 ICE_RESET_OICR_RECV, /* set by driver after rcv reset OICR */
259 ICE_PFR_REQ, /* set by driver */
260 ICE_CORER_REQ, /* set by driver */
261 ICE_GLOBR_REQ, /* set by driver */
262 ICE_CORER_RECV, /* set by OICR handler */
263 ICE_GLOBR_RECV, /* set by OICR handler */
264 ICE_EMPR_RECV, /* set by OICR handler */
265 ICE_SUSPENDED, /* set on module remove path */
266 ICE_RESET_FAILED, /* set by reset/rebuild */
267 /* When checking for the PF to be in a nominal operating state, the
268 * bits that are grouped at the beginning of the list need to be
269 * checked. Bits occurring before ICE_STATE_NOMINAL_CHECK_BITS will
270 * be checked. If you need to add a bit into consideration for nominal
271 * operating state, it must be added before
272 * ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position
273 * without appropriate consideration.
274 */
275 ICE_STATE_NOMINAL_CHECK_BITS,
276 ICE_ADMINQ_EVENT_PENDING,
277 ICE_MAILBOXQ_EVENT_PENDING,
278 ICE_SIDEBANDQ_EVENT_PENDING,
279 ICE_MDD_EVENT_PENDING,
280 ICE_VFLR_EVENT_PENDING,
281 ICE_FLTR_OVERFLOW_PROMISC,
282 ICE_VF_DIS,
283 ICE_VF_DEINIT_IN_PROGRESS,
284 ICE_CFG_BUSY,
285 ICE_SERVICE_SCHED,
286 ICE_SERVICE_DIS,
287 ICE_FD_FLUSH_REQ,
288 ICE_OICR_INTR_DIS, /* Global OICR interrupt disabled */
289 ICE_MDD_VF_PRINT_PENDING, /* set when MDD event handle */
290 ICE_VF_RESETS_DISABLED, /* disable resets during ice_remove */
291 ICE_LINK_DEFAULT_OVERRIDE_PENDING,
292 ICE_PHY_INIT_COMPLETE,
293 ICE_FD_VF_FLUSH_CTX, /* set at FD Rx IRQ or timeout */
294 ICE_STATE_NBITS /* must be last */
295 };
296
297 enum ice_vsi_state {
298 ICE_VSI_DOWN,
299 ICE_VSI_NEEDS_RESTART,
300 ICE_VSI_NETDEV_ALLOCD,
301 ICE_VSI_NETDEV_REGISTERED,
302 ICE_VSI_UMAC_FLTR_CHANGED,
303 ICE_VSI_MMAC_FLTR_CHANGED,
304 ICE_VSI_VLAN_FLTR_CHANGED,
305 ICE_VSI_PROMISC_CHANGED,
306 ICE_VSI_STATE_NBITS /* must be last */
307 };
308
309 /* struct that defines a VSI, associated with a dev */
310 struct ice_vsi {
311 struct net_device *netdev;
312 struct ice_sw *vsw; /* switch this VSI is on */
313 struct ice_pf *back; /* back pointer to PF */
314 struct ice_port_info *port_info; /* back pointer to port_info */
315 struct ice_rx_ring **rx_rings; /* Rx ring array */
316 struct ice_tx_ring **tx_rings; /* Tx ring array */
317 struct ice_q_vector **q_vectors; /* q_vector array */
318
319 irqreturn_t (*irq_handler)(int irq, void *data);
320
321 u64 tx_linearize;
322 DECLARE_BITMAP(state, ICE_VSI_STATE_NBITS);
323 unsigned int current_netdev_flags;
324 u32 tx_restart;
325 u32 tx_busy;
326 u32 rx_buf_failed;
327 u32 rx_page_failed;
328 u16 num_q_vectors;
329 u16 base_vector; /* IRQ base for OS reserved vectors */
330 enum ice_vsi_type type;
331 u16 vsi_num; /* HW (absolute) index of this VSI */
332 u16 idx; /* software index in pf->vsi[] */
333
334 s16 vf_id; /* VF ID for SR-IOV VSIs */
335
336 u16 ethtype; /* Ethernet protocol for pause frame */
337 u16 num_gfltr;
338 u16 num_bfltr;
339
340 /* RSS config */
341 u16 rss_table_size; /* HW RSS table size */
342 u16 rss_size; /* Allocated RSS queues */
343 u8 *rss_hkey_user; /* User configured hash keys */
344 u8 *rss_lut_user; /* User configured lookup table entries */
345 u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */
346
347 /* aRFS members only allocated for the PF VSI */
348 #define ICE_MAX_ARFS_LIST 1024
349 #define ICE_ARFS_LST_MASK (ICE_MAX_ARFS_LIST - 1)
350 struct hlist_head *arfs_fltr_list;
351 struct ice_arfs_active_fltr_cntrs *arfs_fltr_cntrs;
352 spinlock_t arfs_lock; /* protects aRFS hash table and filter state */
353 atomic_t *arfs_last_fltr_id;
354
355 u16 max_frame;
356 u16 rx_buf_len;
357
358 struct ice_aqc_vsi_props info; /* VSI properties */
359
360 /* VSI stats */
361 struct rtnl_link_stats64 net_stats;
362 struct ice_eth_stats eth_stats;
363 struct ice_eth_stats eth_stats_prev;
364
365 struct list_head tmp_sync_list; /* MAC filters to be synced */
366 struct list_head tmp_unsync_list; /* MAC filters to be unsynced */
367
368 u8 irqs_ready:1;
369 u8 current_isup:1; /* Sync 'link up' logging */
370 u8 stat_offsets_loaded:1;
371 u16 num_vlan;
372
373 /* queue information */
374 u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
375 u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
376 u16 *txq_map; /* index in pf->avail_txqs */
377 u16 *rxq_map; /* index in pf->avail_rxqs */
378 u16 alloc_txq; /* Allocated Tx queues */
379 u16 num_txq; /* Used Tx queues */
380 u16 alloc_rxq; /* Allocated Rx queues */
381 u16 num_rxq; /* Used Rx queues */
382 u16 req_txq; /* User requested Tx queues */
383 u16 req_rxq; /* User requested Rx queues */
384 u16 num_rx_desc;
385 u16 num_tx_desc;
386 u16 qset_handle[ICE_MAX_TRAFFIC_CLASS];
387 struct ice_tc_cfg tc_cfg;
388 struct bpf_prog *xdp_prog;
389 struct ice_tx_ring **xdp_rings; /* XDP ring array */
390 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
391 u16 num_xdp_txq; /* Used XDP queues */
392 u8 xdp_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
393
394 struct net_device **target_netdevs;
395
396 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
397
398 /* Channel Specific Fields */
399 struct ice_vsi *tc_map_vsi[ICE_CHNL_MAX_TC];
400 u16 cnt_q_avail;
401 u16 next_base_q; /* next queue to be used for channel setup */
402 struct list_head ch_list;
403 u16 num_chnl_rxq;
404 u16 num_chnl_txq;
405 u16 ch_rss_size;
406 u16 num_chnl_fltr;
407 /* store away rss size info before configuring ADQ channels so that,
408 * it can be used after tc-qdisc delete, to get back RSS setting as
409 * they were before
410 */
411 u16 orig_rss_size;
412 /* this keeps tracks of all enabled TC with and without DCB
413 * and inclusive of ADQ, vsi->mqprio_opt keeps track of queue
414 * information
415 */
416 u8 all_numtc;
417 u16 all_enatc;
418
419 /* store away TC info, to be used for rebuild logic */
420 u8 old_numtc;
421 u16 old_ena_tc;
422
423 struct ice_channel *ch;
424
425 /* setup back reference, to which aggregator node this VSI
426 * corresponds to
427 */
428 struct ice_agg_node *agg_node;
429 } ____cacheline_internodealigned_in_smp;
430
431 /* struct that defines an interrupt vector */
432 struct ice_q_vector {
433 struct ice_vsi *vsi;
434
435 u16 v_idx; /* index in the vsi->q_vector array. */
436 u16 reg_idx;
437 u8 num_ring_rx; /* total number of Rx rings in vector */
438 u8 num_ring_tx; /* total number of Tx rings in vector */
439 u8 wb_on_itr:1; /* if true, WB on ITR is enabled */
440 /* in usecs, need to use ice_intrl_to_usecs_reg() before writing this
441 * value to the device
442 */
443 u8 intrl;
444
445 struct napi_struct napi;
446
447 struct ice_ring_container rx;
448 struct ice_ring_container tx;
449
450 cpumask_t affinity_mask;
451 struct irq_affinity_notify affinity_notify;
452
453 struct ice_channel *ch;
454
455 char name[ICE_INT_NAME_STR_LEN];
456
457 u16 total_events; /* net_dim(): number of interrupts processed */
458 } ____cacheline_internodealigned_in_smp;
459
460 enum ice_pf_flags {
461 ICE_FLAG_FLTR_SYNC,
462 ICE_FLAG_RDMA_ENA,
463 ICE_FLAG_RSS_ENA,
464 ICE_FLAG_SRIOV_ENA,
465 ICE_FLAG_SRIOV_CAPABLE,
466 ICE_FLAG_DCB_CAPABLE,
467 ICE_FLAG_DCB_ENA,
468 ICE_FLAG_FD_ENA,
469 ICE_FLAG_PTP_SUPPORTED, /* PTP is supported by NVM */
470 ICE_FLAG_PTP, /* PTP is enabled by software */
471 ICE_FLAG_AUX_ENA,
472 ICE_FLAG_ADV_FEATURES,
473 ICE_FLAG_TC_MQPRIO, /* support for Multi queue TC */
474 ICE_FLAG_CLS_FLOWER,
475 ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA,
476 ICE_FLAG_TOTAL_PORT_SHUTDOWN_ENA,
477 ICE_FLAG_NO_MEDIA,
478 ICE_FLAG_FW_LLDP_AGENT,
479 ICE_FLAG_MOD_POWER_UNSUPPORTED,
480 ICE_FLAG_PHY_FW_LOAD_FAILED,
481 ICE_FLAG_ETHTOOL_CTXT, /* set when ethtool holds RTNL lock */
482 ICE_FLAG_LEGACY_RX,
483 ICE_FLAG_VF_TRUE_PROMISC_ENA,
484 ICE_FLAG_MDD_AUTO_RESET_VF,
485 ICE_FLAG_LINK_LENIENT_MODE_ENA,
486 ICE_PF_FLAGS_NBITS /* must be last */
487 };
488
489 struct ice_switchdev_info {
490 struct ice_vsi *control_vsi;
491 struct ice_vsi *uplink_vsi;
492 bool is_running;
493 };
494
495 struct ice_agg_node {
496 u32 agg_id;
497 #define ICE_MAX_VSIS_IN_AGG_NODE 64
498 u32 num_vsis;
499 u8 valid;
500 };
501
502 struct ice_pf {
503 struct pci_dev *pdev;
504
505 struct devlink_region *nvm_region;
506 struct devlink_region *devcaps_region;
507
508 /* devlink port data */
509 struct devlink_port devlink_port;
510
511 /* OS reserved IRQ details */
512 struct msix_entry *msix_entries;
513 struct ice_res_tracker *irq_tracker;
514 /* First MSIX vector used by SR-IOV VFs. Calculated by subtracting the
515 * number of MSIX vectors needed for all SR-IOV VFs from the number of
516 * MSIX vectors allowed on this PF.
517 */
518 u16 sriov_base_vector;
519
520 u16 ctrl_vsi_idx; /* control VSI index in pf->vsi array */
521
522 struct ice_vsi **vsi; /* VSIs created by the driver */
523 struct ice_sw *first_sw; /* first switch created by firmware */
524 u16 eswitch_mode; /* current mode of eswitch */
525 /* Virtchnl/SR-IOV config info */
526 struct ice_vf *vf;
527 u16 num_alloc_vfs; /* actual number of VFs allocated */
528 u16 num_vfs_supported; /* num VFs supported for this PF */
529 u16 num_qps_per_vf;
530 u16 num_msix_per_vf;
531 /* used to ratelimit the MDD event logging */
532 unsigned long last_printed_mdd_jiffies;
533 DECLARE_BITMAP(malvfs, ICE_MAX_VF_COUNT);
534 DECLARE_BITMAP(features, ICE_F_MAX);
535 DECLARE_BITMAP(state, ICE_STATE_NBITS);
536 DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
537 unsigned long *avail_txqs; /* bitmap to track PF Tx queue usage */
538 unsigned long *avail_rxqs; /* bitmap to track PF Rx queue usage */
539 unsigned long serv_tmr_period;
540 unsigned long serv_tmr_prev;
541 struct timer_list serv_tmr;
542 struct work_struct serv_task;
543 struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */
544 struct mutex sw_mutex; /* lock for protecting VSI alloc flow */
545 struct mutex tc_mutex; /* lock to protect TC changes */
546 u32 msg_enable;
547 struct ice_ptp ptp;
548 u16 num_rdma_msix; /* Total MSIX vectors for RDMA driver */
549 u16 rdma_base_vector;
550
551 /* spinlock to protect the AdminQ wait list */
552 spinlock_t aq_wait_lock;
553 struct hlist_head aq_wait_list;
554 wait_queue_head_t aq_wait_queue;
555
556 wait_queue_head_t reset_wait_queue;
557
558 u32 hw_csum_rx_error;
559 u16 oicr_idx; /* Other interrupt cause MSIX vector index */
560 u16 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */
561 u16 max_pf_txqs; /* Total Tx queues PF wide */
562 u16 max_pf_rxqs; /* Total Rx queues PF wide */
563 u16 num_lan_msix; /* Total MSIX vectors for base driver */
564 u16 num_lan_tx; /* num LAN Tx queues setup */
565 u16 num_lan_rx; /* num LAN Rx queues setup */
566 u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */
567 u16 num_alloc_vsi;
568 u16 corer_count; /* Core reset count */
569 u16 globr_count; /* Global reset count */
570 u16 empr_count; /* EMP reset count */
571 u16 pfr_count; /* PF reset count */
572
573 u8 wol_ena : 1; /* software state of WoL */
574 u32 wakeup_reason; /* last wakeup reason */
575 struct ice_hw_port_stats stats;
576 struct ice_hw_port_stats stats_prev;
577 struct ice_hw hw;
578 u8 stat_prev_loaded:1; /* has previous stats been loaded */
579 u16 dcbx_cap;
580 u32 tx_timeout_count;
581 unsigned long tx_timeout_last_recovery;
582 u32 tx_timeout_recovery_level;
583 char int_name[ICE_INT_NAME_STR_LEN];
584 struct auxiliary_device *adev;
585 int aux_idx;
586 u32 sw_int_count;
587 /* count of tc_flower filters specific to channel (aka where filter
588 * action is "hw_tc <tc_num>")
589 */
590 u16 num_dmac_chnl_fltrs;
591 struct hlist_head tc_flower_fltr_list;
592
593 __le64 nvm_phy_type_lo; /* NVM PHY type low */
594 __le64 nvm_phy_type_hi; /* NVM PHY type high */
595 struct ice_link_default_override_tlv link_dflt_override;
596 struct ice_lag *lag; /* Link Aggregation information */
597
598 struct ice_switchdev_info switchdev;
599
600 #define ICE_INVALID_AGG_NODE_ID 0
601 #define ICE_PF_AGG_NODE_ID_START 1
602 #define ICE_MAX_PF_AGG_NODES 32
603 struct ice_agg_node pf_agg_node[ICE_MAX_PF_AGG_NODES];
604 #define ICE_VF_AGG_NODE_ID_START 65
605 #define ICE_MAX_VF_AGG_NODES 32
606 struct ice_agg_node vf_agg_node[ICE_MAX_VF_AGG_NODES];
607 };
608
609 struct ice_netdev_priv {
610 struct ice_vsi *vsi;
611 struct ice_repr *repr;
612 /* indirect block callbacks on registered higher level devices
613 * (e.g. tunnel devices)
614 *
615 * tc_indr_block_cb_priv_list is used to look up indirect callback
616 * private data
617 */
618 struct list_head tc_indr_block_priv_list;
619 };
620
621 /**
622 * ice_vector_ch_enabled
623 * @qv: pointer to q_vector, can be NULL
624 *
625 * This function returns true if vector is channel enabled otherwise false
626 */
ice_vector_ch_enabled(struct ice_q_vector * qv)627 static inline bool ice_vector_ch_enabled(struct ice_q_vector *qv)
628 {
629 return !!qv->ch; /* Enable it to run with TC */
630 }
631
632 /**
633 * ice_irq_dynamic_ena - Enable default interrupt generation settings
634 * @hw: pointer to HW struct
635 * @vsi: pointer to VSI struct, can be NULL
636 * @q_vector: pointer to q_vector, can be NULL
637 */
638 static inline void
ice_irq_dynamic_ena(struct ice_hw * hw,struct ice_vsi * vsi,struct ice_q_vector * q_vector)639 ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
640 struct ice_q_vector *q_vector)
641 {
642 u32 vector = (vsi && q_vector) ? q_vector->reg_idx :
643 ((struct ice_pf *)hw->back)->oicr_idx;
644 int itr = ICE_ITR_NONE;
645 u32 val;
646
647 /* clear the PBA here, as this function is meant to clean out all
648 * previous interrupts and enable the interrupt
649 */
650 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
651 (itr << GLINT_DYN_CTL_ITR_INDX_S);
652 if (vsi)
653 if (test_bit(ICE_VSI_DOWN, vsi->state))
654 return;
655 wr32(hw, GLINT_DYN_CTL(vector), val);
656 }
657
658 /**
659 * ice_netdev_to_pf - Retrieve the PF struct associated with a netdev
660 * @netdev: pointer to the netdev struct
661 */
ice_netdev_to_pf(struct net_device * netdev)662 static inline struct ice_pf *ice_netdev_to_pf(struct net_device *netdev)
663 {
664 struct ice_netdev_priv *np = netdev_priv(netdev);
665
666 return np->vsi->back;
667 }
668
ice_is_xdp_ena_vsi(struct ice_vsi * vsi)669 static inline bool ice_is_xdp_ena_vsi(struct ice_vsi *vsi)
670 {
671 return !!vsi->xdp_prog;
672 }
673
ice_set_ring_xdp(struct ice_tx_ring * ring)674 static inline void ice_set_ring_xdp(struct ice_tx_ring *ring)
675 {
676 ring->flags |= ICE_TX_FLAGS_RING_XDP;
677 }
678
679 /**
680 * ice_xsk_pool - get XSK buffer pool bound to a ring
681 * @ring: Rx ring to use
682 *
683 * Returns a pointer to xdp_umem structure if there is a buffer pool present,
684 * NULL otherwise.
685 */
ice_xsk_pool(struct ice_rx_ring * ring)686 static inline struct xsk_buff_pool *ice_xsk_pool(struct ice_rx_ring *ring)
687 {
688 struct ice_vsi *vsi = ring->vsi;
689 u16 qid = ring->q_index;
690
691 if (!ice_is_xdp_ena_vsi(vsi) || !test_bit(qid, vsi->af_xdp_zc_qps))
692 return NULL;
693
694 return xsk_get_pool_from_qid(vsi->netdev, qid);
695 }
696
697 /**
698 * ice_tx_xsk_pool - get XSK buffer pool bound to a ring
699 * @ring: Tx ring to use
700 *
701 * Returns a pointer to xdp_umem structure if there is a buffer pool present,
702 * NULL otherwise. Tx equivalent of ice_xsk_pool.
703 */
ice_tx_xsk_pool(struct ice_tx_ring * ring)704 static inline struct xsk_buff_pool *ice_tx_xsk_pool(struct ice_tx_ring *ring)
705 {
706 struct ice_vsi *vsi = ring->vsi;
707 u16 qid;
708
709 qid = ring->q_index - vsi->num_xdp_txq;
710
711 if (!ice_is_xdp_ena_vsi(vsi) || !test_bit(qid, vsi->af_xdp_zc_qps))
712 return NULL;
713
714 return xsk_get_pool_from_qid(vsi->netdev, qid);
715 }
716
717 /**
718 * ice_get_main_vsi - Get the PF VSI
719 * @pf: PF instance
720 *
721 * returns pf->vsi[0], which by definition is the PF VSI
722 */
ice_get_main_vsi(struct ice_pf * pf)723 static inline struct ice_vsi *ice_get_main_vsi(struct ice_pf *pf)
724 {
725 if (pf->vsi)
726 return pf->vsi[0];
727
728 return NULL;
729 }
730
731 /**
732 * ice_get_netdev_priv_vsi - return VSI associated with netdev priv.
733 * @np: private netdev structure
734 */
ice_get_netdev_priv_vsi(struct ice_netdev_priv * np)735 static inline struct ice_vsi *ice_get_netdev_priv_vsi(struct ice_netdev_priv *np)
736 {
737 /* In case of port representor return source port VSI. */
738 if (np->repr)
739 return np->repr->src_vsi;
740 else
741 return np->vsi;
742 }
743
744 /**
745 * ice_get_ctrl_vsi - Get the control VSI
746 * @pf: PF instance
747 */
ice_get_ctrl_vsi(struct ice_pf * pf)748 static inline struct ice_vsi *ice_get_ctrl_vsi(struct ice_pf *pf)
749 {
750 /* if pf->ctrl_vsi_idx is ICE_NO_VSI, control VSI was not set up */
751 if (!pf->vsi || pf->ctrl_vsi_idx == ICE_NO_VSI)
752 return NULL;
753
754 return pf->vsi[pf->ctrl_vsi_idx];
755 }
756
757 /**
758 * ice_is_switchdev_running - check if switchdev is configured
759 * @pf: pointer to PF structure
760 *
761 * Returns true if eswitch mode is set to DEVLINK_ESWITCH_MODE_SWITCHDEV
762 * and switchdev is configured, false otherwise.
763 */
ice_is_switchdev_running(struct ice_pf * pf)764 static inline bool ice_is_switchdev_running(struct ice_pf *pf)
765 {
766 return pf->switchdev.is_running;
767 }
768
769 /**
770 * ice_set_sriov_cap - enable SRIOV in PF flags
771 * @pf: PF struct
772 */
ice_set_sriov_cap(struct ice_pf * pf)773 static inline void ice_set_sriov_cap(struct ice_pf *pf)
774 {
775 if (pf->hw.func_caps.common_cap.sr_iov_1_1)
776 set_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
777 }
778
779 /**
780 * ice_clear_sriov_cap - disable SRIOV in PF flags
781 * @pf: PF struct
782 */
ice_clear_sriov_cap(struct ice_pf * pf)783 static inline void ice_clear_sriov_cap(struct ice_pf *pf)
784 {
785 clear_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
786 }
787
788 #define ICE_FD_STAT_CTR_BLOCK_COUNT 256
789 #define ICE_FD_STAT_PF_IDX(base_idx) \
790 ((base_idx) * ICE_FD_STAT_CTR_BLOCK_COUNT)
791 #define ICE_FD_SB_STAT_IDX(base_idx) ICE_FD_STAT_PF_IDX(base_idx)
792
793 /**
794 * ice_is_adq_active - any active ADQs
795 * @pf: pointer to PF
796 *
797 * This function returns true if there are any ADQs configured (which is
798 * determined by looking at VSI type (which should be VSI_PF), numtc, and
799 * TC_MQPRIO flag) otherwise return false
800 */
ice_is_adq_active(struct ice_pf * pf)801 static inline bool ice_is_adq_active(struct ice_pf *pf)
802 {
803 struct ice_vsi *vsi;
804
805 vsi = ice_get_main_vsi(pf);
806 if (!vsi)
807 return false;
808
809 /* is ADQ configured */
810 if (vsi->tc_cfg.numtc > ICE_CHNL_START_TC &&
811 test_bit(ICE_FLAG_TC_MQPRIO, pf->flags))
812 return true;
813
814 return false;
815 }
816
817 bool netif_is_ice(struct net_device *dev);
818 int ice_vsi_setup_tx_rings(struct ice_vsi *vsi);
819 int ice_vsi_setup_rx_rings(struct ice_vsi *vsi);
820 int ice_vsi_open_ctrl(struct ice_vsi *vsi);
821 int ice_vsi_open(struct ice_vsi *vsi);
822 void ice_set_ethtool_ops(struct net_device *netdev);
823 void ice_set_ethtool_repr_ops(struct net_device *netdev);
824 void ice_set_ethtool_safe_mode_ops(struct net_device *netdev);
825 u16 ice_get_avail_txq_count(struct ice_pf *pf);
826 u16 ice_get_avail_rxq_count(struct ice_pf *pf);
827 int ice_vsi_recfg_qs(struct ice_vsi *vsi, int new_rx, int new_tx);
828 void ice_update_vsi_stats(struct ice_vsi *vsi);
829 void ice_update_pf_stats(struct ice_pf *pf);
830 int ice_up(struct ice_vsi *vsi);
831 int ice_down(struct ice_vsi *vsi);
832 int ice_vsi_cfg(struct ice_vsi *vsi);
833 struct ice_vsi *ice_lb_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi);
834 int ice_vsi_determine_xdp_res(struct ice_vsi *vsi);
835 int ice_prepare_xdp_rings(struct ice_vsi *vsi, struct bpf_prog *prog);
836 int ice_destroy_xdp_rings(struct ice_vsi *vsi);
837 int
838 ice_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
839 u32 flags);
840 int ice_set_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size);
841 int ice_get_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size);
842 int ice_set_rss_key(struct ice_vsi *vsi, u8 *seed);
843 int ice_get_rss_key(struct ice_vsi *vsi, u8 *seed);
844 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
845 int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset);
846 void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
847 int ice_plug_aux_dev(struct ice_pf *pf);
848 void ice_unplug_aux_dev(struct ice_pf *pf);
849 int ice_init_rdma(struct ice_pf *pf);
850 const char *ice_stat_str(enum ice_status stat_err);
851 const char *ice_aq_str(enum ice_aq_err aq_err);
852 bool ice_is_wol_supported(struct ice_hw *hw);
853 int
854 ice_fdir_write_fltr(struct ice_pf *pf, struct ice_fdir_fltr *input, bool add,
855 bool is_tun);
856 void ice_vsi_manage_fdir(struct ice_vsi *vsi, bool ena);
857 int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
858 int ice_del_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
859 int ice_get_ethtool_fdir_entry(struct ice_hw *hw, struct ethtool_rxnfc *cmd);
860 int
861 ice_get_fdir_fltr_ids(struct ice_hw *hw, struct ethtool_rxnfc *cmd,
862 u32 *rule_locs);
863 void ice_fdir_release_flows(struct ice_hw *hw);
864 void ice_fdir_replay_flows(struct ice_hw *hw);
865 void ice_fdir_replay_fltrs(struct ice_pf *pf);
866 int ice_fdir_create_dflt_rules(struct ice_pf *pf);
867 int ice_aq_wait_for_event(struct ice_pf *pf, u16 opcode, unsigned long timeout,
868 struct ice_rq_event_info *event);
869 int ice_open(struct net_device *netdev);
870 int ice_open_internal(struct net_device *netdev);
871 int ice_stop(struct net_device *netdev);
872 void ice_service_task_schedule(struct ice_pf *pf);
873
874 /**
875 * ice_set_rdma_cap - enable RDMA support
876 * @pf: PF struct
877 */
ice_set_rdma_cap(struct ice_pf * pf)878 static inline void ice_set_rdma_cap(struct ice_pf *pf)
879 {
880 if (pf->hw.func_caps.common_cap.rdma && pf->num_rdma_msix) {
881 set_bit(ICE_FLAG_RDMA_ENA, pf->flags);
882 set_bit(ICE_FLAG_AUX_ENA, pf->flags);
883 ice_plug_aux_dev(pf);
884 }
885 }
886
887 /**
888 * ice_clear_rdma_cap - disable RDMA support
889 * @pf: PF struct
890 */
ice_clear_rdma_cap(struct ice_pf * pf)891 static inline void ice_clear_rdma_cap(struct ice_pf *pf)
892 {
893 ice_unplug_aux_dev(pf);
894 clear_bit(ICE_FLAG_RDMA_ENA, pf->flags);
895 clear_bit(ICE_FLAG_AUX_ENA, pf->flags);
896 }
897 #endif /* _ICE_H_ */
898