1 /*
2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9
10 #include <arch_helpers.h>
11 #include <bl31/interrupt_mgmt.h>
12 #include <bl31/ehf.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <context.h>
16 #include <denver.h>
17 #include <lib/el3_runtime/context_mgmt.h>
18 #include <plat/common/platform.h>
19
20 #if ENABLE_WDT_LEGACY_FIQ_HANDLING
21 #include <flowctrl.h>
22 #endif
23 #include <tegra_def.h>
24 #include <tegra_private.h>
25
26 /* Legacy FIQ used by earlier Tegra platforms */
27 #define LEGACY_FIQ_PPI_WDT 28U
28
29 /*******************************************************************************
30 * Static variables
31 ******************************************************************************/
32 static uint64_t ns_fiq_handler_addr;
33 static uint32_t fiq_handler_active;
34 static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT];
35
36 /*******************************************************************************
37 * Handler for FIQ interrupts
38 ******************************************************************************/
tegra_fiq_interrupt_handler(unsigned int id,unsigned int flags,void * handle,void * cookie)39 static int tegra_fiq_interrupt_handler(unsigned int id, unsigned int flags,
40 void *handle, void *cookie)
41 {
42 cpu_context_t *ctx = cm_get_context(NON_SECURE);
43 el3_state_t *el3state_ctx = get_el3state_ctx(ctx);
44 uint32_t cpu = plat_my_core_pos();
45
46 (void)flags;
47 (void)handle;
48 (void)cookie;
49
50 /*
51 * Jump to NS world only if the NS world's FIQ handler has
52 * been registered
53 */
54 if (ns_fiq_handler_addr != 0U) {
55
56 /*
57 * The FIQ was generated when the execution was in the non-secure
58 * world. Save the context registers to start with.
59 */
60 cm_el1_sysregs_context_save(NON_SECURE);
61
62 /*
63 * Save elr_el3 and spsr_el3 from the saved context, and overwrite
64 * the context with the NS fiq_handler_addr and SPSR value.
65 */
66 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3));
67 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3));
68
69 /*
70 * Set the new ELR to continue execution in the NS world using the
71 * FIQ handler registered earlier.
72 */
73 cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr);
74 }
75
76 #if ENABLE_WDT_LEGACY_FIQ_HANDLING
77 /*
78 * Tegra platforms that use LEGACY_FIQ as the watchdog timer FIQ
79 * need to issue an IPI to other CPUs, to allow them to handle
80 * the "system hung" scenario. This interrupt is passed to the GICD
81 * via the Flow Controller. So, once we receive this interrupt,
82 * disable the routing so that we can mark it as "complete" in the
83 * GIC later.
84 */
85 if (id == LEGACY_FIQ_PPI_WDT) {
86 tegra_fc_disable_fiq_to_ccplex_routing();
87 }
88 #endif
89
90 /*
91 * Mark this interrupt as complete to avoid a FIQ storm.
92 */
93 plat_ic_end_of_interrupt(id);
94
95 return 0;
96 }
97
98 /*******************************************************************************
99 * Setup handler for FIQ interrupts
100 ******************************************************************************/
tegra_fiq_handler_setup(void)101 void tegra_fiq_handler_setup(void)
102 {
103 /* return if already registered */
104 if (fiq_handler_active == 0U) {
105 /*
106 * Register an interrupt handler for FIQ interrupts generated for
107 * NS interrupt sources
108 */
109 ehf_register_priority_handler(PLAT_TEGRA_WDT_PRIO, tegra_fiq_interrupt_handler);
110
111 /* handler is now active */
112 fiq_handler_active = 1;
113 }
114 }
115
116 /*******************************************************************************
117 * Validate and store NS world's entrypoint for FIQ interrupts
118 ******************************************************************************/
tegra_fiq_set_ns_entrypoint(uint64_t entrypoint)119 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint)
120 {
121 ns_fiq_handler_addr = entrypoint;
122 }
123
124 /*******************************************************************************
125 * Handler to return the NS EL1/EL0 CPU context
126 ******************************************************************************/
tegra_fiq_get_intr_context(void)127 int32_t tegra_fiq_get_intr_context(void)
128 {
129 cpu_context_t *ctx = cm_get_context(NON_SECURE);
130 gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx);
131 const el1_sysregs_t *el1state_ctx = get_el1_sysregs_ctx(ctx);
132 uint32_t cpu = plat_my_core_pos();
133 uint64_t val;
134
135 /*
136 * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so
137 * that el3_exit() sends these values back to the NS world.
138 */
139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3));
140 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3));
141
142 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0));
143 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val));
144
145 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1));
146 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val));
147
148 return 0;
149 }
150