1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * ti_usb_phy.c - USB3 and USB3 PHY programming for dwc3
4 *
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Author: Kishon Vijay Abraham I <kishon@ti.com>
8 *
9 * Taken from Linux Kernel v3.16 (drivers/phy/phy-ti-pipe3.c and
10 * drivers/phy/phy-omap-usb2.c) and ported to uboot.
11 *
12 * "commit 56042e : phy: ti-pipe3: Fix suspend/resume and module reload" for
13 * phy-ti-pipe3.c
14 *
15 * "commit eb82a3 : phy: omap-usb2: Balance pm_runtime_enable() on probe failure
16 * and remove" for phy-omap-usb2.c
17 */
18
19 #include <common.h>
20 #include <malloc.h>
21 #include <ti-usb-phy-uboot.h>
22 #include <dm/device_compat.h>
23 #include <dm/devres.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <asm/io.h>
28 #include <asm/arch/sys_proto.h>
29 #include <dm.h>
30
31 #include "linux-compat.h"
32
33 #define PLL_STATUS 0x00000004
34 #define PLL_GO 0x00000008
35 #define PLL_CONFIGURATION1 0x0000000C
36 #define PLL_CONFIGURATION2 0x00000010
37 #define PLL_CONFIGURATION3 0x00000014
38 #define PLL_CONFIGURATION4 0x00000020
39
40 #define PLL_REGM_MASK 0x001FFE00
41 #define PLL_REGM_SHIFT 0x9
42 #define PLL_REGM_F_MASK 0x0003FFFF
43 #define PLL_REGM_F_SHIFT 0x0
44 #define PLL_REGN_MASK 0x000001FE
45 #define PLL_REGN_SHIFT 0x1
46 #define PLL_SELFREQDCO_MASK 0x0000000E
47 #define PLL_SELFREQDCO_SHIFT 0x1
48 #define PLL_SD_MASK 0x0003FC00
49 #define PLL_SD_SHIFT 10
50 #define SET_PLL_GO 0x1
51 #define PLL_LDOPWDN BIT(15)
52 #define PLL_TICOPWDN BIT(16)
53 #define PLL_LOCK 0x2
54 #define PLL_IDLE 0x1
55
56 #define OMAP_CTRL_DEV_PHY_PD BIT(0)
57 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
58 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
59
60 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
61 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
62
63 #define OMAP_CTRL_USB3_PHY_TX_RX_POWERON 0x3
64 #define OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF 0x0
65
66 #define OMAP_CTRL_USB2_PHY_PD BIT(28)
67
68 #define AM437X_CTRL_USB2_PHY_PD BIT(0)
69 #define AM437X_CTRL_USB2_OTG_PD BIT(1)
70 #define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
71 #define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20)
72
73 static LIST_HEAD(ti_usb_phy_list);
74 typedef unsigned int u32;
75
76 struct usb3_dpll_params {
77 u16 m;
78 u8 n;
79 u8 freq:3;
80 u8 sd;
81 u32 mf;
82 };
83
84 struct usb3_dpll_map {
85 unsigned long rate;
86 struct usb3_dpll_params params;
87 struct usb3_dpll_map *dpll_map;
88 };
89
90 struct ti_usb_phy {
91 void __iomem *pll_ctrl_base;
92 void __iomem *usb2_phy_power;
93 void __iomem *usb3_phy_power;
94 struct usb3_dpll_map *dpll_map;
95 struct list_head list;
96 int index;
97 };
98
99 static struct usb3_dpll_map dpll_map_usb[] = {
100 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
101 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
102 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
103 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
104 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
105 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
106 { }, /* Terminator */
107 };
108
ti_usb3_readl(void __iomem * base,u32 offset)109 static inline unsigned int ti_usb3_readl(void __iomem *base, u32 offset)
110 {
111 return readl(base + offset);
112 }
113
ti_usb3_writel(void __iomem * base,u32 offset,u32 value)114 static inline void ti_usb3_writel(void __iomem *base, u32 offset, u32 value)
115 {
116 writel(value, base + offset);
117 }
118
119 #ifndef CONFIG_AM43XX
ti_usb3_get_dpll_params(struct ti_usb_phy * phy)120 static struct usb3_dpll_params *ti_usb3_get_dpll_params(struct ti_usb_phy *phy)
121 {
122 unsigned long rate;
123 struct usb3_dpll_map *dpll_map = phy->dpll_map;
124
125 rate = get_sys_clk_freq();
126
127 for (; dpll_map->rate; dpll_map++) {
128 if (rate == dpll_map->rate)
129 return &dpll_map->params;
130 }
131
132 log_err("No DPLL configuration for %lu Hz SYS CLK\n", rate);
133
134 return NULL;
135 }
136
ti_usb3_dpll_wait_lock(struct ti_usb_phy * phy)137 static int ti_usb3_dpll_wait_lock(struct ti_usb_phy *phy)
138 {
139 u32 val;
140 do {
141 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_STATUS);
142 if (val & PLL_LOCK)
143 break;
144 } while (1);
145
146 return 0;
147 }
148
ti_usb3_dpll_program(struct ti_usb_phy * phy)149 static int ti_usb3_dpll_program(struct ti_usb_phy *phy)
150 {
151 u32 val;
152 struct usb3_dpll_params *dpll_params;
153
154 if (!phy->pll_ctrl_base)
155 return -EINVAL;
156
157 dpll_params = ti_usb3_get_dpll_params(phy);
158 if (!dpll_params)
159 return -EINVAL;
160
161 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
162 val &= ~PLL_REGN_MASK;
163 val |= dpll_params->n << PLL_REGN_SHIFT;
164 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
165
166 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
167 val &= ~PLL_SELFREQDCO_MASK;
168 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
169 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
170
171 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
172 val &= ~PLL_REGM_MASK;
173 val |= dpll_params->m << PLL_REGM_SHIFT;
174 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
175
176 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
177 val &= ~PLL_REGM_F_MASK;
178 val |= dpll_params->mf << PLL_REGM_F_SHIFT;
179 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
180
181 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
182 val &= ~PLL_SD_MASK;
183 val |= dpll_params->sd << PLL_SD_SHIFT;
184 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
185
186 ti_usb3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
187
188 return ti_usb3_dpll_wait_lock(phy);
189 }
190 #endif
191
ti_usb2_phy_power(struct ti_usb_phy * phy,int on)192 void ti_usb2_phy_power(struct ti_usb_phy *phy, int on)
193 {
194 u32 val;
195
196 val = readl(phy->usb2_phy_power);
197
198 if (on) {
199 #if defined(CONFIG_DRA7XX)
200 if (phy->index == 1)
201 val &= ~OMAP_CTRL_USB2_PHY_PD;
202 else
203 val &= ~OMAP_CTRL_DEV_PHY_PD;
204 #elif defined(CONFIG_AM43XX)
205 val &= ~(AM437X_CTRL_USB2_PHY_PD |
206 AM437X_CTRL_USB2_OTG_PD);
207 val |= (AM437X_CTRL_USB2_OTGVDET_EN |
208 AM437X_CTRL_USB2_OTGSESSEND_EN);
209 #endif
210 } else {
211 #if defined(CONFIG_DRA7XX)
212 if (phy->index == 1)
213 val |= OMAP_CTRL_USB2_PHY_PD;
214 else
215 val |= OMAP_CTRL_DEV_PHY_PD;
216
217 #elif defined(CONFIG_AM43XX)
218 val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
219 AM437X_CTRL_USB2_OTGSESSEND_EN);
220 val |= (AM437X_CTRL_USB2_PHY_PD |
221 AM437X_CTRL_USB2_OTG_PD);
222 #endif
223 }
224 writel(val, phy->usb2_phy_power);
225 }
226
227 #ifndef CONFIG_AM43XX
ti_usb3_phy_power(struct ti_usb_phy * phy,int on)228 void ti_usb3_phy_power(struct ti_usb_phy *phy, int on)
229 {
230 u32 val;
231 u32 rate;
232 rate = get_sys_clk_freq();
233 rate = rate/1000000;
234
235 if (!phy->usb3_phy_power)
236 return;
237
238 val = readl(phy->usb3_phy_power);
239 if (on) {
240 val &= ~(OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK |
241 OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK);
242 val |= (OMAP_CTRL_USB3_PHY_TX_RX_POWERON) <<
243 OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
244 val |= rate <<
245 OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT;
246 } else {
247 val &= ~OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK;
248 val |= OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF <<
249 OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
250 }
251 writel(val, phy->usb3_phy_power);
252 }
253 #endif
254
255 /**
256 * ti_usb_phy_uboot_init - usb phy uboot initialization code
257 * @dev: struct ti_usb_phy_device containing initialization data
258 *
259 * Entry point for ti usb phy driver. This driver handles initialization
260 * of both usb2 phy and usb3 phy. Pointer to ti_usb_phy_device should be
261 * passed containing base address and other initialization data.
262 * Returns '0' on success and a negative value on failure.
263 *
264 * Generally called from board_usb_init() implemented in board file.
265 */
ti_usb_phy_uboot_init(struct ti_usb_phy_device * dev)266 int ti_usb_phy_uboot_init(struct ti_usb_phy_device *dev)
267 {
268 struct ti_usb_phy *phy;
269
270 phy = devm_kzalloc(NULL, sizeof(*phy), GFP_KERNEL);
271 if (!phy) {
272 log_err("unable to alloc mem for TI USB3 PHY\n");
273 return -ENOMEM;
274 }
275
276 phy->dpll_map = dpll_map_usb;
277 phy->index = dev->index;
278 phy->pll_ctrl_base = dev->pll_ctrl_base;
279 phy->usb2_phy_power = dev->usb2_phy_power;
280 phy->usb3_phy_power = dev->usb3_phy_power;
281
282 #ifndef CONFIG_AM43XX
283 ti_usb3_dpll_program(phy);
284 ti_usb3_phy_power(phy, 1);
285 #endif
286 ti_usb2_phy_power(phy, 1);
287 mdelay(150);
288 list_add_tail(&phy->list, &ti_usb_phy_list);
289
290 return 0;
291 }
292
293 /**
294 * ti_usb_phy_uboot_exit - usb phy uboot cleanup code
295 * @index: index of this controller
296 *
297 * Performs cleanup of memory allocated in ti_usb_phy_uboot_init.
298 * index of _this_ controller should be passed and should match with
299 * the index passed in ti_usb_phy_device during init.
300 *
301 * Generally called from board file.
302 */
ti_usb_phy_uboot_exit(int index)303 void ti_usb_phy_uboot_exit(int index)
304 {
305 struct ti_usb_phy *phy = NULL;
306
307 list_for_each_entry(phy, &ti_usb_phy_list, list) {
308 if (phy->index != index)
309 continue;
310
311 ti_usb2_phy_power(phy, 0);
312 #ifndef CONFIG_AM43XX
313 ti_usb3_phy_power(phy, 0);
314 #endif
315 list_del(&phy->list);
316 kfree(phy);
317 break;
318 }
319 }
320