1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018-2021 Intel Corporation. All rights reserved.
7 //
8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 //
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <sound/soc-acpi.h>
14 #include <sound/soc-acpi-intel-match.h>
15 #include <sound/sof.h>
16 #include "../ops.h"
17 #include "atom.h"
18 #include "../sof-pci-dev.h"
19 #include "../sof-audio.h"
20
21 /* platform specific devices */
22 #include "shim.h"
23
24 static struct snd_soc_acpi_mach sof_tng_machines[] = {
25 {
26 .id = "INT343A",
27 .drv_name = "edison",
28 .sof_fw_filename = "sof-byt.ri",
29 .sof_tplg_filename = "sof-byt.tplg",
30 },
31 {}
32 };
33
34 static const struct snd_sof_debugfs_map tng_debugfs[] = {
35 {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
36 SOF_DEBUGFS_ACCESS_ALWAYS},
37 {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
38 SOF_DEBUGFS_ACCESS_ALWAYS},
39 {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
40 SOF_DEBUGFS_ACCESS_ALWAYS},
41 {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
42 SOF_DEBUGFS_ACCESS_ALWAYS},
43 {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
44 SOF_DEBUGFS_ACCESS_ALWAYS},
45 {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
46 SOF_DEBUGFS_ACCESS_D0_ONLY},
47 {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
48 SOF_DEBUGFS_ACCESS_D0_ONLY},
49 {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
50 SOF_DEBUGFS_ACCESS_ALWAYS},
51 };
52
tangier_pci_probe(struct snd_sof_dev * sdev)53 static int tangier_pci_probe(struct snd_sof_dev *sdev)
54 {
55 struct snd_sof_pdata *pdata = sdev->pdata;
56 const struct sof_dev_desc *desc = pdata->desc;
57 struct pci_dev *pci = to_pci_dev(sdev->dev);
58 u32 base, size;
59 int ret;
60
61 /* DSP DMA can only access low 31 bits of host memory */
62 ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
63 if (ret < 0) {
64 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
65 return ret;
66 }
67
68 /* LPE base */
69 base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
70 size = PCI_BAR_SIZE;
71
72 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
73 sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
74 if (!sdev->bar[DSP_BAR]) {
75 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
76 base, size);
77 return -ENODEV;
78 }
79 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
80
81 /* IMR base - optional */
82 if (desc->resindex_imr_base == -1)
83 goto irq;
84
85 base = pci_resource_start(pci, desc->resindex_imr_base);
86 size = pci_resource_len(pci, desc->resindex_imr_base);
87
88 /* some BIOSes don't map IMR */
89 if (base == 0x55aa55aa || base == 0x0) {
90 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
91 goto irq;
92 }
93
94 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
95 sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
96 if (!sdev->bar[IMR_BAR]) {
97 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
98 base, size);
99 return -ENODEV;
100 }
101 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
102
103 irq:
104 /* register our IRQ */
105 sdev->ipc_irq = pci->irq;
106 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
107 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
108 atom_irq_handler, atom_irq_thread,
109 0, "AudioDSP", sdev);
110 if (ret < 0) {
111 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
112 sdev->ipc_irq);
113 return ret;
114 }
115
116 /* enable BUSY and disable DONE Interrupt by default */
117 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
118 SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
119 SHIM_IMRX_DONE);
120
121 /* set default mailbox offset for FW ready message */
122 sdev->dsp_box.offset = MBOX_OFFSET;
123
124 return ret;
125 }
126
127 const struct snd_sof_dsp_ops sof_tng_ops = {
128 /* device init */
129 .probe = tangier_pci_probe,
130
131 /* DSP core boot / reset */
132 .run = atom_run,
133 .reset = atom_reset,
134
135 /* Register IO */
136 .write = sof_io_write,
137 .read = sof_io_read,
138 .write64 = sof_io_write64,
139 .read64 = sof_io_read64,
140
141 /* Block IO */
142 .block_read = sof_block_read,
143 .block_write = sof_block_write,
144
145 /* Mailbox IO */
146 .mailbox_read = sof_mailbox_read,
147 .mailbox_write = sof_mailbox_write,
148
149 /* doorbell */
150 .irq_handler = atom_irq_handler,
151 .irq_thread = atom_irq_thread,
152
153 /* ipc */
154 .send_msg = atom_send_msg,
155 .fw_ready = sof_fw_ready,
156 .get_mailbox_offset = atom_get_mailbox_offset,
157 .get_window_offset = atom_get_window_offset,
158
159 .ipc_msg_data = sof_ipc_msg_data,
160 .ipc_pcm_params = sof_ipc_pcm_params,
161
162 /* machine driver */
163 .machine_select = atom_machine_select,
164 .machine_register = sof_machine_register,
165 .machine_unregister = sof_machine_unregister,
166 .set_mach_params = atom_set_mach_params,
167
168 /* debug */
169 .debug_map = tng_debugfs,
170 .debug_map_count = ARRAY_SIZE(tng_debugfs),
171 .dbg_dump = atom_dump,
172 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
173
174 /* stream callbacks */
175 .pcm_open = sof_stream_pcm_open,
176 .pcm_close = sof_stream_pcm_close,
177
178 /* module loading */
179 .load_module = snd_sof_parse_module_memcpy,
180
181 /*Firmware loading */
182 .load_firmware = snd_sof_load_firmware_memcpy,
183
184 /* DAI drivers */
185 .drv = atom_dai,
186 .num_drv = 3, /* we have only 3 SSPs on byt*/
187
188 /* ALSA HW info flags */
189 .hw_info = SNDRV_PCM_INFO_MMAP |
190 SNDRV_PCM_INFO_MMAP_VALID |
191 SNDRV_PCM_INFO_INTERLEAVED |
192 SNDRV_PCM_INFO_PAUSE |
193 SNDRV_PCM_INFO_BATCH,
194
195 .dsp_arch_ops = &sof_xtensa_arch_ops,
196 };
197
198 const struct sof_intel_dsp_desc tng_chip_info = {
199 .cores_num = 1,
200 .host_managed_cores_mask = 1,
201 };
202
203 static const struct sof_dev_desc tng_desc = {
204 .machines = sof_tng_machines,
205 .resindex_lpe_base = 3, /* IRAM, but subtract IRAM offset */
206 .resindex_pcicfg_base = -1,
207 .resindex_imr_base = 0,
208 .irqindex_host_ipc = -1,
209 .chip_info = &tng_chip_info,
210 .default_fw_path = "intel/sof",
211 .default_tplg_path = "intel/sof-tplg",
212 .default_fw_filename = "sof-byt.ri",
213 .nocodec_tplg_filename = "sof-byt.tplg",
214 .ops = &sof_tng_ops,
215 };
216
217 /* PCI IDs */
218 static const struct pci_device_id sof_pci_ids[] = {
219 { PCI_DEVICE(0x8086, 0x119a),
220 .driver_data = (unsigned long)&tng_desc},
221 { 0, }
222 };
223 MODULE_DEVICE_TABLE(pci, sof_pci_ids);
224
225 /* pci_driver definition */
226 static struct pci_driver snd_sof_pci_intel_tng_driver = {
227 .name = "sof-audio-pci-intel-tng",
228 .id_table = sof_pci_ids,
229 .probe = sof_pci_probe,
230 .remove = sof_pci_remove,
231 .shutdown = sof_pci_shutdown,
232 .driver = {
233 .pm = &sof_pci_pm,
234 },
235 };
236 module_pci_driver(snd_sof_pci_intel_tng_driver);
237
238 MODULE_LICENSE("Dual BSD/GPL");
239 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
240 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
241 MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
242 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
243