1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 exceet electronics GmbH
4 * Copyright (c) 2018 Kontron Electronics GmbH
5 *
6 * Author: Frieder Schrempf <frieder.schrempf@kontron.de>
7 */
8
9 #ifndef __UBOOT__
10 #include <malloc.h>
11 #include <linux/device.h>
12 #include <linux/kernel.h>
13 #endif
14 #include <linux/bug.h>
15 #include <linux/mtd/spinand.h>
16
17 #define SPINAND_MFR_TOSHIBA 0x98
18 #define TOSH_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
19
20 static SPINAND_OP_VARIANTS(read_cache_variants,
21 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
22 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
23 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
24 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
25
26 static SPINAND_OP_VARIANTS(write_cache_x4_variants,
27 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
28 SPINAND_PROG_LOAD(true, 0, NULL, 0));
29
30 static SPINAND_OP_VARIANTS(update_cache_x4_variants,
31 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
32 SPINAND_PROG_LOAD(false, 0, NULL, 0));
33
34 /**
35 * Backward compatibility for 1st generation Serial NAND devices
36 * which don't support Quad Program Load operation.
37 */
38 static SPINAND_OP_VARIANTS(write_cache_variants,
39 SPINAND_PROG_LOAD(true, 0, NULL, 0));
40
41 static SPINAND_OP_VARIANTS(update_cache_variants,
42 SPINAND_PROG_LOAD(false, 0, NULL, 0));
43
tx58cxgxsxraix_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)44 static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section,
45 struct mtd_oob_region *region)
46 {
47 if (section > 0)
48 return -ERANGE;
49
50 region->offset = mtd->oobsize / 2;
51 region->length = mtd->oobsize / 2;
52
53 return 0;
54 }
55
tx58cxgxsxraix_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)56 static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section,
57 struct mtd_oob_region *region)
58 {
59 if (section > 0)
60 return -ERANGE;
61
62 /* 2 bytes reserved for BBM */
63 region->offset = 2;
64 region->length = (mtd->oobsize / 2) - 2;
65
66 return 0;
67 }
68
69 static const struct mtd_ooblayout_ops tx58cxgxsxraix_ooblayout = {
70 .ecc = tx58cxgxsxraix_ooblayout_ecc,
71 .rfree = tx58cxgxsxraix_ooblayout_free,
72 };
73
tx58cxgxsxraix_ecc_get_status(struct spinand_device * spinand,u8 status)74 static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
75 u8 status)
76 {
77 struct nand_device *nand = spinand_to_nand(spinand);
78 u8 mbf = 0;
79 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(0x30, &mbf);
80
81 switch (status & STATUS_ECC_MASK) {
82 case STATUS_ECC_NO_BITFLIPS:
83 return 0;
84
85 case STATUS_ECC_UNCOR_ERROR:
86 return -EBADMSG;
87
88 case STATUS_ECC_HAS_BITFLIPS:
89 case TOSH_STATUS_ECC_HAS_BITFLIPS_T:
90 /*
91 * Let's try to retrieve the real maximum number of bitflips
92 * in order to avoid forcing the wear-leveling layer to move
93 * data around if it's not necessary.
94 */
95 if (spi_mem_exec_op(spinand->slave, &op))
96 return nand->eccreq.strength;
97
98 mbf >>= 4;
99
100 if (WARN_ON(mbf > nand->eccreq.strength || !mbf))
101 return nand->eccreq.strength;
102
103 return mbf;
104
105 default:
106 break;
107 }
108
109 return -EINVAL;
110 }
111
112 static const struct spinand_info toshiba_spinand_table[] = {
113 /* 3.3V 1Gb (1st generation) */
114 SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2,
115 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
116 NAND_ECCREQ(8, 512),
117 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
118 &write_cache_variants,
119 &update_cache_variants),
120 0,
121 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
122 tx58cxgxsxraix_ecc_get_status)),
123 /* 3.3V 2Gb (1st generation) */
124 SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB,
125 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
126 NAND_ECCREQ(8, 512),
127 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
128 &write_cache_variants,
129 &update_cache_variants),
130 0,
131 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
132 tx58cxgxsxraix_ecc_get_status)),
133 /* 3.3V 4Gb (1st generation) */
134 SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD,
135 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
136 NAND_ECCREQ(8, 512),
137 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
138 &write_cache_variants,
139 &update_cache_variants),
140 0,
141 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
142 tx58cxgxsxraix_ecc_get_status)),
143 /* 1.8V 1Gb (1st generation) */
144 SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2,
145 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
146 NAND_ECCREQ(8, 512),
147 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
148 &write_cache_variants,
149 &update_cache_variants),
150 0,
151 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
152 tx58cxgxsxraix_ecc_get_status)),
153 /* 1.8V 2Gb (1st generation) */
154 SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB,
155 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
156 NAND_ECCREQ(8, 512),
157 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
158 &write_cache_variants,
159 &update_cache_variants),
160 0,
161 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
162 tx58cxgxsxraix_ecc_get_status)),
163 /* 1.8V 4Gb (1st generation) */
164 SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD,
165 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
166 NAND_ECCREQ(8, 512),
167 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
168 &write_cache_variants,
169 &update_cache_variants),
170 0,
171 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
172 tx58cxgxsxraix_ecc_get_status)),
173
174 /*
175 * 2nd generation serial nand has HOLD_D which is equivalent to
176 * QE_BIT.
177 */
178 /* 3.3V 1Gb (2nd generation) */
179 SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2,
180 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
181 NAND_ECCREQ(8, 512),
182 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
183 &write_cache_x4_variants,
184 &update_cache_x4_variants),
185 SPINAND_HAS_QE_BIT,
186 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
187 tx58cxgxsxraix_ecc_get_status)),
188 /* 3.3V 2Gb (2nd generation) */
189 SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB,
190 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
191 NAND_ECCREQ(8, 512),
192 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
193 &write_cache_x4_variants,
194 &update_cache_x4_variants),
195 SPINAND_HAS_QE_BIT,
196 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
197 tx58cxgxsxraix_ecc_get_status)),
198 /* 3.3V 4Gb (2nd generation) */
199 SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED,
200 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
201 NAND_ECCREQ(8, 512),
202 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
203 &write_cache_x4_variants,
204 &update_cache_x4_variants),
205 SPINAND_HAS_QE_BIT,
206 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
207 tx58cxgxsxraix_ecc_get_status)),
208 /* 3.3V 8Gb (2nd generation) */
209 SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4,
210 NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
211 NAND_ECCREQ(8, 512),
212 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
213 &write_cache_x4_variants,
214 &update_cache_x4_variants),
215 SPINAND_HAS_QE_BIT,
216 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
217 tx58cxgxsxraix_ecc_get_status)),
218 /* 1.8V 1Gb (2nd generation) */
219 SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2,
220 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
221 NAND_ECCREQ(8, 512),
222 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
223 &write_cache_x4_variants,
224 &update_cache_x4_variants),
225 SPINAND_HAS_QE_BIT,
226 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
227 tx58cxgxsxraix_ecc_get_status)),
228 /* 1.8V 2Gb (2nd generation) */
229 SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB,
230 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
231 NAND_ECCREQ(8, 512),
232 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
233 &write_cache_x4_variants,
234 &update_cache_x4_variants),
235 SPINAND_HAS_QE_BIT,
236 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
237 tx58cxgxsxraix_ecc_get_status)),
238 /* 1.8V 4Gb (2nd generation) */
239 SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD,
240 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
241 NAND_ECCREQ(8, 512),
242 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
243 &write_cache_x4_variants,
244 &update_cache_x4_variants),
245 SPINAND_HAS_QE_BIT,
246 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
247 tx58cxgxsxraix_ecc_get_status)),
248 /* 1.8V 8Gb (2nd generation) */
249 SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4,
250 NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
251 NAND_ECCREQ(8, 512),
252 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
253 &write_cache_x4_variants,
254 &update_cache_x4_variants),
255 SPINAND_HAS_QE_BIT,
256 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
257 tx58cxgxsxraix_ecc_get_status)),
258 };
259
toshiba_spinand_detect(struct spinand_device * spinand)260 static int toshiba_spinand_detect(struct spinand_device *spinand)
261 {
262 u8 *id = spinand->id.data;
263 int ret;
264
265 /*
266 * Toshiba SPI NAND read ID needs a dummy byte,
267 * so the first byte in id is garbage.
268 */
269 if (id[1] != SPINAND_MFR_TOSHIBA)
270 return 0;
271
272 ret = spinand_match_and_init(spinand, toshiba_spinand_table,
273 ARRAY_SIZE(toshiba_spinand_table),
274 id[2]);
275 if (ret)
276 return ret;
277
278 return 1;
279 }
280
281 static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
282 .detect = toshiba_spinand_detect,
283 };
284
285 const struct spinand_manufacturer toshiba_spinand_manufacturer = {
286 .id = SPINAND_MFR_TOSHIBA,
287 .name = "Toshiba",
288 .ops = &toshiba_spinand_manuf_ops,
289 };
290