1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include "umc_v6_7.h"
24 #include "amdgpu_ras.h"
25 #include "amdgpu_umc.h"
26 #include "amdgpu.h"
27 
28 #include "umc/umc_6_7_0_offset.h"
29 #include "umc/umc_6_7_0_sh_mask.h"
30 
31 const uint32_t
32 	umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
33 		{28, 20, 24, 16, 12, 4, 8, 0},
34 		{6, 30, 2, 26, 22, 14, 18, 10},
35 		{19, 11, 15, 7, 3, 27, 31, 23},
36 		{9, 1, 5, 29, 25, 17, 21, 13}
37 };
38 const uint32_t
39 	umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
40 		{19, 11, 15, 7,	3, 27, 31, 23},
41 		{9, 1, 5, 29, 25, 17, 21, 13},
42 		{28, 20, 24, 16, 12, 4, 8, 0},
43 		{6, 30, 2, 26, 22, 14, 18, 10},
44 };
45 
get_umc_v6_7_reg_offset(struct amdgpu_device * adev,uint32_t umc_inst,uint32_t ch_inst)46 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,
47 					      uint32_t umc_inst,
48 					      uint32_t ch_inst)
49 {
50 	return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst;
51 }
52 
umc_v6_7_query_correctable_error_count(struct amdgpu_device * adev,uint32_t umc_reg_offset,unsigned long * error_count)53 static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev,
54 						   uint32_t umc_reg_offset,
55 						   unsigned long *error_count)
56 {
57 	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
58 	uint32_t ecc_err_cnt, ecc_err_cnt_addr;
59 	uint64_t mc_umc_status;
60 	uint32_t mc_umc_status_addr;
61 
62 	/* UMC 6_1_1 registers */
63 	ecc_err_cnt_sel_addr =
64 		SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel);
65 	ecc_err_cnt_addr =
66 		SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt);
67 	mc_umc_status_addr =
68 		SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
69 
70 	/* select the lower chip and check the error count */
71 	ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
72 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
73 					EccErrCntCsSel, 0);
74 	WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel);
75 
76 	ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
77 	*error_count +=
78 		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
79 		 UMC_V6_7_CE_CNT_INIT);
80 
81 	/* select the higher chip and check the err counter */
82 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
83 					EccErrCntCsSel, 1);
84 	WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel);
85 
86 	ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
87 	*error_count +=
88 		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
89 		 UMC_V6_7_CE_CNT_INIT);
90 
91 	/* check for SRAM correctable error
92 	  MCUMC_STATUS is a 64 bit register */
93 	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
94 	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
95 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
96 		*error_count += 1;
97 }
98 
umc_v6_7_querry_uncorrectable_error_count(struct amdgpu_device * adev,uint32_t umc_reg_offset,unsigned long * error_count)99 static void umc_v6_7_querry_uncorrectable_error_count(struct amdgpu_device *adev,
100 						      uint32_t umc_reg_offset,
101 						      unsigned long *error_count)
102 {
103 	uint64_t mc_umc_status;
104 	uint32_t mc_umc_status_addr;
105 
106 	mc_umc_status_addr =
107 		SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
108 
109 	/* check the MCUMC_STATUS */
110 	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
111 	if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
112 	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
113 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
114 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
115 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
116 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
117 		*error_count += 1;
118 }
119 
umc_v6_7_reset_error_count_per_channel(struct amdgpu_device * adev,uint32_t umc_reg_offset)120 static void umc_v6_7_reset_error_count_per_channel(struct amdgpu_device *adev,
121 						   uint32_t umc_reg_offset)
122 {
123 	uint32_t ecc_err_cnt_addr;
124 	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
125 
126 	ecc_err_cnt_sel_addr =
127 		SOC15_REG_OFFSET(UMC, 0,
128 				regUMCCH0_0_EccErrCntSel);
129 	ecc_err_cnt_addr =
130 		SOC15_REG_OFFSET(UMC, 0,
131 				regUMCCH0_0_EccErrCnt);
132 
133 	/* select the lower chip */
134 	ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
135 				       umc_reg_offset) * 4);
136 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,
137 					UMCCH0_0_EccErrCntSel,
138 					EccErrCntCsSel, 0);
139 	WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4,
140 			ecc_err_cnt_sel);
141 
142 	/* clear lower chip error count */
143 	WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4,
144 			UMC_V6_7_CE_CNT_INIT);
145 
146 	/* select the higher chip */
147 	ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
148 					umc_reg_offset) * 4);
149 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,
150 					UMCCH0_0_EccErrCntSel,
151 					EccErrCntCsSel, 1);
152 	WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4,
153 			ecc_err_cnt_sel);
154 
155 	/* clear higher chip error count */
156 	WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4,
157 			UMC_V6_7_CE_CNT_INIT);
158 }
159 
umc_v6_7_reset_error_count(struct amdgpu_device * adev)160 static void umc_v6_7_reset_error_count(struct amdgpu_device *adev)
161 {
162 	uint32_t umc_inst        = 0;
163 	uint32_t ch_inst         = 0;
164 	uint32_t umc_reg_offset  = 0;
165 
166 	LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
167 		umc_reg_offset = get_umc_v6_7_reg_offset(adev,
168 							 umc_inst,
169 							 ch_inst);
170 
171 		umc_v6_7_reset_error_count_per_channel(adev,
172 						       umc_reg_offset);
173 	}
174 }
175 
umc_v6_7_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)176 static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev,
177 					   void *ras_error_status)
178 {
179 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
180 
181 	uint32_t umc_inst        = 0;
182 	uint32_t ch_inst         = 0;
183 	uint32_t umc_reg_offset  = 0;
184 
185 	/*TODO: driver needs to toggle DF Cstate to ensure
186 	 * safe access of UMC registers. Will add the protection */
187 	LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
188 		umc_reg_offset = get_umc_v6_7_reg_offset(adev,
189 							 umc_inst,
190 							 ch_inst);
191 		umc_v6_7_query_correctable_error_count(adev,
192 						       umc_reg_offset,
193 						       &(err_data->ce_count));
194 		umc_v6_7_querry_uncorrectable_error_count(adev,
195 							  umc_reg_offset,
196 							  &(err_data->ue_count));
197 	}
198 
199 	umc_v6_7_reset_error_count(adev);
200 }
201 
umc_v6_7_query_error_address(struct amdgpu_device * adev,struct ras_err_data * err_data,uint32_t umc_reg_offset,uint32_t ch_inst,uint32_t umc_inst)202 static void umc_v6_7_query_error_address(struct amdgpu_device *adev,
203 					 struct ras_err_data *err_data,
204 					 uint32_t umc_reg_offset,
205 					 uint32_t ch_inst,
206 					 uint32_t umc_inst)
207 {
208 	uint32_t mc_umc_status_addr;
209 	uint64_t mc_umc_status, err_addr, retired_page, mc_umc_addrt0;
210 	struct eeprom_table_record *err_rec;
211 	uint32_t channel_index;
212 
213 	mc_umc_status_addr =
214 		SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
215 	mc_umc_addrt0 =
216 		SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
217 
218 	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
219 
220 	if (mc_umc_status == 0)
221 		return;
222 
223 	if (!err_data->err_addr) {
224 		/* clear umc status */
225 		WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
226 		return;
227 	}
228 
229 	err_rec = &err_data->err_addr[err_data->err_addr_cnt];
230 
231 	channel_index =
232 		adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
233 
234 	/* calculate error address if ue/ce error is detected */
235 	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
236 	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
237 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
238 
239 		err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
240 		err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
241 
242 		/* translate umc channel address to soc pa, 3 parts are included */
243 		retired_page = ADDR_OF_8KB_BLOCK(err_addr) |
244 				ADDR_OF_256B_BLOCK(channel_index) |
245 				OFFSET_IN_256B_BLOCK(err_addr);
246 
247 		/* we only save ue error information currently, ce is skipped */
248 		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
249 				== 1) {
250 			err_rec->address = err_addr;
251 			/* page frame address is saved */
252 			err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
253 			err_rec->ts = (uint64_t)ktime_get_real_seconds();
254 			err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
255 			err_rec->cu = 0;
256 			err_rec->mem_channel = channel_index;
257 			err_rec->mcumc_id = umc_inst;
258 
259 			err_data->err_addr_cnt++;
260 		}
261 	}
262 
263 	/* clear umc status */
264 	WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
265 }
266 
umc_v6_7_query_ras_error_address(struct amdgpu_device * adev,void * ras_error_status)267 static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev,
268 					     void *ras_error_status)
269 {
270 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
271 
272 	uint32_t umc_inst        = 0;
273 	uint32_t ch_inst         = 0;
274 	uint32_t umc_reg_offset  = 0;
275 
276 	/*TODO: driver needs to toggle DF Cstate to ensure
277 	 * safe access of UMC resgisters. Will add the protection
278 	 * when firmware interface is ready */
279 	LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
280 		umc_reg_offset = get_umc_v6_7_reg_offset(adev,
281 							 umc_inst,
282 							 ch_inst);
283 		umc_v6_7_query_error_address(adev,
284 					     err_data,
285 					     umc_reg_offset,
286 					     ch_inst,
287 					     umc_inst);
288 	}
289 }
290 
umc_v6_7_query_ras_poison_mode_per_channel(struct amdgpu_device * adev,uint32_t umc_reg_offset)291 static uint32_t umc_v6_7_query_ras_poison_mode_per_channel(
292 						struct amdgpu_device *adev,
293 						uint32_t umc_reg_offset)
294 {
295 	uint32_t ecc_ctrl_addr, ecc_ctrl;
296 
297 	ecc_ctrl_addr =
298 		SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccCtrl);
299 	ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr +
300 					umc_reg_offset) * 4);
301 
302 	return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_EccCtrl, UCFatalEn);
303 }
304 
umc_v6_7_query_ras_poison_mode(struct amdgpu_device * adev)305 static bool umc_v6_7_query_ras_poison_mode(struct amdgpu_device *adev)
306 {
307 	uint32_t umc_inst        = 0;
308 	uint32_t ch_inst         = 0;
309 	uint32_t umc_reg_offset  = 0;
310 
311 	LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
312 		umc_reg_offset = get_umc_v6_7_reg_offset(adev,
313 							umc_inst,
314 							ch_inst);
315 		/* Enabling fatal error in one channel will be considered
316 		   as fatal error mode */
317 		if (umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset))
318 			return false;
319 	}
320 
321 	return true;
322 }
323 
324 const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs = {
325 	.ras_late_init = amdgpu_umc_ras_late_init,
326 	.ras_fini = amdgpu_umc_ras_fini,
327 	.query_ras_error_count = umc_v6_7_query_ras_error_count,
328 	.query_ras_error_address = umc_v6_7_query_ras_error_address,
329 	.query_ras_poison_mode = umc_v6_7_query_ras_poison_mode,
330 };
331