1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef __INTEL_UNCORE_H__
26 #define __INTEL_UNCORE_H__
27
28 #include <linux/spinlock.h>
29 #include <linux/notifier.h>
30 #include <linux/hrtimer.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32
33 #include "i915_reg.h"
34
35 struct drm_i915_private;
36 struct intel_runtime_pm;
37 struct intel_uncore;
38 struct intel_gt;
39
40 struct intel_uncore_mmio_debug {
41 spinlock_t lock; /** lock is also taken in irq contexts. */
42 int unclaimed_mmio_check;
43 int saved_mmio_check;
44 u32 suspend_count;
45 };
46
47 enum forcewake_domain_id {
48 FW_DOMAIN_ID_RENDER = 0,
49 FW_DOMAIN_ID_GT, /* also includes blitter engine */
50 FW_DOMAIN_ID_MEDIA,
51 FW_DOMAIN_ID_MEDIA_VDBOX0,
52 FW_DOMAIN_ID_MEDIA_VDBOX1,
53 FW_DOMAIN_ID_MEDIA_VDBOX2,
54 FW_DOMAIN_ID_MEDIA_VDBOX3,
55 FW_DOMAIN_ID_MEDIA_VDBOX4,
56 FW_DOMAIN_ID_MEDIA_VDBOX5,
57 FW_DOMAIN_ID_MEDIA_VDBOX6,
58 FW_DOMAIN_ID_MEDIA_VDBOX7,
59 FW_DOMAIN_ID_MEDIA_VEBOX0,
60 FW_DOMAIN_ID_MEDIA_VEBOX1,
61 FW_DOMAIN_ID_MEDIA_VEBOX2,
62 FW_DOMAIN_ID_MEDIA_VEBOX3,
63
64 FW_DOMAIN_ID_COUNT
65 };
66
67 enum forcewake_domains {
68 FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
69 FORCEWAKE_GT = BIT(FW_DOMAIN_ID_GT),
70 FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
71 FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
72 FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
73 FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
74 FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
75 FORCEWAKE_MEDIA_VDBOX4 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX4),
76 FORCEWAKE_MEDIA_VDBOX5 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX5),
77 FORCEWAKE_MEDIA_VDBOX6 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX6),
78 FORCEWAKE_MEDIA_VDBOX7 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX7),
79 FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
80 FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
81 FORCEWAKE_MEDIA_VEBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX2),
82 FORCEWAKE_MEDIA_VEBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX3),
83
84 FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1,
85 };
86
87 struct intel_uncore_fw_get {
88 void (*force_wake_get)(struct intel_uncore *uncore,
89 enum forcewake_domains domains);
90 };
91
92 struct intel_uncore_funcs {
93 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
94 i915_reg_t r);
95 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
96 i915_reg_t r);
97
98 u8 (*mmio_readb)(struct intel_uncore *uncore,
99 i915_reg_t r, bool trace);
100 u16 (*mmio_readw)(struct intel_uncore *uncore,
101 i915_reg_t r, bool trace);
102 u32 (*mmio_readl)(struct intel_uncore *uncore,
103 i915_reg_t r, bool trace);
104 u64 (*mmio_readq)(struct intel_uncore *uncore,
105 i915_reg_t r, bool trace);
106
107 void (*mmio_writeb)(struct intel_uncore *uncore,
108 i915_reg_t r, u8 val, bool trace);
109 void (*mmio_writew)(struct intel_uncore *uncore,
110 i915_reg_t r, u16 val, bool trace);
111 void (*mmio_writel)(struct intel_uncore *uncore,
112 i915_reg_t r, u32 val, bool trace);
113 };
114
115 struct intel_forcewake_range {
116 u32 start;
117 u32 end;
118
119 enum forcewake_domains domains;
120 };
121
122 /* Other register ranges (e.g., shadow tables, MCR tables, etc.) */
123 struct i915_range {
124 u32 start;
125 u32 end;
126 };
127
128 struct intel_uncore {
129 void __iomem *regs;
130
131 struct drm_i915_private *i915;
132 struct intel_runtime_pm *rpm;
133
134 spinlock_t lock; /** lock is also taken in irq contexts. */
135
136 unsigned int flags;
137 #define UNCORE_HAS_FORCEWAKE BIT(0)
138 #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
139 #define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
140 #define UNCORE_HAS_FIFO BIT(3)
141
142 const struct intel_forcewake_range *fw_domains_table;
143 unsigned int fw_domains_table_entries;
144
145 /*
146 * Shadowed registers are special cases where we can safely write
147 * to the register *without* grabbing forcewake.
148 */
149 const struct i915_range *shadowed_reg_table;
150 unsigned int shadowed_reg_table_entries;
151
152 struct notifier_block pmic_bus_access_nb;
153 const struct intel_uncore_fw_get *fw_get_funcs;
154 struct intel_uncore_funcs funcs;
155
156 unsigned int fifo_count;
157
158 enum forcewake_domains fw_domains;
159 enum forcewake_domains fw_domains_active;
160 enum forcewake_domains fw_domains_timer;
161 enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
162
163 struct intel_uncore_forcewake_domain {
164 struct intel_uncore *uncore;
165 enum forcewake_domain_id id;
166 enum forcewake_domains mask;
167 unsigned int wake_count;
168 bool active;
169 struct hrtimer timer;
170 u32 __iomem *reg_set;
171 u32 __iomem *reg_ack;
172 } *fw_domain[FW_DOMAIN_ID_COUNT];
173
174 unsigned int user_forcewake_count;
175
176 struct intel_uncore_mmio_debug *debug;
177 };
178
179 /* Iterate over initialised fw domains */
180 #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
181 for (tmp__ = (mask__); tmp__ ;) \
182 for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)])
183
184 #define for_each_fw_domain(domain__, uncore__, tmp__) \
185 for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
186
187 static inline bool
intel_uncore_has_forcewake(const struct intel_uncore * uncore)188 intel_uncore_has_forcewake(const struct intel_uncore *uncore)
189 {
190 return uncore->flags & UNCORE_HAS_FORCEWAKE;
191 }
192
193 static inline bool
intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore * uncore)194 intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
195 {
196 return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
197 }
198
199 static inline bool
intel_uncore_has_dbg_unclaimed(const struct intel_uncore * uncore)200 intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
201 {
202 return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
203 }
204
205 static inline bool
intel_uncore_has_fifo(const struct intel_uncore * uncore)206 intel_uncore_has_fifo(const struct intel_uncore *uncore)
207 {
208 return uncore->flags & UNCORE_HAS_FIFO;
209 }
210
211 u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
212 i915_reg_t reg,
213 int slice, int subslice);
214 u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
215 i915_reg_t reg, int slice, int subslice);
216
217 void
218 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
219 void intel_uncore_init_early(struct intel_uncore *uncore,
220 struct drm_i915_private *i915);
221 int intel_uncore_init_mmio(struct intel_uncore *uncore);
222 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
223 struct intel_gt *gt);
224 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
225 bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
226 void intel_uncore_fini_mmio(struct intel_uncore *uncore);
227 void intel_uncore_suspend(struct intel_uncore *uncore);
228 void intel_uncore_resume_early(struct intel_uncore *uncore);
229 void intel_uncore_runtime_resume(struct intel_uncore *uncore);
230
231 void assert_forcewakes_inactive(struct intel_uncore *uncore);
232 void assert_forcewakes_active(struct intel_uncore *uncore,
233 enum forcewake_domains fw_domains);
234 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
235
236 enum forcewake_domains
237 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
238 i915_reg_t reg, unsigned int op);
239 #define FW_REG_READ (1)
240 #define FW_REG_WRITE (2)
241
242 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
243 enum forcewake_domains domains);
244 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
245 enum forcewake_domains domains);
246 void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
247 enum forcewake_domains fw_domains);
248
249 /*
250 * Like above but the caller must manage the uncore.lock itself.
251 * Must be used with intel_uncore_read_fw() and friends.
252 */
253 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
254 enum forcewake_domains domains);
255 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
256 enum forcewake_domains domains);
257
258 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
259 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
260
261 int __intel_wait_for_register(struct intel_uncore *uncore,
262 i915_reg_t reg,
263 u32 mask,
264 u32 value,
265 unsigned int fast_timeout_us,
266 unsigned int slow_timeout_ms,
267 u32 *out_value);
268 static inline int
intel_wait_for_register(struct intel_uncore * uncore,i915_reg_t reg,u32 mask,u32 value,unsigned int timeout_ms)269 intel_wait_for_register(struct intel_uncore *uncore,
270 i915_reg_t reg,
271 u32 mask,
272 u32 value,
273 unsigned int timeout_ms)
274 {
275 return __intel_wait_for_register(uncore, reg, mask, value, 2,
276 timeout_ms, NULL);
277 }
278
279 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
280 i915_reg_t reg,
281 u32 mask,
282 u32 value,
283 unsigned int fast_timeout_us,
284 unsigned int slow_timeout_ms,
285 u32 *out_value);
286 static inline int
intel_wait_for_register_fw(struct intel_uncore * uncore,i915_reg_t reg,u32 mask,u32 value,unsigned int timeout_ms)287 intel_wait_for_register_fw(struct intel_uncore *uncore,
288 i915_reg_t reg,
289 u32 mask,
290 u32 value,
291 unsigned int timeout_ms)
292 {
293 return __intel_wait_for_register_fw(uncore, reg, mask, value,
294 2, timeout_ms, NULL);
295 }
296
297 /* register access functions */
298 #define __raw_read(x__, s__) \
299 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
300 i915_reg_t reg) \
301 { \
302 return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
303 }
304
305 #define __raw_write(x__, s__) \
306 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
307 i915_reg_t reg, u##x__ val) \
308 { \
309 write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
310 }
311 __raw_read(8, b)
312 __raw_read(16, w)
313 __raw_read(32, l)
314 __raw_read(64, q)
315
316 __raw_write(8, b)
317 __raw_write(16, w)
318 __raw_write(32, l)
319 __raw_write(64, q)
320
321 #undef __raw_read
322 #undef __raw_write
323
324 #define __uncore_read(name__, x__, s__, trace__) \
325 static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
326 i915_reg_t reg) \
327 { \
328 return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
329 }
330
331 #define __uncore_write(name__, x__, s__, trace__) \
332 static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
333 i915_reg_t reg, u##x__ val) \
334 { \
335 uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
336 }
337
338 __uncore_read(read8, 8, b, true)
339 __uncore_read(read16, 16, w, true)
340 __uncore_read(read, 32, l, true)
341 __uncore_read(read16_notrace, 16, w, false)
342 __uncore_read(read_notrace, 32, l, false)
343
344 __uncore_write(write8, 8, b, true)
345 __uncore_write(write16, 16, w, true)
346 __uncore_write(write, 32, l, true)
347 __uncore_write(write_notrace, 32, l, false)
348
349 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
350 * will be implemented using 2 32-bit writes in an arbitrary order with
351 * an arbitrary delay between them. This can cause the hardware to
352 * act upon the intermediate value, possibly leading to corruption and
353 * machine death. For this reason we do not support intel_uncore_write64,
354 * or uncore->funcs.mmio_writeq.
355 *
356 * When reading a 64-bit value as two 32-bit values, the delay may cause
357 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
358 * occasionally a 64-bit register does not actually support a full readq
359 * and must be read using two 32-bit reads.
360 *
361 * You have been warned.
362 */
363 __uncore_read(read64, 64, q, true)
364
365 static inline u64
intel_uncore_read64_2x32(struct intel_uncore * uncore,i915_reg_t lower_reg,i915_reg_t upper_reg)366 intel_uncore_read64_2x32(struct intel_uncore *uncore,
367 i915_reg_t lower_reg, i915_reg_t upper_reg)
368 {
369 u32 upper, lower, old_upper, loop = 0;
370 upper = intel_uncore_read(uncore, upper_reg);
371 do {
372 old_upper = upper;
373 lower = intel_uncore_read(uncore, lower_reg);
374 upper = intel_uncore_read(uncore, upper_reg);
375 } while (upper != old_upper && loop++ < 2);
376 return (u64)upper << 32 | lower;
377 }
378
379 #define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
380 #define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
381
382 #undef __uncore_read
383 #undef __uncore_write
384
385 /* These are untraced mmio-accessors that are only valid to be used inside
386 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
387 * controlled.
388 *
389 * Think twice, and think again, before using these.
390 *
391 * As an example, these accessors can possibly be used between:
392 *
393 * spin_lock_irq(&uncore->lock);
394 * intel_uncore_forcewake_get__locked();
395 *
396 * and
397 *
398 * intel_uncore_forcewake_put__locked();
399 * spin_unlock_irq(&uncore->lock);
400 *
401 *
402 * Note: some registers may not need forcewake held, so
403 * intel_uncore_forcewake_{get,put} can be omitted, see
404 * intel_uncore_forcewake_for_reg().
405 *
406 * Certain architectures will die if the same cacheline is concurrently accessed
407 * by different clients (e.g. on Ivybridge). Access to registers should
408 * therefore generally be serialised, by either the dev_priv->uncore.lock or
409 * a more localised lock guarding all access to that bank of registers.
410 */
411 #define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
412 #define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
413 #define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
414 #define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
415
intel_uncore_rmw(struct intel_uncore * uncore,i915_reg_t reg,u32 clear,u32 set)416 static inline void intel_uncore_rmw(struct intel_uncore *uncore,
417 i915_reg_t reg, u32 clear, u32 set)
418 {
419 u32 old, val;
420
421 old = intel_uncore_read(uncore, reg);
422 val = (old & ~clear) | set;
423 if (val != old)
424 intel_uncore_write(uncore, reg, val);
425 }
426
intel_uncore_rmw_fw(struct intel_uncore * uncore,i915_reg_t reg,u32 clear,u32 set)427 static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
428 i915_reg_t reg, u32 clear, u32 set)
429 {
430 u32 old, val;
431
432 old = intel_uncore_read_fw(uncore, reg);
433 val = (old & ~clear) | set;
434 if (val != old)
435 intel_uncore_write_fw(uncore, reg, val);
436 }
437
intel_uncore_write_and_verify(struct intel_uncore * uncore,i915_reg_t reg,u32 val,u32 mask,u32 expected_val)438 static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
439 i915_reg_t reg, u32 val,
440 u32 mask, u32 expected_val)
441 {
442 u32 reg_val;
443
444 intel_uncore_write(uncore, reg, val);
445 reg_val = intel_uncore_read(uncore, reg);
446
447 return (reg_val & mask) != expected_val ? -EINVAL : 0;
448 }
449
450 #define raw_reg_read(base, reg) \
451 readl(base + i915_mmio_reg_offset(reg))
452 #define raw_reg_write(base, reg, value) \
453 writel(value, base + i915_mmio_reg_offset(reg))
454
455 #endif /* !__INTEL_UNCORE_H__ */
456