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Searched defs:val (Results 1 – 25 of 123) sorted by relevance

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/optee_os/core/drivers/crypto/caam/hal/common/registers/
A Drng_regs.h28 #define TRNG_SDCTL_ENT_DLY(val) SHIFT_U32(((val) & 0xFFFF), 16) argument
29 #define TRNG_SDCTL_SAMP_SIZE(val) ((val) & 0xFFFF) argument
42 #define TRNG_RTSCMISC_RTY_CNT(val) SHIFT_U32(((val) & (0xF)), 16) argument
44 #define TRNG_RTSCMISC_LRUN_MAX(val) SHIFT_U32(((val) & (0xFF)), 0) argument
49 #define TRNG_RTPKRRNG_PKR_RNG(val) SHIFT_U32(((val) & (0xFFFF)), 0) argument
59 #define TRNG_RTSCML_MONO_RNG(val) SHIFT_U32(((val) & (0xFFFF)), 16) argument
61 #define TRNG_RTSCML_MONO_MAX(val) SHIFT_U32(((val) & (0xFFFF)), 0) argument
68 #define TRNG_RTSCR1L_RUN1_MAX(val) SHIFT_U32(((val) & (0x7FFF)), 0) argument
75 #define TRNG_RTSCR2L_RUN2_MAX(val) SHIFT_U32(((val) & (0x3FFF)), 0) argument
89 #define TRNG_RTSCR4L_RUN4_MAX(val) SHIFT_U32(((val) & (0xFFF)), 0) argument
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A Dversion_regs.h15 #define GET_CTPR_MS_RNG_I(val) (((val) & BM_CTPR_MS_RNG_I) >> 8) argument
19 #define GET_CTPR_LS_SPLIT_KEY(val) (((val) & BM_CTPR_LS_SPLIT_KEY) >> 14) argument
24 #define GET_SMVID_MS_MAX_NPAG(val) (((val) & BM_SMVID_MS_MAX_NPAG) >> 16) argument
26 #define GET_SMVID_MS_NPRT(val) (((val) & BM_SMVID_MS_NPRT) >> 12) argument
30 #define GET_SMVID_LS_PSIZ(val) (((val) & BM_SMVID_LS_PSIZ) >> 16) argument
52 #define GET_CHANUM_LS_PKNUM(val) (((val) & BM_CHANUM_LS_PKNUM) >> 28) argument
54 #define GET_CHANUM_LS_MDNUM(val) (((val) & BM_CHANUM_LS_MDNUM) >> 12) argument
59 #define GET_PKHA_VERSION_PKNUM(val) ((val) & BM_PKHA_VERSION_PKNUM) argument
64 #define GET_MDHA_VERSION_MDNUM(val) ((val) & BM_MDHA_VERSION_MDNUM) argument
72 #define GET_RNG_VERSION_VID(val) ((val) & BM_RNG_VERSION_VID) argument
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/optee_os/core/drivers/crypto/caam/hal/common/
A Dhal_ctrl.c19 uint32_t val = io_caam_read32(baseaddr + CCBVID); in caam_hal_ctrl_era() local
26 uint32_t val = 0; in caam_hal_ctrl_jrnum() local
42 uint32_t val = 0; in caam_hal_ctrl_hash_limit() local
76 uint32_t val = io_caam_read32(baseaddr + CTPR_LS); in caam_hal_ctrl_splitkey_support() local
83 uint32_t val = 0; in caam_hal_ctrl_pknum() local
101 uint32_t val = 0; in caam_hal_ctrl_inc_priblob() local
A Dhal_jr.c158 uint32_t val = 0; in caam_hal_jr_check_ack_itr() local
174 uint32_t val = 0; in caam_hal_jr_halt() local
204 uint32_t val = 0; in caam_hal_jr_flush() local
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/registers/
A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) argument
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) argument
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) argument
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) argument
38 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0xF, 0) argument
41 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0xF, 16) argument
43 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0xF, 0) argument
/optee_os/core/arch/arm/plat-imx/pm/
A Dgpcv2.c21 uint32_t val = io_read32(gpc_base() + offset) & (~GPC_PGC_PCG_MASK); in imx_gpcv2_set_core_pgc() local
31 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ); in imx_gpcv2_set_core1_pdn_by_software() local
48 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ); in imx_gpcv2_set_core1_pup_by_software() local
/optee_os/core/include/
A Dio.h23 static inline void io_write8(vaddr_t addr, uint8_t val) in io_write8()
28 static inline void io_write16(vaddr_t addr, uint16_t val) in io_write16()
33 static inline void io_write32(vaddr_t addr, uint32_t val) in io_write32()
53 static inline void io_mask8(vaddr_t addr, uint8_t val, uint8_t mask) in io_mask8()
58 static inline void io_mask16(vaddr_t addr, uint16_t val, uint16_t mask) in io_mask16()
63 static inline void io_mask32(vaddr_t addr, uint32_t val, uint32_t mask) in io_mask32()
73 static inline void put_be64(void *p, uint64_t val) in put_be64()
83 static inline void put_be32(void *p, uint32_t val) in put_be32()
93 static inline void put_be16(void *p, uint16_t val) in put_be16()
98 static inline void put_le32(const void *p, uint32_t val) in put_le32()
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A Dgen-asm-defines.h9 #define DEFINE(def, val) \ argument
/optee_os/core/drivers/crypto/caam/hal/ls/registers/
A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) argument
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) argument
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) argument
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) argument
/optee_os/out/arm/export-ta_arm32/include/
A Datomic.h46 static inline void atomic_store_int(int *p, int val) in atomic_store_int()
51 static inline void atomic_store_short(short int *p, short int val) in atomic_store_short()
56 static inline void atomic_store_uint(unsigned int *p, unsigned int val) in atomic_store_uint()
61 static inline void atomic_store_u32(uint32_t *p, uint32_t val) in atomic_store_u32()
/optee_os/out/arm/export-ta_arm64/include/
A Datomic.h46 static inline void atomic_store_int(int *p, int val) in atomic_store_int()
51 static inline void atomic_store_short(short int *p, short int val) in atomic_store_short()
56 static inline void atomic_store_uint(unsigned int *p, unsigned int val) in atomic_store_uint()
61 static inline void atomic_store_u32(uint32_t *p, uint32_t val) in atomic_store_u32()
/optee_os/lib/libutils/ext/include/
A Datomic.h46 static inline void atomic_store_int(int *p, int val) in atomic_store_int()
51 static inline void atomic_store_short(short int *p, short int val) in atomic_store_short()
56 static inline void atomic_store_uint(unsigned int *p, unsigned int val) in atomic_store_uint()
61 static inline void atomic_store_u32(uint32_t *p, uint32_t val) in atomic_store_u32()
/optee_os/core/drivers/
A Dimx_snvs.c19 uint32_t val = 0; in snvs_get_security_cfg() local
39 uint32_t val = 0; in snvs_get_ssm_mode() local
A Dtzc400.c92 static void tzc_write_gate_keeper(vaddr_t base, uint32_t val) in tzc_write_gate_keeper()
108 uint32_t val) in tzc_write_region_base_low()
119 uint32_t val) in tzc_write_region_base_high()
130 uint32_t val) in tzc_write_region_top_low()
141 uint32_t val) in tzc_write_region_top_high()
152 uint32_t val) in tzc_write_region_attributes()
163 uint32_t val) in tzc_write_region_id_access()
191 static void tzc_set_gate_keeper(vaddr_t base, uint8_t filter, uint32_t val) in tzc_set_gate_keeper()
A Dtzc380.c71 uint32_t val) in tzc_write_region_base_low()
77 uint32_t val) in tzc_write_region_base_high()
88 uint32_t val) in tzc_write_region_attributes()
128 uint32_t val; in tzc_region_enable() local
300 uint32_t val = 0; in tzc_regions_lockdown() local
/optee_os/core/include/kernel/
A Drefcount.h51 unsigned int val; member
59 static inline void refcount_set(struct refcount *r, unsigned int val) in refcount_set()
/optee_os/core/arch/arm/plat-marvell/armada3700/
A Dhal_sec_perf.c70 #define TZ_SET_PERM(data, val) \ argument
77 #define TZ_SET_RZ_EN(data, val) \ argument
85 #define TZ_SET_AREA_LEN_CODE(data, val) \ argument
94 #define TZ_SET_START_ADDR_L(data, val) \ argument
100 #define TZ_GET_UR_PERM(data, val) ((ret) = (((data) & (0x3 << 4)) >> 4)) argument
101 #define TZ_SET_UR_PERM(data, val) \ argument
107 #define TZ_GET_UR_RZ_EN(data, val) \ argument
110 #define TZ_SET_UR_RZ_EN(data, val) \ argument
/optee_os/core/lib/libfdt/
A Dfdt_addresses.c17 uint32_t val; in fdt_cells() local
36 int val; in fdt_address_cells() local
48 int val; in fdt_size_cells() local
/optee_os/core/arch/arm/plat-marvell/armada7k8k/
A Dhal_sec_perf.c69 #define TZ_SET_PERM(data, val) \ argument
76 #define TZ_SET_RZ_EN(data, val) \ argument
84 #define TZ_SET_AREA_LEN_CODE(data, val) \ argument
93 #define TZ_SET_START_ADDR_L(data, val) \ argument
99 #define TZ_GET_UR_PERM(data, val) ((ret) = (((data) & (0x3 << 4)) >> 4)) argument
100 #define TZ_SET_UR_PERM(data, val) \ argument
106 #define TZ_GET_UR_RZ_EN(data, val) \ argument
109 #define TZ_SET_UR_RZ_EN(data, val) \ argument
/optee_os/core/lib/libfdt/include/
A Dlibfdt.h1285 const char *name, uint32_t val) in fdt_setprop_inplace_u32()
1320 const char *name, uint64_t val) in fdt_setprop_inplace_u64()
1332 const char *name, uint32_t val) in fdt_setprop_inplace_cell()
1435 static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) in fdt_property_u32()
1440 static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) in fdt_property_u64()
1646 uint32_t val) in fdt_setprop_u32()
1681 uint64_t val) in fdt_setprop_u64()
1693 uint32_t val) in fdt_setprop_cell()
1818 const char *name, uint32_t val) in fdt_appendprop_u32()
1853 const char *name, uint64_t val) in fdt_appendprop_u64()
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/optee_os/core/arch/arm/plat-zynq7k/
A Dmain.c134 uint32_t val; in arm_cl2_enable() local
175 static uint32_t write_slcr(uint32_t addr, uint32_t val) in write_slcr()
196 static uint32_t read_slcr(uint32_t addr, uint32_t *val) in read_slcr()
/optee_os/core/drivers/crypto/caam/hal/imx_8q/registers/
A Dctrl_regs.h19 #define JRxDID_MS_PRIM_ICID(val) SHIFT_U32((val) & (0x3FF), 19) argument
24 #define JRxDID_MS_PRIM_DID(val) SHIFT_U32((val) & (0xF), 0) argument
/optee_os/core/drivers/crypto/caam/hal/imx_8m/registers/
A Dctrl_regs.h24 #define JRxDID_MS_PRIM_ICID(val) SHIFT_U32(((val) & 0x3FF), 19) argument
29 #define JRxDID_MS_PRIM_DID(val) SHIFT_U32(((val) & 0xF), 0) argument
/optee_os/core/drivers/crypto/caam/include/
A Dcaam_io.h18 #define io_caam_write32(a, val) io_write32(a, TEE_U32_TO_BIG_ENDIAN(val)) argument
26 #define io_caam_write32(a, val) io_write32(a, val) argument
/optee_os/ldelf/
A Dta_elf_rel.c38 vaddr_t *val, bool weak_ok) in __resolve_sym()
82 vaddr_t *val, struct ta_elf *elf, in resolve_sym_helper()
153 TEE_Result ta_elf_resolve_sym(const char *name, vaddr_t *val, in ta_elf_resolve_sym()
205 static void resolve_sym(const char *name, vaddr_t *val, struct ta_elf **mod) in resolve_sym()
218 vaddr_t val = 0; in e32_process_dyn_rel() local
247 Elf32_Rel *rel, vaddr_t *val) in e32_tls_resolve()
328 vaddr_t val = 0; in e32_relocate() local
424 uintptr_t val = 0; in e64_process_dyn_rela() local

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