1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Architecture-specific setup.
4 *
5 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 2000, 2004 Intel Corp
9 * Rohit Seth <rohit.seth@intel.com>
10 * Suresh Siddha <suresh.b.siddha@intel.com>
11 * Gordon Jin <gordon.jin@intel.com>
12 * Copyright (C) 1999 VA Linux Systems
13 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
14 *
15 * 12/26/04 S.Siddha, G.Jin, R.Seth
16 * Add multi-threading and multi-core detection
17 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
18 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
19 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
20 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
21 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
22 * 01/07/99 S.Eranian added the support for command line argument
23 * 06/24/99 W.Drummond added boot_cpu_data.
24 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
25 */
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/pgtable.h>
29
30 #include <linux/acpi.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/cpu.h>
34 #include <linux/kdev_t.h>
35 #include <linux/kernel.h>
36 #include <linux/memblock.h>
37 #include <linux/reboot.h>
38 #include <linux/sched/mm.h>
39 #include <linux/sched/clock.h>
40 #include <linux/sched/task_stack.h>
41 #include <linux/seq_file.h>
42 #include <linux/string.h>
43 #include <linux/threads.h>
44 #include <linux/screen_info.h>
45 #include <linux/dmi.h>
46 #include <linux/root_dev.h>
47 #include <linux/serial.h>
48 #include <linux/serial_core.h>
49 #include <linux/efi.h>
50 #include <linux/initrd.h>
51 #include <linux/pm.h>
52 #include <linux/cpufreq.h>
53 #include <linux/kexec.h>
54 #include <linux/crash_dump.h>
55
56 #include <asm/mca.h>
57 #include <asm/meminit.h>
58 #include <asm/page.h>
59 #include <asm/patch.h>
60 #include <asm/processor.h>
61 #include <asm/sal.h>
62 #include <asm/sections.h>
63 #include <asm/setup.h>
64 #include <asm/smp.h>
65 #include <asm/tlbflush.h>
66 #include <asm/unistd.h>
67 #include <asm/uv/uv.h>
68 #include <asm/xtp.h>
69
70 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
71 # error "struct cpuinfo_ia64 too big!"
72 #endif
73
74 char ia64_platform_name[64];
75
76 #ifdef CONFIG_SMP
77 unsigned long __per_cpu_offset[NR_CPUS];
78 EXPORT_SYMBOL(__per_cpu_offset);
79 #endif
80
81 DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info);
82 EXPORT_SYMBOL(ia64_cpu_info);
83 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
84 #ifdef CONFIG_SMP
85 EXPORT_SYMBOL(local_per_cpu_offset);
86 #endif
87 unsigned long ia64_cycles_per_usec;
88 struct ia64_boot_param *ia64_boot_param;
89 struct screen_info screen_info;
90 unsigned long vga_console_iobase;
91 unsigned long vga_console_membase;
92
93 static struct resource data_resource = {
94 .name = "Kernel data",
95 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
96 };
97
98 static struct resource code_resource = {
99 .name = "Kernel code",
100 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
101 };
102
103 static struct resource bss_resource = {
104 .name = "Kernel bss",
105 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
106 };
107
108 unsigned long ia64_max_cacheline_size;
109
110 unsigned long ia64_iobase; /* virtual address for I/O accesses */
111 EXPORT_SYMBOL(ia64_iobase);
112 struct io_space io_space[MAX_IO_SPACES];
113 EXPORT_SYMBOL(io_space);
114 unsigned int num_io_spaces;
115
116 /*
117 * "flush_icache_range()" needs to know what processor dependent stride size to use
118 * when it makes i-cache(s) coherent with d-caches.
119 */
120 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
121 unsigned long ia64_i_cache_stride_shift = ~0;
122 /*
123 * "clflush_cache_range()" needs to know what processor dependent stride size to
124 * use when it flushes cache lines including both d-cache and i-cache.
125 */
126 /* Safest way to go: 32 bytes by 32 bytes */
127 #define CACHE_STRIDE_SHIFT 5
128 unsigned long ia64_cache_stride_shift = ~0;
129
130 /*
131 * We use a special marker for the end of memory and it uses the extra (+1) slot
132 */
133 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
134 static int num_rsvd_regions __initdata;
135
136
137 /*
138 * Filter incoming memory segments based on the primitive map created from the boot
139 * parameters. Segments contained in the map are removed from the memory ranges. A
140 * caller-specified function is called with the memory ranges that remain after filtering.
141 * This routine does not assume the incoming segments are sorted.
142 */
143 int __init
filter_rsvd_memory(u64 start,u64 end,void * arg)144 filter_rsvd_memory (u64 start, u64 end, void *arg)
145 {
146 u64 range_start, range_end, prev_start;
147 void (*func)(unsigned long, unsigned long, int);
148 int i;
149
150 #if IGNORE_PFN0
151 if (start == PAGE_OFFSET) {
152 printk(KERN_WARNING "warning: skipping physical page 0\n");
153 start += PAGE_SIZE;
154 if (start >= end) return 0;
155 }
156 #endif
157 /*
158 * lowest possible address(walker uses virtual)
159 */
160 prev_start = PAGE_OFFSET;
161 func = arg;
162
163 for (i = 0; i < num_rsvd_regions; ++i) {
164 range_start = max(start, prev_start);
165 range_end = min(end, rsvd_region[i].start);
166
167 if (range_start < range_end)
168 call_pernode_memory(__pa(range_start), range_end - range_start, func);
169
170 /* nothing more available in this segment */
171 if (range_end == end) return 0;
172
173 prev_start = rsvd_region[i].end;
174 }
175 /* end of memory marker allows full processing inside loop body */
176 return 0;
177 }
178
179 /*
180 * Similar to "filter_rsvd_memory()", but the reserved memory ranges
181 * are not filtered out.
182 */
183 int __init
filter_memory(u64 start,u64 end,void * arg)184 filter_memory(u64 start, u64 end, void *arg)
185 {
186 void (*func)(unsigned long, unsigned long, int);
187
188 #if IGNORE_PFN0
189 if (start == PAGE_OFFSET) {
190 printk(KERN_WARNING "warning: skipping physical page 0\n");
191 start += PAGE_SIZE;
192 if (start >= end)
193 return 0;
194 }
195 #endif
196 func = arg;
197 if (start < end)
198 call_pernode_memory(__pa(start), end - start, func);
199 return 0;
200 }
201
202 static void __init
sort_regions(struct rsvd_region * rsvd_region,int max)203 sort_regions (struct rsvd_region *rsvd_region, int max)
204 {
205 int j;
206
207 /* simple bubble sorting */
208 while (max--) {
209 for (j = 0; j < max; ++j) {
210 if (rsvd_region[j].start > rsvd_region[j+1].start) {
211 struct rsvd_region tmp;
212 tmp = rsvd_region[j];
213 rsvd_region[j] = rsvd_region[j + 1];
214 rsvd_region[j + 1] = tmp;
215 }
216 }
217 }
218 }
219
220 /* merge overlaps */
221 static int __init
merge_regions(struct rsvd_region * rsvd_region,int max)222 merge_regions (struct rsvd_region *rsvd_region, int max)
223 {
224 int i;
225 for (i = 1; i < max; ++i) {
226 if (rsvd_region[i].start >= rsvd_region[i-1].end)
227 continue;
228 if (rsvd_region[i].end > rsvd_region[i-1].end)
229 rsvd_region[i-1].end = rsvd_region[i].end;
230 --max;
231 memmove(&rsvd_region[i], &rsvd_region[i+1],
232 (max - i) * sizeof(struct rsvd_region));
233 }
234 return max;
235 }
236
237 /*
238 * Request address space for all standard resources
239 */
register_memory(void)240 static int __init register_memory(void)
241 {
242 code_resource.start = ia64_tpa(_text);
243 code_resource.end = ia64_tpa(_etext) - 1;
244 data_resource.start = ia64_tpa(_etext);
245 data_resource.end = ia64_tpa(_edata) - 1;
246 bss_resource.start = ia64_tpa(__bss_start);
247 bss_resource.end = ia64_tpa(_end) - 1;
248 efi_initialize_iomem_resources(&code_resource, &data_resource,
249 &bss_resource);
250
251 return 0;
252 }
253
254 __initcall(register_memory);
255
256
257 #ifdef CONFIG_KEXEC
258
259 /*
260 * This function checks if the reserved crashkernel is allowed on the specific
261 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require
262 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of
263 * kernel/dma/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that
264 * in kdump case. See the comment in sba_init() in sba_iommu.c.
265 *
266 * So, the only machvec that really supports loading the kdump kernel
267 * over 4 GB is "uv".
268 */
check_crashkernel_memory(unsigned long pbase,size_t size)269 static int __init check_crashkernel_memory(unsigned long pbase, size_t size)
270 {
271 if (is_uv_system())
272 return 1;
273 else
274 return pbase < (1UL << 32);
275 }
276
setup_crashkernel(unsigned long total,int * n)277 static void __init setup_crashkernel(unsigned long total, int *n)
278 {
279 unsigned long long base = 0, size = 0;
280 int ret;
281
282 ret = parse_crashkernel(boot_command_line, total,
283 &size, &base);
284 if (ret == 0 && size > 0) {
285 if (!base) {
286 sort_regions(rsvd_region, *n);
287 *n = merge_regions(rsvd_region, *n);
288 base = kdump_find_rsvd_region(size,
289 rsvd_region, *n);
290 }
291
292 if (!check_crashkernel_memory(base, size)) {
293 pr_warn("crashkernel: There would be kdump memory "
294 "at %ld GB but this is unusable because it "
295 "must\nbe below 4 GB. Change the memory "
296 "configuration of the machine.\n",
297 (unsigned long)(base >> 30));
298 return;
299 }
300
301 if (base != ~0UL) {
302 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
303 "for crashkernel (System RAM: %ldMB)\n",
304 (unsigned long)(size >> 20),
305 (unsigned long)(base >> 20),
306 (unsigned long)(total >> 20));
307 rsvd_region[*n].start =
308 (unsigned long)__va(base);
309 rsvd_region[*n].end =
310 (unsigned long)__va(base + size);
311 (*n)++;
312 crashk_res.start = base;
313 crashk_res.end = base + size - 1;
314 }
315 }
316 efi_memmap_res.start = ia64_boot_param->efi_memmap;
317 efi_memmap_res.end = efi_memmap_res.start +
318 ia64_boot_param->efi_memmap_size;
319 boot_param_res.start = __pa(ia64_boot_param);
320 boot_param_res.end = boot_param_res.start +
321 sizeof(*ia64_boot_param);
322 }
323 #else
setup_crashkernel(unsigned long total,int * n)324 static inline void __init setup_crashkernel(unsigned long total, int *n)
325 {}
326 #endif
327
328 #ifdef CONFIG_CRASH_DUMP
reserve_elfcorehdr(u64 * start,u64 * end)329 static int __init reserve_elfcorehdr(u64 *start, u64 *end)
330 {
331 u64 length;
332
333 /* We get the address using the kernel command line,
334 * but the size is extracted from the EFI tables.
335 * Both address and size are required for reservation
336 * to work properly.
337 */
338
339 if (!is_vmcore_usable())
340 return -EINVAL;
341
342 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) {
343 vmcore_unusable();
344 return -EINVAL;
345 }
346
347 *start = (unsigned long)__va(elfcorehdr_addr);
348 *end = *start + length;
349 return 0;
350 }
351 #endif /* CONFIG_CRASH_DUMP */
352
353 /**
354 * reserve_memory - setup reserved memory areas
355 *
356 * Setup the reserved memory areas set aside for the boot parameters,
357 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
358 * see arch/ia64/include/asm/meminit.h if you need to define more.
359 */
360 void __init
reserve_memory(void)361 reserve_memory (void)
362 {
363 int n = 0;
364 unsigned long total_memory;
365
366 /*
367 * none of the entries in this table overlap
368 */
369 rsvd_region[n].start = (unsigned long) ia64_boot_param;
370 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
371 n++;
372
373 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
374 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
375 n++;
376
377 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
378 rsvd_region[n].end = (rsvd_region[n].start
379 + strlen(__va(ia64_boot_param->command_line)) + 1);
380 n++;
381
382 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
383 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
384 n++;
385
386 #ifdef CONFIG_BLK_DEV_INITRD
387 if (ia64_boot_param->initrd_start) {
388 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
389 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
390 n++;
391 }
392 #endif
393
394 #ifdef CONFIG_CRASH_DUMP
395 if (reserve_elfcorehdr(&rsvd_region[n].start,
396 &rsvd_region[n].end) == 0)
397 n++;
398 #endif
399
400 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
401 n++;
402
403 setup_crashkernel(total_memory, &n);
404
405 /* end of memory marker */
406 rsvd_region[n].start = ~0UL;
407 rsvd_region[n].end = ~0UL;
408 n++;
409
410 num_rsvd_regions = n;
411 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
412
413 sort_regions(rsvd_region, num_rsvd_regions);
414 num_rsvd_regions = merge_regions(rsvd_region, num_rsvd_regions);
415
416 /* reserve all regions except the end of memory marker with memblock */
417 for (n = 0; n < num_rsvd_regions - 1; n++) {
418 struct rsvd_region *region = &rsvd_region[n];
419 phys_addr_t addr = __pa(region->start);
420 phys_addr_t size = region->end - region->start;
421
422 memblock_reserve(addr, size);
423 }
424 }
425
426 /**
427 * find_initrd - get initrd parameters from the boot parameter structure
428 *
429 * Grab the initrd start and end from the boot parameter struct given us by
430 * the boot loader.
431 */
432 void __init
find_initrd(void)433 find_initrd (void)
434 {
435 #ifdef CONFIG_BLK_DEV_INITRD
436 if (ia64_boot_param->initrd_start) {
437 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
438 initrd_end = initrd_start+ia64_boot_param->initrd_size;
439
440 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n",
441 initrd_start, ia64_boot_param->initrd_size);
442 }
443 #endif
444 }
445
446 static void __init
io_port_init(void)447 io_port_init (void)
448 {
449 unsigned long phys_iobase;
450
451 /*
452 * Set `iobase' based on the EFI memory map or, failing that, the
453 * value firmware left in ar.k0.
454 *
455 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
456 * the port's virtual address, so ia32_load_state() loads it with a
457 * user virtual address. But in ia64 mode, glibc uses the
458 * *physical* address in ar.k0 to mmap the appropriate area from
459 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
460 * cases, user-mode can only use the legacy 0-64K I/O port space.
461 *
462 * ar.k0 is not involved in kernel I/O port accesses, which can use
463 * any of the I/O port spaces and are done via MMIO using the
464 * virtual mmio_base from the appropriate io_space[].
465 */
466 phys_iobase = efi_get_iobase();
467 if (!phys_iobase) {
468 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
469 printk(KERN_INFO "No I/O port range found in EFI memory map, "
470 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
471 }
472 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
473 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
474
475 /* setup legacy IO port space */
476 io_space[0].mmio_base = ia64_iobase;
477 io_space[0].sparse = 1;
478 num_io_spaces = 1;
479 }
480
481 /**
482 * early_console_setup - setup debugging console
483 *
484 * Consoles started here require little enough setup that we can start using
485 * them very early in the boot process, either right after the machine
486 * vector initialization, or even before if the drivers can detect their hw.
487 *
488 * Returns non-zero if a console couldn't be setup.
489 */
490 static inline int __init
early_console_setup(char * cmdline)491 early_console_setup (char *cmdline)
492 {
493 #ifdef CONFIG_EFI_PCDP
494 if (!efi_setup_pcdp_console(cmdline))
495 return 0;
496 #endif
497 return -1;
498 }
499
500 static void __init
screen_info_setup(void)501 screen_info_setup(void)
502 {
503 unsigned int orig_x, orig_y, num_cols, num_rows, font_height;
504
505 memset(&screen_info, 0, sizeof(screen_info));
506
507 if (!ia64_boot_param->console_info.num_rows ||
508 !ia64_boot_param->console_info.num_cols) {
509 printk(KERN_WARNING "invalid screen-info, guessing 80x25\n");
510 orig_x = 0;
511 orig_y = 0;
512 num_cols = 80;
513 num_rows = 25;
514 font_height = 16;
515 } else {
516 orig_x = ia64_boot_param->console_info.orig_x;
517 orig_y = ia64_boot_param->console_info.orig_y;
518 num_cols = ia64_boot_param->console_info.num_cols;
519 num_rows = ia64_boot_param->console_info.num_rows;
520 font_height = 400 / num_rows;
521 }
522
523 screen_info.orig_x = orig_x;
524 screen_info.orig_y = orig_y;
525 screen_info.orig_video_cols = num_cols;
526 screen_info.orig_video_lines = num_rows;
527 screen_info.orig_video_points = font_height;
528 screen_info.orig_video_mode = 3; /* XXX fake */
529 screen_info.orig_video_isVGA = 1; /* XXX fake */
530 screen_info.orig_video_ega_bx = 3; /* XXX fake */
531 }
532
533 static inline void
mark_bsp_online(void)534 mark_bsp_online (void)
535 {
536 #ifdef CONFIG_SMP
537 /* If we register an early console, allow CPU 0 to printk */
538 set_cpu_online(smp_processor_id(), true);
539 #endif
540 }
541
542 static __initdata int nomca;
setup_nomca(char * s)543 static __init int setup_nomca(char *s)
544 {
545 nomca = 1;
546 return 0;
547 }
548 early_param("nomca", setup_nomca);
549
550 void __init
setup_arch(char ** cmdline_p)551 setup_arch (char **cmdline_p)
552 {
553 unw_init();
554
555 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
556
557 *cmdline_p = __va(ia64_boot_param->command_line);
558 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
559
560 efi_init();
561 io_port_init();
562
563 uv_probe_system_type();
564 parse_early_param();
565
566 if (early_console_setup(*cmdline_p) == 0)
567 mark_bsp_online();
568
569 /* Initialize the ACPI boot-time table parser */
570 acpi_table_init();
571 early_acpi_boot_init();
572 #ifdef CONFIG_ACPI_NUMA
573 acpi_numa_init();
574 acpi_numa_fixup();
575 #ifdef CONFIG_ACPI_HOTPLUG_CPU
576 prefill_possible_map();
577 #endif
578 per_cpu_scan_finalize((cpumask_weight(&early_cpu_possible_map) == 0 ?
579 32 : cpumask_weight(&early_cpu_possible_map)),
580 additional_cpus > 0 ? additional_cpus : 0);
581 #endif /* CONFIG_ACPI_NUMA */
582
583 #ifdef CONFIG_SMP
584 smp_build_cpu_map();
585 #endif
586 find_memory();
587
588 /* process SAL system table: */
589 ia64_sal_init(__va(sal_systab_phys));
590
591 #ifdef CONFIG_ITANIUM
592 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist);
593 #else
594 {
595 unsigned long num_phys_stacked;
596
597 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96)
598 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist);
599 }
600 #endif
601
602 #ifdef CONFIG_SMP
603 cpu_physical_id(0) = hard_smp_processor_id();
604 #endif
605
606 cpu_init(); /* initialize the bootstrap CPU */
607 mmu_context_init(); /* initialize context_id bitmap */
608
609 #ifdef CONFIG_VT
610 if (!conswitchp) {
611 # if defined(CONFIG_VGA_CONSOLE)
612 /*
613 * Non-legacy systems may route legacy VGA MMIO range to system
614 * memory. vga_con probes the MMIO hole, so memory looks like
615 * a VGA device to it. The EFI memory map can tell us if it's
616 * memory so we can avoid this problem.
617 */
618 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
619 conswitchp = &vga_con;
620 # endif
621 }
622 #endif
623
624 /* enable IA-64 Machine Check Abort Handling unless disabled */
625 if (!nomca)
626 ia64_mca_init();
627
628 /*
629 * Default to /dev/sda2. This assumes that the EFI partition
630 * is physical disk 1 partition 1 and the Linux root disk is
631 * physical disk 1 partition 2.
632 */
633 ROOT_DEV = Root_SDA2; /* default to second partition on first drive */
634
635 if (is_uv_system())
636 uv_setup(cmdline_p);
637 #ifdef CONFIG_SMP
638 else
639 init_smp_config();
640 #endif
641
642 screen_info_setup();
643 paging_init();
644
645 clear_sched_clock_stable();
646 }
647
648 /*
649 * Display cpu info for all CPUs.
650 */
651 static int
show_cpuinfo(struct seq_file * m,void * v)652 show_cpuinfo (struct seq_file *m, void *v)
653 {
654 #ifdef CONFIG_SMP
655 # define lpj c->loops_per_jiffy
656 # define cpunum c->cpu
657 #else
658 # define lpj loops_per_jiffy
659 # define cpunum 0
660 #endif
661 static struct {
662 unsigned long mask;
663 const char *feature_name;
664 } feature_bits[] = {
665 { 1UL << 0, "branchlong" },
666 { 1UL << 1, "spontaneous deferral"},
667 { 1UL << 2, "16-byte atomic ops" }
668 };
669 char features[128], *cp, *sep;
670 struct cpuinfo_ia64 *c = v;
671 unsigned long mask;
672 unsigned long proc_freq;
673 int i, size;
674
675 mask = c->features;
676
677 /* build the feature string: */
678 memcpy(features, "standard", 9);
679 cp = features;
680 size = sizeof(features);
681 sep = "";
682 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) {
683 if (mask & feature_bits[i].mask) {
684 cp += snprintf(cp, size, "%s%s", sep,
685 feature_bits[i].feature_name),
686 sep = ", ";
687 mask &= ~feature_bits[i].mask;
688 size = sizeof(features) - (cp - features);
689 }
690 }
691 if (mask && size > 1) {
692 /* print unknown features as a hex value */
693 snprintf(cp, size, "%s0x%lx", sep, mask);
694 }
695
696 proc_freq = cpufreq_quick_get(cpunum);
697 if (!proc_freq)
698 proc_freq = c->proc_freq / 1000;
699
700 seq_printf(m,
701 "processor : %d\n"
702 "vendor : %s\n"
703 "arch : IA-64\n"
704 "family : %u\n"
705 "model : %u\n"
706 "model name : %s\n"
707 "revision : %u\n"
708 "archrev : %u\n"
709 "features : %s\n"
710 "cpu number : %lu\n"
711 "cpu regs : %u\n"
712 "cpu MHz : %lu.%03lu\n"
713 "itc MHz : %lu.%06lu\n"
714 "BogoMIPS : %lu.%02lu\n",
715 cpunum, c->vendor, c->family, c->model,
716 c->model_name, c->revision, c->archrev,
717 features, c->ppn, c->number,
718 proc_freq / 1000, proc_freq % 1000,
719 c->itc_freq / 1000000, c->itc_freq % 1000000,
720 lpj*HZ/500000, (lpj*HZ/5000) % 100);
721 #ifdef CONFIG_SMP
722 seq_printf(m, "siblings : %u\n",
723 cpumask_weight(&cpu_core_map[cpunum]));
724 if (c->socket_id != -1)
725 seq_printf(m, "physical id: %u\n", c->socket_id);
726 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
727 seq_printf(m,
728 "core id : %u\n"
729 "thread id : %u\n",
730 c->core_id, c->thread_id);
731 #endif
732 seq_printf(m,"\n");
733
734 return 0;
735 }
736
737 static void *
c_start(struct seq_file * m,loff_t * pos)738 c_start (struct seq_file *m, loff_t *pos)
739 {
740 #ifdef CONFIG_SMP
741 while (*pos < nr_cpu_ids && !cpu_online(*pos))
742 ++*pos;
743 #endif
744 return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL;
745 }
746
747 static void *
c_next(struct seq_file * m,void * v,loff_t * pos)748 c_next (struct seq_file *m, void *v, loff_t *pos)
749 {
750 ++*pos;
751 return c_start(m, pos);
752 }
753
754 static void
c_stop(struct seq_file * m,void * v)755 c_stop (struct seq_file *m, void *v)
756 {
757 }
758
759 const struct seq_operations cpuinfo_op = {
760 .start = c_start,
761 .next = c_next,
762 .stop = c_stop,
763 .show = show_cpuinfo
764 };
765
766 #define MAX_BRANDS 8
767 static char brandname[MAX_BRANDS][128];
768
769 static char *
get_model_name(__u8 family,__u8 model)770 get_model_name(__u8 family, __u8 model)
771 {
772 static int overflow;
773 char brand[128];
774 int i;
775
776 memcpy(brand, "Unknown", 8);
777 if (ia64_pal_get_brand_info(brand)) {
778 if (family == 0x7)
779 memcpy(brand, "Merced", 7);
780 else if (family == 0x1f) switch (model) {
781 case 0: memcpy(brand, "McKinley", 9); break;
782 case 1: memcpy(brand, "Madison", 8); break;
783 case 2: memcpy(brand, "Madison up to 9M cache", 23); break;
784 }
785 }
786 for (i = 0; i < MAX_BRANDS; i++)
787 if (strcmp(brandname[i], brand) == 0)
788 return brandname[i];
789 for (i = 0; i < MAX_BRANDS; i++)
790 if (brandname[i][0] == '\0')
791 return strcpy(brandname[i], brand);
792 if (overflow++ == 0)
793 printk(KERN_ERR
794 "%s: Table overflow. Some processor model information will be missing\n",
795 __func__);
796 return "Unknown";
797 }
798
799 static void
identify_cpu(struct cpuinfo_ia64 * c)800 identify_cpu (struct cpuinfo_ia64 *c)
801 {
802 union {
803 unsigned long bits[5];
804 struct {
805 /* id 0 & 1: */
806 char vendor[16];
807
808 /* id 2 */
809 u64 ppn; /* processor serial number */
810
811 /* id 3: */
812 unsigned number : 8;
813 unsigned revision : 8;
814 unsigned model : 8;
815 unsigned family : 8;
816 unsigned archrev : 8;
817 unsigned reserved : 24;
818
819 /* id 4: */
820 u64 features;
821 } field;
822 } cpuid;
823 pal_vm_info_1_u_t vm1;
824 pal_vm_info_2_u_t vm2;
825 pal_status_t status;
826 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
827 int i;
828 for (i = 0; i < 5; ++i)
829 cpuid.bits[i] = ia64_get_cpuid(i);
830
831 memcpy(c->vendor, cpuid.field.vendor, 16);
832 #ifdef CONFIG_SMP
833 c->cpu = smp_processor_id();
834
835 /* below default values will be overwritten by identify_siblings()
836 * for Multi-Threading/Multi-Core capable CPUs
837 */
838 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
839 c->socket_id = -1;
840
841 identify_siblings(c);
842
843 if (c->threads_per_core > smp_num_siblings)
844 smp_num_siblings = c->threads_per_core;
845 #endif
846 c->ppn = cpuid.field.ppn;
847 c->number = cpuid.field.number;
848 c->revision = cpuid.field.revision;
849 c->model = cpuid.field.model;
850 c->family = cpuid.field.family;
851 c->archrev = cpuid.field.archrev;
852 c->features = cpuid.field.features;
853 c->model_name = get_model_name(c->family, c->model);
854
855 status = ia64_pal_vm_summary(&vm1, &vm2);
856 if (status == PAL_STATUS_SUCCESS) {
857 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
858 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
859 }
860 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
861 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
862 }
863
864 /*
865 * Do the following calculations:
866 *
867 * 1. the max. cache line size.
868 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()".
869 * 3. the minimum of the cache stride sizes for "clflush_cache_range()".
870 */
871 static void
get_cache_info(void)872 get_cache_info(void)
873 {
874 unsigned long line_size, max = 1;
875 unsigned long l, levels, unique_caches;
876 pal_cache_config_info_t cci;
877 long status;
878
879 status = ia64_pal_cache_summary(&levels, &unique_caches);
880 if (status != 0) {
881 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
882 __func__, status);
883 max = SMP_CACHE_BYTES;
884 /* Safest setup for "flush_icache_range()" */
885 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
886 /* Safest setup for "clflush_cache_range()" */
887 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT;
888 goto out;
889 }
890
891 for (l = 0; l < levels; ++l) {
892 /* cache_type (data_or_unified)=2 */
893 status = ia64_pal_cache_config_info(l, 2, &cci);
894 if (status != 0) {
895 printk(KERN_ERR "%s: ia64_pal_cache_config_info"
896 "(l=%lu, 2) failed (status=%ld)\n",
897 __func__, l, status);
898 max = SMP_CACHE_BYTES;
899 /* The safest setup for "flush_icache_range()" */
900 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
901 /* The safest setup for "clflush_cache_range()" */
902 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT;
903 cci.pcci_unified = 1;
904 } else {
905 if (cci.pcci_stride < ia64_cache_stride_shift)
906 ia64_cache_stride_shift = cci.pcci_stride;
907
908 line_size = 1 << cci.pcci_line_size;
909 if (line_size > max)
910 max = line_size;
911 }
912
913 if (!cci.pcci_unified) {
914 /* cache_type (instruction)=1*/
915 status = ia64_pal_cache_config_info(l, 1, &cci);
916 if (status != 0) {
917 printk(KERN_ERR "%s: ia64_pal_cache_config_info"
918 "(l=%lu, 1) failed (status=%ld)\n",
919 __func__, l, status);
920 /* The safest setup for flush_icache_range() */
921 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
922 }
923 }
924 if (cci.pcci_stride < ia64_i_cache_stride_shift)
925 ia64_i_cache_stride_shift = cci.pcci_stride;
926 }
927 out:
928 if (max > ia64_max_cacheline_size)
929 ia64_max_cacheline_size = max;
930 }
931
932 /*
933 * cpu_init() initializes state that is per-CPU. This function acts
934 * as a 'CPU state barrier', nothing should get across.
935 */
936 void
cpu_init(void)937 cpu_init (void)
938 {
939 extern void ia64_mmu_init(void *);
940 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG;
941 unsigned long num_phys_stacked;
942 pal_vm_info_2_u_t vmi;
943 unsigned int max_ctx;
944 struct cpuinfo_ia64 *cpu_info;
945 void *cpu_data;
946
947 cpu_data = per_cpu_init();
948 #ifdef CONFIG_SMP
949 /*
950 * insert boot cpu into sibling and core mapes
951 * (must be done after per_cpu area is setup)
952 */
953 if (smp_processor_id() == 0) {
954 cpumask_set_cpu(0, &per_cpu(cpu_sibling_map, 0));
955 cpumask_set_cpu(0, &cpu_core_map[0]);
956 } else {
957 /*
958 * Set ar.k3 so that assembly code in MCA handler can compute
959 * physical addresses of per cpu variables with a simple:
960 * phys = ar.k3 + &per_cpu_var
961 * and the alt-dtlb-miss handler can set per-cpu mapping into
962 * the TLB when needed. head.S already did this for cpu0.
963 */
964 ia64_set_kr(IA64_KR_PER_CPU_DATA,
965 ia64_tpa(cpu_data) - (long) __per_cpu_start);
966 }
967 #endif
968
969 get_cache_info();
970
971 /*
972 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
973 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
974 * depends on the data returned by identify_cpu(). We break the dependency by
975 * accessing cpu_data() through the canonical per-CPU address.
976 */
977 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start);
978 identify_cpu(cpu_info);
979
980 #ifdef CONFIG_MCKINLEY
981 {
982 # define FEATURE_SET 16
983 struct ia64_pal_retval iprv;
984
985 if (cpu_info->family == 0x1f) {
986 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
987 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
988 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
989 (iprv.v1 | 0x80), FEATURE_SET, 0);
990 }
991 }
992 #endif
993
994 /* Clear the stack memory reserved for pt_regs: */
995 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
996
997 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
998
999 /*
1000 * Initialize the page-table base register to a global
1001 * directory with all zeroes. This ensure that we can handle
1002 * TLB-misses to user address-space even before we created the
1003 * first user address-space. This may happen, e.g., due to
1004 * aggressive use of lfetch.fault.
1005 */
1006 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
1007
1008 /*
1009 * Initialize default control register to defer speculative faults except
1010 * for those arising from TLB misses, which are not deferred. The
1011 * kernel MUST NOT depend on a particular setting of these bits (in other words,
1012 * the kernel must have recovery code for all speculative accesses). Turn on
1013 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
1014 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
1015 * be fine).
1016 */
1017 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
1018 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
1019 mmgrab(&init_mm);
1020 current->active_mm = &init_mm;
1021 BUG_ON(current->mm);
1022
1023 ia64_mmu_init(ia64_imva(cpu_data));
1024 ia64_mca_cpu_init(ia64_imva(cpu_data));
1025
1026 /* Clear ITC to eliminate sched_clock() overflows in human time. */
1027 ia64_set_itc(0);
1028
1029 /* disable all local interrupt sources: */
1030 ia64_set_itv(1 << 16);
1031 ia64_set_lrr0(1 << 16);
1032 ia64_set_lrr1(1 << 16);
1033 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
1034 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
1035
1036 /* clear TPR & XTP to enable all interrupt classes: */
1037 ia64_setreg(_IA64_REG_CR_TPR, 0);
1038
1039 /* Clear any pending interrupts left by SAL/EFI */
1040 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR)
1041 ia64_eoi();
1042
1043 #ifdef CONFIG_SMP
1044 normal_xtp();
1045 #endif
1046
1047 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
1048 if (ia64_pal_vm_summary(NULL, &vmi) == 0) {
1049 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
1050 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL);
1051 } else {
1052 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
1053 max_ctx = (1U << 15) - 1; /* use architected minimum */
1054 }
1055 while (max_ctx < ia64_ctx.max_ctx) {
1056 unsigned int old = ia64_ctx.max_ctx;
1057 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
1058 break;
1059 }
1060
1061 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
1062 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
1063 "stacked regs\n");
1064 num_phys_stacked = 96;
1065 }
1066 /* size of physical stacked register partition plus 8 bytes: */
1067 if (num_phys_stacked > max_num_phys_stacked) {
1068 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8);
1069 max_num_phys_stacked = num_phys_stacked;
1070 }
1071 }
1072
1073 void __init
check_bugs(void)1074 check_bugs (void)
1075 {
1076 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
1077 (unsigned long) __end___mckinley_e9_bundles);
1078 }
1079
run_dmi_scan(void)1080 static int __init run_dmi_scan(void)
1081 {
1082 dmi_setup();
1083 return 0;
1084 }
1085 core_initcall(run_dmi_scan);
1086