1 /*
2 * hvm_vlapic.h: virtualize LAPIC definitions.
3 *
4 * Copyright (c) 2004, Intel Corporation.
5 * Copyright (c) 2006 Keir Fraser, XenSource Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef __ASM_X86_HVM_VLAPIC_H__
21 #define __ASM_X86_HVM_VLAPIC_H__
22
23 #include <xen/tasklet.h>
24 #include <asm/hvm/vpt.h>
25
26 #define vcpu_vlapic(x) (&(x)->arch.hvm.vlapic)
27 #define vlapic_vcpu(x) (container_of((x), struct vcpu, arch.hvm.vlapic))
28 #define const_vlapic_vcpu(x) (container_of((x), const struct vcpu, \
29 arch.hvm.vlapic))
30 #define vlapic_domain(x) (vlapic_vcpu(x)->domain)
31
32 #define _VLAPIC_ID(vlapic, id) (vlapic_x2apic_mode(vlapic) \
33 ? (id) : GET_xAPIC_ID(id))
34 #define VLAPIC_ID(vlapic) _VLAPIC_ID(vlapic, vlapic_get_reg(vlapic, APIC_ID))
35
36 /*
37 * APIC can be disabled in two ways:
38 * 1. 'Hardware disable': via IA32_APIC_BASE_MSR[11]
39 * CPU should behave as if it does not have an APIC.
40 * 2. 'Software disable': via APIC_SPIV[8].
41 * APIC is visible but does not respond to interrupt messages.
42 */
43 #define VLAPIC_HW_DISABLED 0x1
44 #define VLAPIC_SW_DISABLED 0x2
45 #define vlapic_sw_disabled(vlapic) ((vlapic)->hw.disabled & VLAPIC_SW_DISABLED)
46 #define vlapic_hw_disabled(vlapic) ((vlapic)->hw.disabled & VLAPIC_HW_DISABLED)
47 #define vlapic_disabled(vlapic) ((vlapic)->hw.disabled)
48 #define vlapic_enabled(vlapic) (!vlapic_disabled(vlapic))
49
50 #define vlapic_base_address(vlapic) \
51 ((vlapic)->hw.apic_base_msr & APIC_BASE_ADDR_MASK)
52 /* Only check EXTD bit as EXTD can't be set if it is disabled by hardware */
53 #define vlapic_x2apic_mode(vlapic) \
54 ((vlapic)->hw.apic_base_msr & APIC_BASE_EXTD)
55 #define vlapic_xapic_mode(vlapic) \
56 (!vlapic_hw_disabled(vlapic) && \
57 !((vlapic)->hw.apic_base_msr & APIC_BASE_EXTD))
58
59 /*
60 * Generic APIC bitmap vector update & search routines.
61 */
62
63 #define VEC_POS(v) ((v) % 32)
64 #define REG_POS(v) (((v) / 32) * 0x10)
65 #define vlapic_test_vector(vec, bitmap) \
66 test_bit(VEC_POS(vec), (const uint32_t *)((bitmap) + REG_POS(vec)))
67 #define vlapic_test_and_set_vector(vec, bitmap) \
68 test_and_set_bit(VEC_POS(vec), (uint32_t *)((bitmap) + REG_POS(vec)))
69 #define vlapic_test_and_clear_vector(vec, bitmap) \
70 test_and_clear_bit(VEC_POS(vec), (uint32_t *)((bitmap) + REG_POS(vec)))
71 #define vlapic_set_vector(vec, bitmap) \
72 set_bit(VEC_POS(vec), (uint32_t *)((bitmap) + REG_POS(vec)))
73 #define vlapic_clear_vector(vec, bitmap) \
74 clear_bit(VEC_POS(vec), (uint32_t *)((bitmap) + REG_POS(vec)))
75
76 struct vlapic {
77 struct hvm_hw_lapic hw;
78 struct hvm_hw_lapic_regs *regs;
79 struct {
80 bool_t hw, regs;
81 uint32_t id, ldr;
82 } loaded;
83 spinlock_t esr_lock;
84 struct periodic_time pt;
85 s_time_t timer_last_update;
86 struct page_info *regs_page;
87 /* INIT-SIPI-SIPI work gets deferred to a tasklet. */
88 struct {
89 uint32_t icr, dest;
90 struct tasklet tasklet;
91 } init_sipi;
92 };
93
94 /* vlapic's frequence is 100 MHz */
95 #define APIC_BUS_CYCLE_NS 10
96
vlapic_get_reg(const struct vlapic * vlapic,uint32_t reg)97 static inline uint32_t vlapic_get_reg(const struct vlapic *vlapic,
98 uint32_t reg)
99 {
100 return *((uint32_t *)(&vlapic->regs->data[reg]));
101 }
102
vlapic_set_reg(struct vlapic * vlapic,uint32_t reg,uint32_t val)103 static inline void vlapic_set_reg(
104 struct vlapic *vlapic, uint32_t reg, uint32_t val)
105 {
106 *((uint32_t *)(&vlapic->regs->data[reg])) = val;
107 }
108
109 void vlapic_reg_write(struct vcpu *v, unsigned int reg, uint32_t val);
110
111 bool_t is_vlapic_lvtpc_enabled(struct vlapic *vlapic);
112
113 bool vlapic_test_irq(const struct vlapic *vlapic, uint8_t vec);
114 void vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig);
115
116 int vlapic_has_pending_irq(struct vcpu *v);
117 int vlapic_ack_pending_irq(struct vcpu *v, int vector, bool_t force_ack);
118
119 int vlapic_init(struct vcpu *v);
120 void vlapic_destroy(struct vcpu *v);
121
122 void vlapic_reset(struct vlapic *vlapic);
123
124 int guest_wrmsr_apic_base(struct vcpu *v, uint64_t val);
125 int guest_rdmsr_x2apic(const struct vcpu *v, uint32_t msr, uint64_t *val);
126 int guest_wrmsr_x2apic(struct vcpu *v, uint32_t msr, uint64_t val);
127
128 void vlapic_tdt_msr_set(struct vlapic *vlapic, uint64_t value);
129 uint64_t vlapic_tdt_msr_get(struct vlapic *vlapic);
130
131 int vlapic_accept_pic_intr(struct vcpu *v);
132 uint32_t vlapic_set_ppr(struct vlapic *vlapic);
133
134 void vlapic_adjust_i8259_target(struct domain *d);
135
136 void vlapic_EOI_set(struct vlapic *vlapic);
137 void vlapic_handle_EOI(struct vlapic *vlapic, u8 vector);
138
139 void vlapic_ipi(struct vlapic *vlapic, uint32_t icr_low, uint32_t icr_high);
140
141 int vlapic_apicv_write(struct vcpu *v, unsigned int offset);
142
143 struct vlapic *vlapic_lowest_prio(
144 struct domain *d, const struct vlapic *source,
145 int short_hand, uint32_t dest, bool_t dest_mode);
146
147 bool_t vlapic_match_dest(
148 const struct vlapic *target, const struct vlapic *source,
149 int short_hand, uint32_t dest, bool_t dest_mode);
150
vlapic_sync_pir_to_irr(struct vcpu * v)151 static inline void vlapic_sync_pir_to_irr(struct vcpu *v)
152 {
153 if ( hvm_funcs.sync_pir_to_irr )
154 alternative_vcall(hvm_funcs.sync_pir_to_irr, v);
155 }
156
157 #endif /* __ASM_X86_HVM_VLAPIC_H__ */
158