1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
4 * All rights reserved.
5 *
6 * Purpose: rf function code
7 *
8 * Author: Jerry Chen
9 *
10 * Date: Feb. 19, 2004
11 *
12 * Functions:
13 * vnt_rf_write_embedded - Embedded write RF register via MAC
14 *
15 * Revision History:
16 * RF_VT3226: RobertYu:20051111, VT3226C0 and before
17 * RF_VT3226D0: RobertYu:20051228
18 * RF_VT3342A0: RobertYu:20060609
19 *
20 */
21
22 #include <linux/errno.h>
23 #include "mac.h"
24 #include "rf.h"
25 #include "baseband.h"
26 #include "usbpipe.h"
27
28 #define CB_AL2230_INIT_SEQ 15
29 #define CB_AL7230_INIT_SEQ 16
30 #define CB_VT3226_INIT_SEQ 11
31 #define CB_VT3342_INIT_SEQ 13
32
33 static u8 al2230_init_table[CB_AL2230_INIT_SEQ][3] = {
34 {0x03, 0xf7, 0x90},
35 {0x03, 0x33, 0x31},
36 {0x01, 0xb8, 0x02},
37 {0x00, 0xff, 0xf3},
38 {0x00, 0x05, 0xa4},
39 {0x0f, 0x4d, 0xc5},
40 {0x08, 0x05, 0xb6},
41 {0x01, 0x47, 0xc7},
42 {0x00, 0x06, 0x88},
43 {0x04, 0x03, 0xb9},
44 {0x00, 0xdb, 0xba},
45 {0x00, 0x09, 0x9b},
46 {0x0b, 0xdf, 0xfc},
47 {0x00, 0x00, 0x0d},
48 {0x00, 0x58, 0x0f}
49 };
50
51 static u8 al2230_channel_table0[CB_MAX_CHANNEL_24G][3] = {
52 {0x03, 0xf7, 0x90},
53 {0x03, 0xf7, 0x90},
54 {0x03, 0xe7, 0x90},
55 {0x03, 0xe7, 0x90},
56 {0x03, 0xf7, 0xa0},
57 {0x03, 0xf7, 0xa0},
58 {0x03, 0xe7, 0xa0},
59 {0x03, 0xe7, 0xa0},
60 {0x03, 0xf7, 0xb0},
61 {0x03, 0xf7, 0xb0},
62 {0x03, 0xe7, 0xb0},
63 {0x03, 0xe7, 0xb0},
64 {0x03, 0xf7, 0xc0},
65 {0x03, 0xe7, 0xc0}
66 };
67
68 static u8 al2230_channel_table1[CB_MAX_CHANNEL_24G][3] = {
69 {0x03, 0x33, 0x31},
70 {0x0b, 0x33, 0x31},
71 {0x03, 0x33, 0x31},
72 {0x0b, 0x33, 0x31},
73 {0x03, 0x33, 0x31},
74 {0x0b, 0x33, 0x31},
75 {0x03, 0x33, 0x31},
76 {0x0b, 0x33, 0x31},
77 {0x03, 0x33, 0x31},
78 {0x0b, 0x33, 0x31},
79 {0x03, 0x33, 0x31},
80 {0x0b, 0x33, 0x31},
81 {0x03, 0x33, 0x31},
82 {0x06, 0x66, 0x61}
83 };
84
85 static u8 al7230_init_table[CB_AL7230_INIT_SEQ][3] = {
86 {0x20, 0x37, 0x90},
87 {0x13, 0x33, 0x31},
88 {0x84, 0x1f, 0xf2},
89 {0x3f, 0xdf, 0xa3},
90 {0x7f, 0xd7, 0x84},
91 {0x80, 0x2b, 0x55},
92 {0x56, 0xaf, 0x36},
93 {0xce, 0x02, 0x07},
94 {0x6e, 0xbc, 0x98},
95 {0x22, 0x1b, 0xb9},
96 {0xe0, 0x00, 0x0a},
97 {0x08, 0x03, 0x1b},
98 {0x00, 0x0a, 0x3c},
99 {0xff, 0xff, 0xfd},
100 {0x00, 0x00, 0x0e},
101 {0x1a, 0xba, 0x8f}
102 };
103
104 static u8 al7230_init_table_amode[CB_AL7230_INIT_SEQ][3] = {
105 {0x2f, 0xf5, 0x20},
106 {0x00, 0x00, 0x01},
107 {0x45, 0x1f, 0xe2},
108 {0x5f, 0xdf, 0xa3},
109 {0x6f, 0xd7, 0x84},
110 {0x85, 0x3f, 0x55},
111 {0x56, 0xaf, 0x36},
112 {0xce, 0x02, 0x07},
113 {0x6e, 0xbc, 0x98},
114 {0x22, 0x1b, 0xb9},
115 {0xe0, 0x60, 0x0a},
116 {0x08, 0x03, 0x1b},
117 {0x00, 0x14, 0x7c},
118 {0xff, 0xff, 0xfd},
119 {0x00, 0x00, 0x0e},
120 {0x12, 0xba, 0xcf}
121 };
122
123 static u8 al7230_channel_table0[CB_MAX_CHANNEL][3] = {
124 {0x20, 0x37, 0x90},
125 {0x20, 0x37, 0x90},
126 {0x20, 0x37, 0x90},
127 {0x20, 0x37, 0x90},
128 {0x20, 0x37, 0xa0},
129 {0x20, 0x37, 0xa0},
130 {0x20, 0x37, 0xa0},
131 {0x20, 0x37, 0xa0},
132 {0x20, 0x37, 0xb0},
133 {0x20, 0x37, 0xb0},
134 {0x20, 0x37, 0xb0},
135 {0x20, 0x37, 0xb0},
136 {0x20, 0x37, 0xc0},
137 {0x20, 0x37, 0xc0},
138 {0x0f, 0xf5, 0x20}, /* channel 15 Tf = 4915MHz */
139 {0x2f, 0xf5, 0x20},
140 {0x0f, 0xf5, 0x20},
141 {0x0f, 0xf5, 0x20},
142 {0x2f, 0xf5, 0x20},
143 {0x0f, 0xf5, 0x20},
144 {0x2f, 0xf5, 0x30},
145 {0x2f, 0xf5, 0x30},
146 {0x0f, 0xf5, 0x40},
147 {0x2f, 0xf5, 0x40},
148 {0x0f, 0xf5, 0x40},
149 {0x0f, 0xf5, 0x40},
150 {0x2f, 0xf5, 0x40},
151 {0x2f, 0xf5, 0x50},
152 {0x2f, 0xf5, 0x60},
153 {0x2f, 0xf5, 0x60},
154 {0x2f, 0xf5, 0x70},
155 {0x2f, 0xf5, 0x70},
156 {0x2f, 0xf5, 0x70},
157 {0x2f, 0xf5, 0x70},
158 {0x2f, 0xf5, 0x70},
159 {0x2f, 0xf5, 0x70},
160 {0x2f, 0xf5, 0x80},
161 {0x2f, 0xf5, 0x80},
162 {0x2f, 0xf5, 0x80},
163 {0x2f, 0xf5, 0x90},
164 {0x2f, 0xf5, 0xc0},
165 {0x2f, 0xf5, 0xc0},
166 {0x2f, 0xf5, 0xc0},
167 {0x2f, 0xf5, 0xd0},
168 {0x2f, 0xf5, 0xd0},
169 {0x2f, 0xf5, 0xd0},
170 {0x2f, 0xf5, 0xe0},
171 {0x2f, 0xf5, 0xe0},
172 {0x2f, 0xf5, 0xe0},
173 {0x2f, 0xf5, 0xf0},
174 {0x2f, 0xf5, 0xf0},
175 {0x2f, 0xf6, 0x00},
176 {0x2f, 0xf6, 0x00},
177 {0x2f, 0xf6, 0x00},
178 {0x2f, 0xf6, 0x10},
179 {0x2f, 0xf6, 0x10}
180 };
181
182 static u8 al7230_channel_table1[CB_MAX_CHANNEL][3] = {
183 {0x13, 0x33, 0x31},
184 {0x1b, 0x33, 0x31},
185 {0x03, 0x33, 0x31},
186 {0x0b, 0x33, 0x31},
187 {0x13, 0x33, 0x31},
188 {0x1b, 0x33, 0x31},
189 {0x03, 0x33, 0x31},
190 {0x0b, 0x33, 0x31},
191 {0x13, 0x33, 0x31},
192 {0x1b, 0x33, 0x31},
193 {0x03, 0x33, 0x31},
194 {0x0b, 0x33, 0x31},
195 {0x13, 0x33, 0x31},
196 {0x06, 0x66, 0x61},
197 {0x1d, 0x55, 0x51}, /* channel = 15, Tf = 4915MHz */
198 {0x00, 0x00, 0x01},
199 {0x02, 0xaa, 0xa1},
200 {0x08, 0x00, 0x01},
201 {0x0a, 0xaa, 0xa1},
202 {0x0d, 0x55, 0x51},
203 {0x15, 0x55, 0x51},
204 {0x00, 0x00, 0x01},
205 {0x1d, 0x55, 0x51},
206 {0x00, 0x00, 0x01},
207 {0x02, 0xaa, 0xa1},
208 {0x08, 0x00, 0x01},
209 {0x0a, 0xaa, 0xa1},
210 {0x15, 0x55, 0x51},
211 {0x05, 0x55, 0x51},
212 {0x0a, 0xaa, 0xa1},
213 {0x10, 0x00, 0x01},
214 {0x15, 0x55, 0x51},
215 {0x1a, 0xaa, 0xa1},
216 {0x00, 0x00, 0x01},
217 {0x05, 0x55, 0x51},
218 {0x0a, 0xaa, 0xa1},
219 {0x15, 0x55, 0x51},
220 {0x00, 0x00, 0x01},
221 {0x0a, 0xaa, 0xa1},
222 {0x15, 0x55, 0x51},
223 {0x15, 0x55, 0x51},
224 {0x00, 0x00, 0x01},
225 {0x0a, 0xaa, 0xa1},
226 {0x15, 0x55, 0x51},
227 {0x00, 0x00, 0x01},
228 {0x0a, 0xaa, 0xa1},
229 {0x15, 0x55, 0x51},
230 {0x00, 0x00, 0x01},
231 {0x0a, 0xaa, 0xa1},
232 {0x15, 0x55, 0x51},
233 {0x00, 0x00, 0x01},
234 {0x18, 0x00, 0x01},
235 {0x02, 0xaa, 0xa1},
236 {0x0d, 0x55, 0x51},
237 {0x18, 0x00, 0x01},
238 {0x02, 0xaa, 0xb1}
239 };
240
241 static u8 al7230_channel_table2[CB_MAX_CHANNEL][3] = {
242 {0x7f, 0xd7, 0x84},
243 {0x7f, 0xd7, 0x84},
244 {0x7f, 0xd7, 0x84},
245 {0x7f, 0xd7, 0x84},
246 {0x7f, 0xd7, 0x84},
247 {0x7f, 0xd7, 0x84},
248 {0x7f, 0xd7, 0x84},
249 {0x7f, 0xd7, 0x84},
250 {0x7f, 0xd7, 0x84},
251 {0x7f, 0xd7, 0x84},
252 {0x7f, 0xd7, 0x84},
253 {0x7f, 0xd7, 0x84},
254 {0x7f, 0xd7, 0x84},
255 {0x7f, 0xd7, 0x84},
256 {0x7f, 0xd7, 0x84}, /* channel = 15 Tf = 4915MHz */
257 {0x6f, 0xd7, 0x84},
258 {0x7f, 0xd7, 0x84},
259 {0x7f, 0xd7, 0x84},
260 {0x7f, 0xd7, 0x84},
261 {0x7f, 0xd7, 0x84},
262 {0x7f, 0xd7, 0x84},
263 {0x6f, 0xd7, 0x84},
264 {0x7f, 0xd7, 0x84},
265 {0x6f, 0xd7, 0x84},
266 {0x7f, 0xd7, 0x84},
267 {0x7f, 0xd7, 0x84},
268 {0x7f, 0xd7, 0x84},
269 {0x7f, 0xd7, 0x84},
270 {0x7f, 0xd7, 0x84},
271 {0x7f, 0xd7, 0x84},
272 {0x7f, 0xd7, 0x84},
273 {0x7f, 0xd7, 0x84},
274 {0x7f, 0xd7, 0x84},
275 {0x6f, 0xd7, 0x84},
276 {0x7f, 0xd7, 0x84},
277 {0x7f, 0xd7, 0x84},
278 {0x7f, 0xd7, 0x84},
279 {0x6f, 0xd7, 0x84},
280 {0x7f, 0xd7, 0x84},
281 {0x7f, 0xd7, 0x84},
282 {0x7f, 0xd7, 0x84},
283 {0x6f, 0xd7, 0x84},
284 {0x7f, 0xd7, 0x84},
285 {0x7f, 0xd7, 0x84},
286 {0x6f, 0xd7, 0x84},
287 {0x7f, 0xd7, 0x84},
288 {0x7f, 0xd7, 0x84},
289 {0x6f, 0xd7, 0x84},
290 {0x7f, 0xd7, 0x84},
291 {0x7f, 0xd7, 0x84},
292 {0x6f, 0xd7, 0x84},
293 {0x7f, 0xd7, 0x84},
294 {0x7f, 0xd7, 0x84},
295 {0x7f, 0xd7, 0x84},
296 {0x7f, 0xd7, 0x84},
297 {0x7f, 0xd7, 0x84}
298 };
299
300 static u8 vt3226_init_table[CB_VT3226_INIT_SEQ][3] = {
301 {0x03, 0xff, 0x80},
302 {0x02, 0x82, 0xa1},
303 {0x03, 0xc6, 0xa2},
304 {0x01, 0x97, 0x93},
305 {0x03, 0x66, 0x64},
306 {0x00, 0x61, 0xa5},
307 {0x01, 0x7b, 0xd6},
308 {0x00, 0x80, 0x17},
309 {0x03, 0xf8, 0x08},
310 {0x00, 0x02, 0x39},
311 {0x02, 0x00, 0x2a}
312 };
313
314 static u8 vt3226d0_init_table[CB_VT3226_INIT_SEQ][3] = {
315 {0x03, 0xff, 0x80},
316 {0x03, 0x02, 0x21},
317 {0x03, 0xc6, 0xa2},
318 {0x01, 0x97, 0x93},
319 {0x03, 0x66, 0x64},
320 {0x00, 0x71, 0xa5},
321 {0x01, 0x15, 0xc6},
322 {0x01, 0x2e, 0x07},
323 {0x00, 0x58, 0x08},
324 {0x00, 0x02, 0x79},
325 {0x02, 0x01, 0xaa}
326 };
327
328 static u8 vt3226_channel_table0[CB_MAX_CHANNEL_24G][3] = {
329 {0x01, 0x97, 0x83},
330 {0x01, 0x97, 0x83},
331 {0x01, 0x97, 0x93},
332 {0x01, 0x97, 0x93},
333 {0x01, 0x97, 0x93},
334 {0x01, 0x97, 0x93},
335 {0x01, 0x97, 0xa3},
336 {0x01, 0x97, 0xa3},
337 {0x01, 0x97, 0xa3},
338 {0x01, 0x97, 0xa3},
339 {0x01, 0x97, 0xb3},
340 {0x01, 0x97, 0xb3},
341 {0x01, 0x97, 0xb3},
342 {0x03, 0x37, 0xc3}
343 };
344
345 static u8 vt3226_channel_table1[CB_MAX_CHANNEL_24G][3] = {
346 {0x02, 0x66, 0x64},
347 {0x03, 0x66, 0x64},
348 {0x00, 0x66, 0x64},
349 {0x01, 0x66, 0x64},
350 {0x02, 0x66, 0x64},
351 {0x03, 0x66, 0x64},
352 {0x00, 0x66, 0x64},
353 {0x01, 0x66, 0x64},
354 {0x02, 0x66, 0x64},
355 {0x03, 0x66, 0x64},
356 {0x00, 0x66, 0x64},
357 {0x01, 0x66, 0x64},
358 {0x02, 0x66, 0x64},
359 {0x00, 0xcc, 0xc4}
360 };
361
362 static const u32 vt3226d0_lo_current_table[CB_MAX_CHANNEL_24G] = {
363 0x0135c600,
364 0x0135c600,
365 0x0235c600,
366 0x0235c600,
367 0x0235c600,
368 0x0335c600,
369 0x0335c600,
370 0x0335c600,
371 0x0335c600,
372 0x0335c600,
373 0x0335c600,
374 0x0335c600,
375 0x0335c600,
376 0x0135c600
377 };
378
379 static u8 vt3342a0_init_table[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */
380 {0x03, 0xff, 0x80},
381 {0x02, 0x08, 0x81},
382 {0x00, 0xc6, 0x02},
383 {0x03, 0xc5, 0x13},
384 {0x00, 0xee, 0xe4},
385 {0x00, 0x71, 0xa5},
386 {0x01, 0x75, 0x46},
387 {0x01, 0x40, 0x27},
388 {0x01, 0x54, 0x08},
389 {0x00, 0x01, 0x69},
390 {0x02, 0x00, 0xaa},
391 {0x00, 0x08, 0xcb},
392 {0x01, 0x70, 0x0c}
393 };
394
395 static u8 vt3342_channel_table0[CB_MAX_CHANNEL][3] = {
396 {0x02, 0x05, 0x03},
397 {0x01, 0x15, 0x03},
398 {0x03, 0xc5, 0x03},
399 {0x02, 0x65, 0x03},
400 {0x01, 0x15, 0x13},
401 {0x03, 0xc5, 0x13},
402 {0x02, 0x05, 0x13},
403 {0x01, 0x15, 0x13},
404 {0x03, 0xc5, 0x13},
405 {0x02, 0x65, 0x13},
406 {0x01, 0x15, 0x23},
407 {0x03, 0xc5, 0x23},
408 {0x02, 0x05, 0x23},
409 {0x00, 0xd5, 0x23},
410 {0x01, 0x15, 0x13}, /* channel = 15 Tf = 4915MHz */
411 {0x01, 0x15, 0x13},
412 {0x01, 0x15, 0x13},
413 {0x01, 0x15, 0x13},
414 {0x01, 0x15, 0x13},
415 {0x01, 0x15, 0x13},
416 {0x01, 0x15, 0x13},
417 {0x01, 0x15, 0x13},
418 {0x01, 0x15, 0x13},
419 {0x01, 0x15, 0x13},
420 {0x01, 0x15, 0x13},
421 {0x01, 0x15, 0x13},
422 {0x01, 0x15, 0x13},
423 {0x01, 0x15, 0x13},
424 {0x01, 0x15, 0x13},
425 {0x01, 0x55, 0x63},
426 {0x01, 0x55, 0x63},
427 {0x02, 0xa5, 0x63},
428 {0x02, 0xa5, 0x63},
429 {0x00, 0x05, 0x73},
430 {0x00, 0x05, 0x73},
431 {0x01, 0x55, 0x73},
432 {0x02, 0xa5, 0x73},
433 {0x00, 0x05, 0x83},
434 {0x01, 0x55, 0x83},
435 {0x02, 0xa5, 0x83},
436 {0x02, 0xa5, 0x83},
437 {0x02, 0xa5, 0x83},
438 {0x02, 0xa5, 0x83},
439 {0x02, 0xa5, 0x83},
440 {0x02, 0xa5, 0x83},
441 {0x02, 0xa5, 0x83},
442 {0x02, 0xa5, 0x83},
443 {0x02, 0xa5, 0x83},
444 {0x02, 0xa5, 0x83},
445 {0x02, 0xa5, 0x83},
446 {0x02, 0xa5, 0x83},
447 {0x00, 0x05, 0xF3},
448 {0x01, 0x56, 0x03},
449 {0x02, 0xa6, 0x03},
450 {0x00, 0x06, 0x03},
451 {0x00, 0x06, 0x03}
452 };
453
454 static u8 vt3342_channel_table1[CB_MAX_CHANNEL][3] = {
455 {0x01, 0x99, 0x94},
456 {0x02, 0x44, 0x44},
457 {0x02, 0xee, 0xe4},
458 {0x03, 0x99, 0x94},
459 {0x00, 0x44, 0x44},
460 {0x00, 0xee, 0xe4},
461 {0x01, 0x99, 0x94},
462 {0x02, 0x44, 0x44},
463 {0x02, 0xee, 0xe4},
464 {0x03, 0x99, 0x94},
465 {0x00, 0x44, 0x44},
466 {0x00, 0xee, 0xe4},
467 {0x01, 0x99, 0x94},
468 {0x03, 0x33, 0x34},
469 {0x00, 0x44, 0x44}, /* channel = 15 Tf = 4915MHz */
470 {0x00, 0x44, 0x44},
471 {0x00, 0x44, 0x44},
472 {0x00, 0x44, 0x44},
473 {0x00, 0x44, 0x44},
474 {0x00, 0x44, 0x44},
475 {0x00, 0x44, 0x44},
476 {0x00, 0x44, 0x44},
477 {0x00, 0x44, 0x44},
478 {0x00, 0x44, 0x44},
479 {0x00, 0x44, 0x44},
480 {0x00, 0x44, 0x44},
481 {0x00, 0x44, 0x44},
482 {0x00, 0x44, 0x44},
483 {0x00, 0x44, 0x44},
484 {0x01, 0x55, 0x54},
485 {0x01, 0x55, 0x54},
486 {0x02, 0xaa, 0xa4},
487 {0x02, 0xaa, 0xa4},
488 {0x00, 0x00, 0x04},
489 {0x00, 0x00, 0x04},
490 {0x01, 0x55, 0x54},
491 {0x02, 0xaa, 0xa4},
492 {0x00, 0x00, 0x04},
493 {0x01, 0x55, 0x54},
494 {0x02, 0xaa, 0xa4},
495 {0x02, 0xaa, 0xa4},
496 {0x02, 0xaa, 0xa4},
497 {0x02, 0xaa, 0xa4},
498 {0x02, 0xaa, 0xa4},
499 {0x02, 0xaa, 0xa4},
500 {0x02, 0xaa, 0xa4},
501 {0x02, 0xaa, 0xa4},
502 {0x02, 0xaa, 0xa4},
503 {0x02, 0xaa, 0xa4},
504 {0x02, 0xaa, 0xa4},
505 {0x02, 0xaa, 0xa4},
506 {0x03, 0x00, 0x04},
507 {0x00, 0x55, 0x54},
508 {0x01, 0xaa, 0xa4},
509 {0x03, 0x00, 0x04},
510 {0x03, 0x00, 0x04}
511 };
512
513 enum {
514 VNT_TABLE_INIT = 0,
515 VNT_TABLE_INIT_2 = 0,
516 VNT_TABLE_0 = 1,
517 VNT_TABLE_1 = 2,
518 VNT_TABLE_2 = 1
519 };
520
521 struct vnt_table_info {
522 u8 *addr;
523 int length;
524 };
525
526 static const struct vnt_table_info vnt_table_seq[][3] = {
527 { /* RF_AL2230, RF_AL2230S init table, channel table 0 and 1 */
528 {&al2230_init_table[0][0], CB_AL2230_INIT_SEQ * 3},
529 {&al2230_channel_table0[0][0], CB_MAX_CHANNEL_24G * 3},
530 {&al2230_channel_table1[0][0], CB_MAX_CHANNEL_24G * 3}
531 }, { /* RF_AIROHA7230 init table, channel table 0 and 1 */
532 {&al7230_init_table[0][0], CB_AL7230_INIT_SEQ * 3},
533 {&al7230_channel_table0[0][0], CB_MAX_CHANNEL * 3},
534 {&al7230_channel_table1[0][0], CB_MAX_CHANNEL * 3}
535 }, { /* RF_VT3226 init table, channel table 0 and 1 */
536 {&vt3226_init_table[0][0], CB_VT3226_INIT_SEQ * 3},
537 {&vt3226_channel_table0[0][0], CB_MAX_CHANNEL_24G * 3},
538 {&vt3226_channel_table1[0][0], CB_MAX_CHANNEL_24G * 3}
539 }, { /* RF_VT3226D0 init table, channel table 0 and 1 */
540 {&vt3226d0_init_table[0][0], CB_VT3226_INIT_SEQ * 3},
541 {&vt3226_channel_table0[0][0], CB_MAX_CHANNEL_24G * 3},
542 {&vt3226_channel_table1[0][0], CB_MAX_CHANNEL_24G * 3}
543 }, { /* RF_VT3342A0 init table, channel table 0 and 1 */
544 {&vt3342a0_init_table[0][0], CB_VT3342_INIT_SEQ * 3},
545 {&vt3342_channel_table0[0][0], CB_MAX_CHANNEL * 3},
546 {&vt3342_channel_table1[0][0], CB_MAX_CHANNEL * 3}
547 }, { /* RF_AIROHA7230 init table 2 and channel table 2 */
548 {&al7230_init_table_amode[0][0], CB_AL7230_INIT_SEQ * 3},
549 {&al7230_channel_table2[0][0], CB_MAX_CHANNEL * 3},
550 {NULL, 0}
551 }
552 };
553
554 /*
555 * Description: Write to IF/RF, by embedded programming
556 */
vnt_rf_write_embedded(struct vnt_private * priv,u32 data)557 int vnt_rf_write_embedded(struct vnt_private *priv, u32 data)
558 {
559 u8 reg_data[4];
560
561 data |= (VNT_RF_REG_LEN << 3) | IFREGCTL_REGW;
562
563 reg_data[0] = (u8)data;
564 reg_data[1] = (u8)(data >> 8);
565 reg_data[2] = (u8)(data >> 16);
566 reg_data[3] = (u8)(data >> 24);
567
568 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_IFRF, 0, 0,
569 ARRAY_SIZE(reg_data), reg_data);
570 }
571
vnt_rf_addpower(struct vnt_private * priv)572 static u8 vnt_rf_addpower(struct vnt_private *priv)
573 {
574 int base;
575 s32 rssi = -priv->current_rssi;
576
577 if (!rssi)
578 return 7;
579
580 if (priv->rf_type == RF_VT3226D0)
581 base = -60;
582 else
583 base = -70;
584
585 if (rssi < base)
586 return ((rssi - base + 1) / -5) * 2 + 5;
587
588 return 0;
589 }
590
591 /* Set Tx power by power level and rate */
vnt_rf_set_txpower(struct vnt_private * priv,u8 power,struct ieee80211_channel * ch)592 static int vnt_rf_set_txpower(struct vnt_private *priv, u8 power,
593 struct ieee80211_channel *ch)
594 {
595 u32 power_setting = 0;
596 int ret = 0;
597
598 power += vnt_rf_addpower(priv);
599 if (power > VNT_RF_MAX_POWER)
600 power = VNT_RF_MAX_POWER;
601
602 if (priv->power == power)
603 return 0;
604
605 priv->power = power;
606
607 switch (priv->rf_type) {
608 case RF_AL2230:
609 power_setting = 0x0404090 | (power << 12);
610
611 ret = vnt_rf_write_embedded(priv, power_setting);
612 if (ret)
613 return ret;
614
615 if (ch->flags & IEEE80211_CHAN_NO_OFDM)
616 ret = vnt_rf_write_embedded(priv, 0x0001b400);
617 else
618 ret = vnt_rf_write_embedded(priv, 0x0005a400);
619
620 break;
621 case RF_AL2230S:
622 power_setting = 0x0404090 | (power << 12);
623
624 ret = vnt_rf_write_embedded(priv, power_setting);
625 if (ret)
626 return ret;
627
628 if (ch->flags & IEEE80211_CHAN_NO_OFDM) {
629 ret = vnt_rf_write_embedded(priv, 0x040c1400);
630 if (ret)
631 return ret;
632
633 ret = vnt_rf_write_embedded(priv, 0x00299b00);
634 } else {
635 ret = vnt_rf_write_embedded(priv, 0x0005a400);
636 if (ret)
637 return ret;
638
639 ret = vnt_rf_write_embedded(priv, 0x00099b00);
640 }
641
642 break;
643
644 case RF_AIROHA7230:
645 if (ch->flags & IEEE80211_CHAN_NO_OFDM)
646 ret = vnt_rf_write_embedded(priv, 0x111bb900);
647 else
648 ret = vnt_rf_write_embedded(priv, 0x221bb900);
649
650 if (ret)
651 return ret;
652
653 /*
654 * 0x080F1B00 for 3 wire control TxGain(D10)
655 * and 0x31 as TX Gain value
656 */
657 power_setting = 0x080c0b00 | (power << 12);
658
659 ret = vnt_rf_write_embedded(priv, power_setting);
660 break;
661
662 case RF_VT3226:
663 power_setting = ((0x3f - power) << 20) | (0x17 << 8);
664
665 ret = vnt_rf_write_embedded(priv, power_setting);
666 break;
667 case RF_VT3226D0:
668 if (ch->flags & IEEE80211_CHAN_NO_OFDM) {
669 u16 hw_value = ch->hw_value;
670
671 power_setting = ((0x3f - power) << 20) | (0xe07 << 8);
672
673 ret = vnt_rf_write_embedded(priv, power_setting);
674 if (ret)
675 return ret;
676
677 ret = vnt_rf_write_embedded(priv, 0x03c6a200);
678 if (ret)
679 return ret;
680
681 dev_dbg(&priv->usb->dev,
682 "%s 11b channel [%d]\n", __func__, hw_value);
683
684 hw_value--;
685
686 if (hw_value < ARRAY_SIZE(vt3226d0_lo_current_table)) {
687 ret = vnt_rf_write_embedded(priv,
688 vt3226d0_lo_current_table[hw_value]);
689 if (ret)
690 return ret;
691 }
692
693 ret = vnt_rf_write_embedded(priv, 0x015C0800);
694 } else {
695 dev_dbg(&priv->usb->dev,
696 "@@@@ %s> 11G mode\n", __func__);
697
698 power_setting = ((0x3f - power) << 20) | (0x7 << 8);
699
700 ret = vnt_rf_write_embedded(priv, power_setting);
701 if (ret)
702 return ret;
703
704 ret = vnt_rf_write_embedded(priv, 0x00C6A200);
705 if (ret)
706 return ret;
707
708 ret = vnt_rf_write_embedded(priv, 0x016BC600);
709 if (ret)
710 return ret;
711
712 ret = vnt_rf_write_embedded(priv, 0x00900800);
713 }
714
715 break;
716
717 case RF_VT3342A0:
718 power_setting = ((0x3f - power) << 20) | (0x27 << 8);
719
720 ret = vnt_rf_write_embedded(priv, power_setting);
721 break;
722 default:
723 break;
724 }
725 return ret;
726 }
727
728 /* Set Tx power by channel number type */
vnt_rf_setpower(struct vnt_private * priv,struct ieee80211_channel * ch)729 int vnt_rf_setpower(struct vnt_private *priv,
730 struct ieee80211_channel *ch)
731 {
732 u16 channel;
733 u8 power = priv->cck_pwr;
734
735 if (!ch)
736 return -EINVAL;
737
738 /* set channel number to array number */
739 channel = ch->hw_value - 1;
740
741 if (ch->flags & IEEE80211_CHAN_NO_OFDM) {
742 if (channel < ARRAY_SIZE(priv->cck_pwr_tbl))
743 power = priv->cck_pwr_tbl[channel];
744 } else if (ch->band == NL80211_BAND_5GHZ) {
745 /* remove 14 channels to array size */
746 channel -= 14;
747
748 if (channel < ARRAY_SIZE(priv->ofdm_a_pwr_tbl))
749 power = priv->ofdm_a_pwr_tbl[channel];
750 } else {
751 if (channel < ARRAY_SIZE(priv->ofdm_pwr_tbl))
752 power = priv->ofdm_pwr_tbl[channel];
753 }
754
755 return vnt_rf_set_txpower(priv, power, ch);
756 }
757
758 /* Convert rssi to dbm */
vnt_rf_rssi_to_dbm(struct vnt_private * priv,u8 rssi,long * dbm)759 void vnt_rf_rssi_to_dbm(struct vnt_private *priv, u8 rssi, long *dbm)
760 {
761 u8 idx = ((rssi & 0xc0) >> 6) & 0x03;
762 long b = rssi & 0x3f;
763 long a = 0;
764 u8 airoharf[4] = {0, 18, 0, 40};
765
766 switch (priv->rf_type) {
767 case RF_AL2230:
768 case RF_AL2230S:
769 case RF_AIROHA7230:
770 case RF_VT3226:
771 case RF_VT3226D0:
772 case RF_VT3342A0:
773 a = airoharf[idx];
774 break;
775 default:
776 break;
777 }
778
779 *dbm = -1 * (a + b * 2);
780 }
781
vnt_rf_table_download(struct vnt_private * priv)782 int vnt_rf_table_download(struct vnt_private *priv)
783 {
784 int ret;
785 int idx = -1;
786 const struct vnt_table_info *table_seq;
787
788 switch (priv->rf_type) {
789 case RF_AL2230:
790 case RF_AL2230S:
791 idx = 0;
792 break;
793 case RF_AIROHA7230:
794 idx = 1;
795 break;
796 case RF_VT3226:
797 idx = 2;
798 break;
799 case RF_VT3226D0:
800 idx = 3;
801 break;
802 case RF_VT3342A0:
803 idx = 4;
804 break;
805 }
806
807 if (idx < 0)
808 return 0;
809
810 table_seq = &vnt_table_seq[idx][0];
811
812 /* Init Table */
813 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
814 MESSAGE_REQUEST_RF_INIT,
815 table_seq[VNT_TABLE_INIT].length,
816 table_seq[VNT_TABLE_INIT].addr);
817 if (ret)
818 return ret;
819
820 /* Channel Table 0 */
821 ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE,
822 MESSAGE_REQUEST_RF_CH0,
823 table_seq[VNT_TABLE_0].length,
824 table_seq[VNT_TABLE_0].addr);
825 if (ret)
826 return ret;
827
828 /* Channel Table 1 */
829 ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE,
830 MESSAGE_REQUEST_RF_CH1,
831 table_seq[VNT_TABLE_1].length,
832 table_seq[VNT_TABLE_1].addr);
833
834 if (priv->rf_type == RF_AIROHA7230) {
835 table_seq = &vnt_table_seq[5][0];
836
837 /* Init Table 2 */
838 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
839 MESSAGE_REQUEST_RF_INIT2,
840 table_seq[VNT_TABLE_INIT_2].length,
841 table_seq[VNT_TABLE_INIT_2].addr);
842 if (ret)
843 return ret;
844
845 /* Channel Table 2 */
846 ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE,
847 MESSAGE_REQUEST_RF_CH2,
848 table_seq[VNT_TABLE_2].length,
849 table_seq[VNT_TABLE_2].addr);
850 }
851
852 return ret;
853 }
854