1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
4  *
5  */
6 
7 #ifndef __JR_H
8 #define __JR_H
9 
10 #include <linux/compiler.h>
11 
12 #define JR_SIZE 4
13 /* Timeout currently defined as 90 sec */
14 #define CONFIG_SEC_DEQ_TIMEOUT	90000000U
15 
16 #define DEFAULT_JR_ID		0
17 #define DEFAULT_JR_LIODN	0
18 #define DEFAULT_IRQ		0	/* Interrupts not to be configured */
19 
20 #define MCFGR_SWRST       ((uint32_t)(1)<<31) /* Software Reset */
21 #define MCFGR_DMA_RST     ((uint32_t)(1)<<28) /* DMA Reset */
22 #define MCFGR_PS_SHIFT          16
23 #define MCFGR_AWCACHE_SHIFT	8
24 #define MCFGR_AWCACHE_MASK	(0xf << MCFGR_AWCACHE_SHIFT)
25 #define MCFGR_ARCACHE_SHIFT	12
26 #define MCFGR_ARCACHE_MASK	(0xf << MCFGR_ARCACHE_SHIFT)
27 
28 #define JR_INTMASK	  0x00000001
29 #define JRCR_RESET                  0x01
30 #define JRINT_ERR_HALT_INPROGRESS   0x4
31 #define JRINT_ERR_HALT_MASK         0xc
32 #define JRNSLIODN_SHIFT		16
33 #define JRNSLIODN_MASK		0x0fff0000
34 #define JRSLIODN_SHIFT		0
35 #define JRSLIODN_MASK		0x00000fff
36 
37 #define JQ_DEQ_ERR		-1
38 #define JQ_DEQ_TO_ERR		-2
39 #define JQ_ENQ_ERR		-3
40 
41 #define RNG4_MAX_HANDLES	2
42 
43 struct op_ring {
44 	phys_addr_t desc;
45 	uint32_t status;
46 } __packed;
47 
48 struct jr_info {
49 	void (*callback)(uint32_t status, void *arg);
50 	phys_addr_t desc_phys_addr;
51 	uint32_t desc_len;
52 	uint32_t op_done;
53 	void *arg;
54 };
55 
56 struct jobring {
57 	int jq_id;
58 	int irq;
59 	int liodn;
60 	/* Head is the index where software would enq the descriptor in
61 	 * the i/p ring
62 	 */
63 	int head;
64 	/* Tail index would be used by s/w ehile enqueuing to determine if
65 	 * there is any space left in the s/w maintained i/p rings
66 	 */
67 	/* Also in case of deq tail will be incremented only in case of
68 	 * in-order job completion
69 	 */
70 	int tail;
71 	/* Read index of the output ring. It may not match with tail in case
72 	 * of out of order completetion
73 	 */
74 	int read_idx;
75 	/* Write index to input ring. Would be always equal to head */
76 	int write_idx;
77 	/* Size of the rings. */
78 	int size;
79 	/* Op ring size aligned to cache line size */
80 	int op_size;
81 	/* The ip and output rings have to be accessed by SEC. So the
82 	 * pointers will ahve to point to the housekeeping region provided
83 	 * by SEC
84 	 */
85 	/*Circular  Ring of i/p descriptors */
86 	dma_addr_t *input_ring;
87 	/* Circular Ring of o/p descriptors */
88 	/* Circula Ring containing info regarding descriptors in i/p
89 	 * and o/p ring
90 	 */
91 	/* This ring can be on the stack */
92 	struct jr_info info[JR_SIZE];
93 	struct op_ring *output_ring;
94 	/* Offset in CCSR to the SEC engine to which this JR belongs */
95 	uint32_t sec_offset;
96 
97 };
98 
99 struct result {
100 	int done;
101 	uint32_t status;
102 };
103 
104 void caam_jr_strstatus(u32 status);
105 int run_descriptor_jr(uint32_t *desc);
106 
107 #endif
108