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/linux/tools/lib/bpf/
A Dbpf_tracing.h74 #define PT_REGS_RET(x) ((x)->sp) argument
75 #define PT_REGS_FP(x) ((x)->bp) argument
76 #define PT_REGS_RC(x) ((x)->ax) argument
77 #define PT_REGS_SP(x) ((x)->sp) argument
78 #define PT_REGS_IP(x) ((x)->ip) argument
98 #define PT_REGS_PARM4(x) 0 argument
99 #define PT_REGS_PARM5(x) 0 argument
101 #define PT_REGS_FP(x) ((x)->ebp) argument
102 #define PT_REGS_RC(x) ((x)->eax) argument
109 #define PT_REGS_PARM4_CORE(x) 0 argument
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A Dbpf_endian.h64 # define __bpf_ntohs(x) (x) argument
65 # define __bpf_htons(x) (x) argument
68 # define __bpf_ntohl(x) (x) argument
69 # define __bpf_htonl(x) (x) argument
72 # define __bpf_be64_to_cpu(x) (x) argument
80 #define bpf_htons(x) \ argument
83 #define bpf_ntohs(x) \ argument
86 #define bpf_htonl(x) \ argument
89 #define bpf_ntohl(x) \ argument
92 #define bpf_cpu_to_be64(x) \ argument
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/linux/drivers/gpu/drm/radeon/
A Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
656 #define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0) argument
657 #define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4) argument
658 #define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8) argument
659 #define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12) argument
660 #define POWER_D1_SCLK_HILEN(x) ((x) << 16) argument
661 #define POWER_D1_SCLK_LOLEN(x) ((x) << 20) argument
662 #define STATIC_SCREEN_HILEN(x) ((x) << 24) argument
663 #define STATIC_SCREEN_LOLEN(x) ((x) << 28) argument
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A Dr100d.h69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
848 #define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17) argument
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A Dr420d.h32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
49 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
50 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
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A Drs690d.h34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
55 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
56 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
58 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
59 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
61 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
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A Dr300d.h84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
92 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
93 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
95 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
96 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
98 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
99 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
101 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
102 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
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A Drs400d.h33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
50 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
51 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
53 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
54 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
56 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
57 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
59 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) argument
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A Dr520d.h41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
50 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
51 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
53 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) argument
54 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) argument
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A Drv250d.h32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) argument
33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) argument
35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) argument
36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) argument
38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) argument
39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) argument
41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) argument
42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) argument
44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) argument
45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) argument
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A Drv515d.h210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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/linux/drivers/phy/microchip/
A Dsparx5_serdes_regs.h56 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ argument
941 #define SD10G_LANE_LANE_DF_LOL_SET(x)\ argument
943 #define SD10G_LANE_LANE_DF_LOL_GET(x)\ argument
2093 #define SD6G_LANE_LANE_DF_LOL_SET(x)\ argument
2095 #define SD6G_LANE_LANE_DF_LOL_GET(x)\ argument
2288 #define SD_CMU_CMU_45_RESERVED_SET(x)\ argument
2290 #define SD_CMU_CMU_45_RESERVED_GET(x)\ argument
2456 #define SD_LANE_MISC_RX_ENA_SET(x)\ argument
2458 #define SD_LANE_MISC_RX_ENA_GET(x)\ argument
2462 #define SD_LANE_MISC_MUX_ENA_SET(x)\ argument
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/linux/drivers/staging/media/hantro/
A Drockchip_vpu2_regs.h14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
129 #define VEPU_REG_CHECKPOINT_RESULT(x) \ argument
198 #define VEPU_REG_IDR_PIC_ID(x) (((x) & 0xf) << 1) argument
257 #define VEPU_REG_MB_WIDTH(x) (((x) & 0x1ff) << 8) argument
280 #define VEPU_REG_PPS_ID(x) (((x) & 0xff) << 24) argument
320 #define VDPU_REG_CONFIG_TILED_MODE_MSB(x) BIT(0) argument
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A Dhantro_g1_regs.h28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) argument
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11) argument
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5) argument
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) argument
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) argument
101 #define G1_REG_DEC_CTRL2_MVTAB(x) (((x) & 0x7) << 7) argument
102 #define G1_REG_DEC_CTRL2_CBPTAB(x) (((x) & 0x7) << 4) argument
111 #define G1_REG_DEC_CTRL2_JPEG_MODE(x) (((x) & 0x7) << 8) argument
146 #define G1_REG_DEC_CTRL4_DQ_EDGES(x) (((x) & 0xf) << 20) argument
153 #define G1_REG_DEC_CTRL4_TTFRM(x) (((x) & 0x3) << 8) argument
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/linux/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_main_regs.h60 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument
2903 #define FDMA_CTRL_NRESET_SET(x)\ argument
2905 #define FDMA_CTRL_NRESET_GET(x)\ argument
2930 #define GCB_CHIP_ID_ONE_SET(x)\ argument
2932 #define GCB_CHIP_ID_ONE_GET(x)\ argument
4319 #define QS_INJ_CTRL_EOF_SET(x)\ argument
4321 #define QS_INJ_CTRL_EOF_GET(x)\ argument
4325 #define QS_INJ_CTRL_SOF_SET(x)\ argument
4327 #define QS_INJ_CTRL_SOF_GET(x)\ argument
4388 #define QSYS_ATOP_ATOP_SET(x)\ argument
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/linux/include/soc/mscc/
A Docelot_ana.h19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) argument
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) argument
64 #define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0)) argument
76 #define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0)) argument
99 #define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0)) argument
108 #define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0)) argument
116 #define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0)) argument
130 #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0)) argument
144 #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0)) argument
162 #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0)) argument
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A Docelot_qsys.h28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) argument
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) argument
47 #define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0)) argument
59 #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0)) argument
67 #define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0)) argument
74 #define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(x) ((x) & GENMASK(15, 0)) argument
80 #define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0)) argument
101 #define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0)) argument
118 #define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0)) argument
183 #define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0)) argument
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A Docelot_hsio.h106 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
166 #define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0)) argument
172 #define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0)) argument
178 #define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0)) argument
194 #define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
228 #define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0)) argument
253 #define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0)) argument
258 #define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0)) argument
310 #define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) argument
327 #define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) argument
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/linux/arch/arm/include/asm/
A Dopcodes.h24 #define ___asm_opcode_swab32(x) ( \ argument
30 #define ___asm_opcode_swab16(x) ( \ argument
34 #define ___asm_opcode_swahb32(x) ( \ argument
38 #define ___asm_opcode_swahw32(x) ( \ argument
88 #define ___opcode_swab32(x) swab32(x) argument
89 #define ___opcode_swab16(x) swab16(x) argument
90 #define ___opcode_swahb32(x) swahb32(x) argument
91 #define ___opcode_swahw32(x) swahw32(x) argument
139 #define __opcode_is_thumb32(x) ( \ argument
223 #define ___inst_arm(x) .long x argument
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/linux/drivers/net/ethernet/chelsio/cxgb/
A Dregs.h206 #define V_DAY(x) ((x) << S_DAY) argument
211 #define V_MONTH(x) ((x) << S_MONTH) argument
261 #define V_READY(x) ((x) << S_READY) argument
313 #define V_BANKS(x) ((x) << S_BANKS) argument
337 #define V_BUSY(x) ((x) << S_BUSY) argument
468 #define V_OP(x) ((x) << S_OP) argument
854 #define V_SACK(x) ((x) << S_SACK) argument
859 #define V_ECN(x) ((x) << S_ECN) argument
868 #define V_MSS(x) ((x) << S_MSS) argument
1052 #define V_2MSL(x) ((x) << S_2MSL) argument
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/linux/drivers/net/ethernet/chelsio/cxgb3/
A Dsge_defs.h11 #define V_EC_CREDITS(x) ((x) << S_EC_CREDITS) argument
15 #define V_EC_GTS(x) ((x) << S_EC_GTS) argument
20 #define V_EC_INDEX(x) ((x) << S_EC_INDEX) argument
25 #define V_EC_SIZE(x) ((x) << S_EC_SIZE) argument
45 #define V_EC_TYPE(x) ((x) << S_EC_TYPE) argument
49 #define V_EC_GEN(x) ((x) << S_EC_GEN) argument
71 #define V_RQ_GEN(x) ((x) << S_RQ_GEN) argument
107 #define V_CQ_GEN(x) ((x) << S_CQ_GEN) argument
111 #define V_CQ_ERR(x) ((x) << S_CQ_ERR) argument
149 #define V_FL_GEN(x) ((x) << S_FL_GEN) argument
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/linux/include/uapi/linux/byteorder/
A Dbig_endian.h16 #define __constant_htonl(x) ((__force __be32)(__u32)(x)) argument
17 #define __constant_ntohl(x) ((__force __u32)(__be32)(x)) argument
18 #define __constant_htons(x) ((__force __be16)(__u16)(x)) argument
19 #define __constant_ntohs(x) ((__force __u16)(__be16)(x)) argument
38 #define __cpu_to_be64(x) ((__force __be64)(__u64)(x)) argument
93 #define __cpu_to_le64s(x) __swab64s((x)) argument
94 #define __le64_to_cpus(x) __swab64s((x)) argument
95 #define __cpu_to_le32s(x) __swab32s((x)) argument
96 #define __le32_to_cpus(x) __swab32s((x)) argument
97 #define __cpu_to_le16s(x) __swab16s((x)) argument
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A Dlittle_endian.h32 #define __cpu_to_le64(x) ((__force __le64)(__u64)(x)) argument
33 #define __le64_to_cpu(x) ((__force __u64)(__le64)(x)) argument
34 #define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) argument
35 #define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) argument
36 #define __cpu_to_le16(x) ((__force __le16)(__u16)(x)) argument
99 #define __cpu_to_be64s(x) __swab64s((x)) argument
100 #define __be64_to_cpus(x) __swab64s((x)) argument
101 #define __cpu_to_be32s(x) __swab32s((x)) argument
102 #define __be32_to_cpus(x) __swab32s((x)) argument
103 #define __cpu_to_be16s(x) __swab16s((x)) argument
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/linux/arch/mips/include/asm/sibyte/
A Dbcm1480_mc.h31 #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) argument
37 #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) argument
43 #define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) argument
120 #define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) argument
125 #define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) argument
130 #define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) argument
373 #define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) argument
715 #define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL) argument
724 #define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR) argument
738 #define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP) argument
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A Dsb1250_genbus.h191 #define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0) argument
196 #define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A) argument
201 #define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B) argument
206 #define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C) argument
211 #define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D) argument
220 #define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E) argument
225 #define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F) argument
230 #define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1) argument
235 #define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G) argument
240 #define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2) argument
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