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/u-boot/include/synopsys/
A Ddwcddr21mctl.h47 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument
50 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument
51 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument
52 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument
58 #define DWCDDR21MCTL_CCR_IB(x) ((x) << 29) argument
59 #define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30) argument
60 #define DWCDDR21MCTL_CCR_IT(x) ((x) << 31) argument
65 #define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0) argument
69 #define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9) argument
264 #define DWCDDR21MCTL_MR_BT(x) ((x) << 3) argument
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/u-boot/board/samsung/odroid/
A Dsetup.h11 #define SDIV(x) ((x) & 0x7) argument
81 #define MUX_C2C_SEL(x) ((x) & 0x1) argument
91 #define C2C_SEL(x) (((x)) & 0x7) argument
109 #define ACP_RATIO(x) ((x) & 0x7) argument
117 #define DIV_ACP(x) ((x) & 0x1) argument
159 #define UART0_SEL(x) ((x) & 0xf) argument
173 #define DIV_UART0(x) ((x) & 0x1) argument
182 #define MMC0_RATIO(x) ((x) & 0xf) argument
188 #define DIV_MMC0(x) ((x) & 1) argument
205 #define DIV_MMC2(x) ((x) & 0x1) argument
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/u-boot/include/andestech/
A Dandes_pcu.h100 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument
107 #define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) argument
126 #define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) argument
127 #define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) argument
129 #define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) argument
132 #define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) argument
133 #define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) argument
134 #define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) argument
135 #define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) argument
137 #define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) argument
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/u-boot/arch/arm/include/asm/
A Dopcodes.h24 #define ___asm_opcode_swab32(x) ( \ argument
30 #define ___asm_opcode_swab16(x) ( \ argument
34 #define ___asm_opcode_swahb32(x) ( \ argument
38 #define ___asm_opcode_swahw32(x) ( \ argument
88 #define ___opcode_swab32(x) swab32(x) argument
89 #define ___opcode_swab16(x) swab16(x) argument
90 #define ___opcode_swahb32(x) swahb32(x) argument
134 #define __opcode_is_thumb32(x) ( \ argument
138 #define __opcode_is_thumb16(x) ( \ argument
218 #define ___inst_arm(x) .long x argument
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/u-boot/include/linux/byteorder/
A Dbig_endian.h16 #define __constant_htonl(x) ((__force __be32)(__u32)(x)) argument
17 #define __constant_ntohl(x) ((__force __u32)(__be32)(x)) argument
18 #define __constant_htons(x) ((__force __be16)(__u16)(x)) argument
19 #define __constant_ntohs(x) ((__force __u16)(__be16)(x)) argument
38 #define __cpu_to_be64(x) ((__force __be64)(__u64)(x)) argument
93 #define __cpu_to_le64s(x) __swab64s((x)) argument
94 #define __le64_to_cpus(x) __swab64s((x)) argument
95 #define __cpu_to_le32s(x) __swab32s((x)) argument
96 #define __le32_to_cpus(x) __swab32s((x)) argument
97 #define __cpu_to_le16s(x) __swab16s((x)) argument
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A Dlittle_endian.h32 #define __cpu_to_le64(x) ((__force __le64)(__u64)(x)) argument
33 #define __le64_to_cpu(x) ((__force __u64)(__le64)(x)) argument
34 #define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) argument
35 #define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) argument
36 #define __cpu_to_le16(x) ((__force __le16)(__u16)(x)) argument
99 #define __cpu_to_be64s(x) __swab64s((x)) argument
100 #define __be64_to_cpus(x) __swab64s((x)) argument
101 #define __cpu_to_be32s(x) __swab32s((x)) argument
102 #define __be32_to_cpus(x) __swab32s((x)) argument
103 #define __cpu_to_be16s(x) __swab16s((x)) argument
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A Dswab.h21 #define ___swab16(x) \ argument
25 #define ___swab32(x) \ argument
31 #define ___swab64(x) \ argument
46 # define __arch__swab16(x) ___swab16(x) argument
49 # define __arch__swab32(x) ___swab32(x) argument
80 # define __swab16(x) \ argument
84 # define __swab32(x) \ argument
88 # define __swab64(x) \ argument
93 # define __swab16(x) __fswab16(x) argument
94 # define __swab32(x) __fswab32(x) argument
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/u-boot/include/
A Dcompiler.h71 #define uswap_16(x) \ argument
74 #define uswap_32(x) \ argument
79 #define _uswap_64(x, sfx) \ argument
95 # define cpu_to_le16(x) (x) argument
96 # define cpu_to_le32(x) (x) argument
97 # define cpu_to_le64(x) (x) argument
98 # define le16_to_cpu(x) (x) argument
99 # define le32_to_cpu(x) (x) argument
100 # define le64_to_cpu(x) (x) argument
114 # define cpu_to_be16(x) (x) argument
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A Dimx_lpi2c.h114 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIF… argument
117 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIF… argument
126 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIF… argument
129 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIF… argument
134 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIF… argument
137 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIF… argument
140 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIF… argument
143 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIF… argument
146 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIF… argument
149 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIF… argument
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/u-boot/arch/arm/include/asm/arch-omap3/
A Domap3-regs.h23 #define CLKACTIVATIONTIME(x) (((x) & 3) << 25) argument
40 #define CSWROFFTIME(x) (((x) & 0x1f) << 16) argument
41 #define CSRDOFFTIME(x) (((x) & 0x1f) << 8) argument
43 #define CSONTIME(x) (((x) & 0xf) << 0) argument
46 #define ADVWROFFTIME(x) (((x) & 0x1f) << 16) argument
47 #define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) argument
49 #define ADVONTIME(x) (((x) & 0xf) << 0) argument
52 #define WEOFFTIME(x) (((x) & 0x1f) << 24) argument
54 #define WEONTIME(x) (((x) & 0xf) << 16) argument
55 #define OEOFFTIME(x) (((x) & 0x1f) << 8) argument
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/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) argument
45 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
65 #define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x)) argument
72 #define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x)) argument
74 #define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x)) argument
100 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
117 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) argument
143 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
163 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) argument
194 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) argument
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/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2_icpu_cfg.h11 #define ICPU_GPR(x) (0x4 * (x)) argument
49 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
69 #define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x)) argument
74 #define ICPU_TIMER_VALUE(x) (0x10c + 0x4 * (x)) argument
77 #define ICPU_TIMER_CTRL(x) (0x124 + 0x4 * (x)) argument
106 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
123 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) argument
154 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
174 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) argument
205 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) argument
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/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) argument
46 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
66 #define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x)) argument
71 #define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x)) argument
74 #define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x)) argument
103 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
120 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) argument
151 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
171 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) argument
202 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) argument
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/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) argument
41 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
61 #define ICPU_DST_INTR_MAP(x) (0x94 + 0x4 * (x)) argument
66 #define ICPU_TIMER_VALUE(x) (0xe4 + 0x4 * (x)) argument
69 #define ICPU_TIMER_CTRL(x) (0xfc + 0x4 * (x)) argument
98 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
115 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) argument
146 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
166 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) argument
197 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) argument
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/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) argument
36 #define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
45 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
89 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) argument
106 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) argument
132 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) argument
152 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) argument
166 #define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(x) ((x) & GENMASK(15, 0)) argument
183 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) argument
207 #define ICPU_MEMCTRL_DQS_DLY(x) (0x270) argument
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/u-boot/arch/arm/include/asm/arch-rockchip/
A Dvop_rk3288.h133 #define V_AUTO_GATING_EN(x) (((x) & 1) << 23) argument
134 #define V_STANDBY_EN(x) (((x) & 1) << 22) argument
135 #define V_DMA_STOP(x) (((x) & 1) << 21) argument
136 #define V_MMU_EN(x) (((x) & 1) << 20) argument
144 #define V_EDPI_HALT_EN(x) (((x)&1)<<8) argument
148 #define V_DIRECT_PATH_EN(x) ((x) & 1) argument
286 #define V_WIN0_EN(x) ((x) & 1) argument
364 #define V_VSYNC(x) (((x)&0x1fff)<<0) argument
365 #define V_VERPRD(x) (((x)&0x1fff)<<16) argument
369 #define V_VAEP(x) (((x)&0x1fff)<<0) argument
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/u-boot/drivers/ddr/altera/
A Dsdram_soc64.h93 #define CTRLCFG0_CFG_MEMTYPE(x) \ argument
95 #define CTRLCFG0_CFG_DIMM_TYPE(x) \ argument
97 #define CTRLCFG0_CFG_AC_POS(x) \ argument
104 #define CTRLCFG1_CFG_ADDR_ORDER(x) \ argument
106 #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ argument
109 #define DRAMTIMING0_CFG_TCL(x) \ argument
121 #define CALTIMING1_CFG_RD_TO_RD(x) \ argument
127 #define CALTIMING1_CFG_RD_TO_WR(x) \ argument
138 #define CALTIMING2_CFG_WR_TO_WR(x) \ argument
145 #define CALTIMING3_CFG_WR_TO_RD(x) \ argument
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/u-boot/arch/arm/mach-keystone/include/mach/
A Dpsc_defs.h23 #define PSC_REG_PDSTAT(x) (0x200 + (4 * (x))) argument
24 #define PSC_REG_PDCTL(x) (0x300 + (4 * (x))) argument
25 #define PSC_REG_MDCFG(x) (0x600 + (4 * (x))) argument
26 #define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) argument
27 #define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) argument
30 static inline u32 _boot_bit_mask(u32 x, u32 y) in _boot_bit_mask()
36 static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y) in boot_read_bitfield()
42 static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y) in boot_set_bitfield()
54 #define PSC_REG_PDSTAT_GET_STATE(x) boot_read_bitfield((x), 4, 0) argument
63 #define PSC_REG_MDCTL_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8) argument
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/u-boot/arch/arm/mach-s5pc1xx/include/mach/
A Dsromc.h15 #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) argument
16 #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ argument
18 #define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) argument
19 #define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) argument
21 #define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ argument
22 #define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ argument
23 #define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ argument
24 #define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ argument
25 #define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ argument
26 #define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ argument
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/u-boot/include/linux/
A Dbitrev.h21 static inline u16 __bitrev16(u16 x) in __bitrev16()
26 static inline u32 __bitrev32(u32 x) in __bitrev32()
33 #define __bitrev8x4(x) (__bitrev32(swab32(x))) argument
35 #define __constant_bitrev32(x) \ argument
46 #define __constant_bitrev16(x) \ argument
56 #define __constant_bitrev8x4(x) \ argument
65 #define __constant_bitrev8(x) \ argument
74 #define bitrev32(x) \ argument
82 #define bitrev16(x) \ argument
90 #define bitrev8x4(x) \ argument
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A Dcompletion.h34 #define init_completion_map(x, m) __init_completion(x) argument
35 #define init_completion(x) __init_completion(x) argument
36 static inline void complete_acquire(struct completion *x) {} in complete_acquire()
37 static inline void complete_release(struct completion *x) {} in complete_release()
88 static inline void __init_completion(struct completion *x) in __init_completion()
129 #define wait_for_completion(x) do {} while (0) argument
130 #define wait_for_completion_io(x) do {} while (0) argument
160 inline bool try_wait_for_completion(struct completion *x) in try_wait_for_completion()
164 inline bool completion_done(struct completion *x) in completion_done()
169 #define complete(x) do {} while (0) argument
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/u-boot/arch/m68k/include/asm/coldfire/
A Dlcd.h54 #define LCDC_SR_YMAX(x) ((x)&0x000003FF) argument
57 #define LCDC_VPWR_VPW(x) (((x)&0x000003FF) argument
67 #define LCDC_CPR_CYP(x) ((x)&0x000003FF) argument
73 #define LCDC_CWHBR_BD(x) ((x)&0x000000FF) argument
113 #define LCDC_PCR_PCD(x) ((x)&0x0000003F) argument
130 #define LCDC_SCR_GRAY1(x) ((x)&&0x0000000F) argument
140 #define LCDC_PCCR_PW(x) ((x)&0x000000FF) argument
145 #define LCDC_DCR_TM(x) ((x)&0x0000001F) argument
170 #define LCDC_GWSR_GWH(x) ((x)&0x000003FF) argument
176 #define LCDC_GWPOR_GWPO(x) ((x)&0x0000001F) argument
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/u-boot/arch/mips/include/asm/mach-generic/
A Dmangle-port.h27 # define ioswabb(a, x) (x) argument
28 # define __mem_ioswabb(a, x) (x) argument
29 # define ioswabw(a, x) le16_to_cpu(x) argument
30 # define __mem_ioswabw(a, x) (x) argument
32 # define __mem_ioswabl(a, x) (x) argument
34 # define __mem_ioswabq(a, x) (x) argument
38 # define ioswabb(a, x) (x) argument
39 # define __mem_ioswabb(a, x) (x) argument
40 # define ioswabw(a, x) (x) argument
42 # define ioswabl(a, x) (x) argument
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/u-boot/arch/arm/mach-at91/include/mach/
A Dsama5d2_smc.h32 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) argument
33 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) argument
34 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) argument
37 #define AT91_SMC_PULSE_NWE(x) (x & 0x7f) argument
38 #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) argument
39 #define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) argument
42 #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) argument
43 #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) argument
45 #define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) argument
46 #define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) argument
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/u-boot/arch/m68k/include/asm/
A Dm5329.h17 #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) argument
18 #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) argument
19 #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) argument
20 #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) argument
21 #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) argument
22 #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) argument
96 #define PACR0(x) SCM_PACRA_PACR0(x) argument
97 #define PACR1(x) SCM_PACRA_PACR1(x) argument
98 #define PACR2(x) SCM_PACRA_PACR2(x) argument
99 #define PACR8(x) SCM_PACRB_PACR8(x) argument
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