1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
4
5 #include <asm/processor-flags.h>
6
7 /* Forward declaration, a strange C thing */
8 struct task_struct;
9 struct mm_struct;
10 struct io_bitmap;
11 struct vm86;
12
13 #include <asm/math_emu.h>
14 #include <asm/segment.h>
15 #include <asm/types.h>
16 #include <uapi/asm/sigcontext.h>
17 #include <asm/current.h>
18 #include <asm/cpufeatures.h>
19 #include <asm/page.h>
20 #include <asm/pgtable_types.h>
21 #include <asm/percpu.h>
22 #include <asm/msr.h>
23 #include <asm/desc_defs.h>
24 #include <asm/nops.h>
25 #include <asm/special_insns.h>
26 #include <asm/fpu/types.h>
27 #include <asm/unwind_hints.h>
28 #include <asm/vmxfeatures.h>
29 #include <asm/vdso/processor.h>
30
31 #include <linux/personality.h>
32 #include <linux/cache.h>
33 #include <linux/threads.h>
34 #include <linux/math64.h>
35 #include <linux/err.h>
36 #include <linux/irqflags.h>
37 #include <linux/mem_encrypt.h>
38
39 /*
40 * We handle most unaligned accesses in hardware. On the other hand
41 * unaligned DMA can be quite expensive on some Nehalem processors.
42 *
43 * Based on this we disable the IP header alignment in network drivers.
44 */
45 #define NET_IP_ALIGN 0
46
47 #define HBP_NUM 4
48
49 /*
50 * These alignment constraints are for performance in the vSMP case,
51 * but in the task_struct case we must also meet hardware imposed
52 * alignment requirements of the FPU state:
53 */
54 #ifdef CONFIG_X86_VSMP
55 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
56 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
57 #else
58 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
59 # define ARCH_MIN_MMSTRUCT_ALIGN 0
60 #endif
61
62 enum tlb_infos {
63 ENTRIES,
64 NR_INFO
65 };
66
67 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
68 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
69 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
70 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
71 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
72 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
73 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
74
75 /*
76 * CPU type and hardware bug flags. Kept separately for each CPU.
77 * Members of this structure are referenced in head_32.S, so think twice
78 * before touching them. [mj]
79 */
80
81 struct cpuinfo_x86 {
82 __u8 x86; /* CPU family */
83 __u8 x86_vendor; /* CPU vendor */
84 __u8 x86_model;
85 __u8 x86_stepping;
86 #ifdef CONFIG_X86_64
87 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
88 int x86_tlbsize;
89 #endif
90 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
91 __u32 vmx_capability[NVMXINTS];
92 #endif
93 __u8 x86_virt_bits;
94 __u8 x86_phys_bits;
95 /* CPUID returned core id bits: */
96 __u8 x86_coreid_bits;
97 __u8 cu_id;
98 /* Max extended CPUID function supported: */
99 __u32 extended_cpuid_level;
100 /* Maximum supported CPUID level, -1=no CPUID: */
101 int cpuid_level;
102 /*
103 * Align to size of unsigned long because the x86_capability array
104 * is passed to bitops which require the alignment. Use unnamed
105 * union to enforce the array is aligned to size of unsigned long.
106 */
107 union {
108 __u32 x86_capability[NCAPINTS + NBUGINTS];
109 unsigned long x86_capability_alignment;
110 };
111 char x86_vendor_id[16];
112 char x86_model_id[64];
113 /* in KB - valid for CPUS which support this call: */
114 unsigned int x86_cache_size;
115 int x86_cache_alignment; /* In bytes */
116 /* Cache QoS architectural values, valid only on the BSP: */
117 int x86_cache_max_rmid; /* max index */
118 int x86_cache_occ_scale; /* scale to bytes */
119 int x86_cache_mbm_width_offset;
120 int x86_power;
121 unsigned long loops_per_jiffy;
122 /* cpuid returned max cores value: */
123 u16 x86_max_cores;
124 u16 apicid;
125 u16 initial_apicid;
126 u16 x86_clflush_size;
127 /* number of cores as seen by the OS: */
128 u16 booted_cores;
129 /* Physical processor id: */
130 u16 phys_proc_id;
131 /* Logical processor id: */
132 u16 logical_proc_id;
133 /* Core id: */
134 u16 cpu_core_id;
135 u16 cpu_die_id;
136 u16 logical_die_id;
137 /* Index into per_cpu list: */
138 u16 cpu_index;
139 /* Is SMT active on this core? */
140 bool smt_active;
141 u32 microcode;
142 /* Address space bits used by the cache internally */
143 u8 x86_cache_bits;
144 unsigned initialized : 1;
145 } __randomize_layout;
146
147 struct cpuid_regs {
148 u32 eax, ebx, ecx, edx;
149 };
150
151 enum cpuid_regs_idx {
152 CPUID_EAX = 0,
153 CPUID_EBX,
154 CPUID_ECX,
155 CPUID_EDX,
156 };
157
158 #define X86_VENDOR_INTEL 0
159 #define X86_VENDOR_CYRIX 1
160 #define X86_VENDOR_AMD 2
161 #define X86_VENDOR_UMC 3
162 #define X86_VENDOR_CENTAUR 5
163 #define X86_VENDOR_TRANSMETA 7
164 #define X86_VENDOR_NSC 8
165 #define X86_VENDOR_HYGON 9
166 #define X86_VENDOR_ZHAOXIN 10
167 #define X86_VENDOR_VORTEX 11
168 #define X86_VENDOR_NUM 12
169
170 #define X86_VENDOR_UNKNOWN 0xff
171
172 /*
173 * capabilities of CPUs
174 */
175 extern struct cpuinfo_x86 boot_cpu_data;
176 extern struct cpuinfo_x86 new_cpu_data;
177
178 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
179 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
180
181 #ifdef CONFIG_SMP
182 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
183 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
184 #else
185 #define cpu_info boot_cpu_data
186 #define cpu_data(cpu) boot_cpu_data
187 #endif
188
189 extern const struct seq_operations cpuinfo_op;
190
191 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
192
193 extern void cpu_detect(struct cpuinfo_x86 *c);
194
l1tf_pfn_limit(void)195 static inline unsigned long long l1tf_pfn_limit(void)
196 {
197 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
198 }
199
200 extern void early_cpu_init(void);
201 extern void identify_boot_cpu(void);
202 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
203 extern void print_cpu_info(struct cpuinfo_x86 *);
204 void print_cpu_msr(struct cpuinfo_x86 *);
205
206 #ifdef CONFIG_X86_32
207 extern int have_cpuid_p(void);
208 #else
have_cpuid_p(void)209 static inline int have_cpuid_p(void)
210 {
211 return 1;
212 }
213 #endif
native_cpuid(unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)214 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
215 unsigned int *ecx, unsigned int *edx)
216 {
217 /* ecx is often an input as well as an output. */
218 asm volatile("cpuid"
219 : "=a" (*eax),
220 "=b" (*ebx),
221 "=c" (*ecx),
222 "=d" (*edx)
223 : "0" (*eax), "2" (*ecx)
224 : "memory");
225 }
226
227 #define native_cpuid_reg(reg) \
228 static inline unsigned int native_cpuid_##reg(unsigned int op) \
229 { \
230 unsigned int eax = op, ebx, ecx = 0, edx; \
231 \
232 native_cpuid(&eax, &ebx, &ecx, &edx); \
233 \
234 return reg; \
235 }
236
237 /*
238 * Native CPUID functions returning a single datum.
239 */
240 native_cpuid_reg(eax)
native_cpuid_reg(ebx)241 native_cpuid_reg(ebx)
242 native_cpuid_reg(ecx)
243 native_cpuid_reg(edx)
244
245 /*
246 * Friendlier CR3 helpers.
247 */
248 static inline unsigned long read_cr3_pa(void)
249 {
250 return __read_cr3() & CR3_ADDR_MASK;
251 }
252
native_read_cr3_pa(void)253 static inline unsigned long native_read_cr3_pa(void)
254 {
255 return __native_read_cr3() & CR3_ADDR_MASK;
256 }
257
load_cr3(pgd_t * pgdir)258 static inline void load_cr3(pgd_t *pgdir)
259 {
260 write_cr3(__sme_pa(pgdir));
261 }
262
263 /*
264 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
265 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
266 * unrelated to the task-switch mechanism:
267 */
268 #ifdef CONFIG_X86_32
269 /* This is the TSS defined by the hardware. */
270 struct x86_hw_tss {
271 unsigned short back_link, __blh;
272 unsigned long sp0;
273 unsigned short ss0, __ss0h;
274 unsigned long sp1;
275
276 /*
277 * We don't use ring 1, so ss1 is a convenient scratch space in
278 * the same cacheline as sp0. We use ss1 to cache the value in
279 * MSR_IA32_SYSENTER_CS. When we context switch
280 * MSR_IA32_SYSENTER_CS, we first check if the new value being
281 * written matches ss1, and, if it's not, then we wrmsr the new
282 * value and update ss1.
283 *
284 * The only reason we context switch MSR_IA32_SYSENTER_CS is
285 * that we set it to zero in vm86 tasks to avoid corrupting the
286 * stack if we were to go through the sysenter path from vm86
287 * mode.
288 */
289 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
290
291 unsigned short __ss1h;
292 unsigned long sp2;
293 unsigned short ss2, __ss2h;
294 unsigned long __cr3;
295 unsigned long ip;
296 unsigned long flags;
297 unsigned long ax;
298 unsigned long cx;
299 unsigned long dx;
300 unsigned long bx;
301 unsigned long sp;
302 unsigned long bp;
303 unsigned long si;
304 unsigned long di;
305 unsigned short es, __esh;
306 unsigned short cs, __csh;
307 unsigned short ss, __ssh;
308 unsigned short ds, __dsh;
309 unsigned short fs, __fsh;
310 unsigned short gs, __gsh;
311 unsigned short ldt, __ldth;
312 unsigned short trace;
313 unsigned short io_bitmap_base;
314
315 } __attribute__((packed));
316 #else
317 struct x86_hw_tss {
318 u32 reserved1;
319 u64 sp0;
320 u64 sp1;
321
322 /*
323 * Since Linux does not use ring 2, the 'sp2' slot is unused by
324 * hardware. entry_SYSCALL_64 uses it as scratch space to stash
325 * the user RSP value.
326 */
327 u64 sp2;
328
329 u64 reserved2;
330 u64 ist[7];
331 u32 reserved3;
332 u32 reserved4;
333 u16 reserved5;
334 u16 io_bitmap_base;
335
336 } __attribute__((packed));
337 #endif
338
339 /*
340 * IO-bitmap sizes:
341 */
342 #define IO_BITMAP_BITS 65536
343 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE)
344 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long))
345
346 #define IO_BITMAP_OFFSET_VALID_MAP \
347 (offsetof(struct tss_struct, io_bitmap.bitmap) - \
348 offsetof(struct tss_struct, x86_tss))
349
350 #define IO_BITMAP_OFFSET_VALID_ALL \
351 (offsetof(struct tss_struct, io_bitmap.mapall) - \
352 offsetof(struct tss_struct, x86_tss))
353
354 #ifdef CONFIG_X86_IOPL_IOPERM
355 /*
356 * sizeof(unsigned long) coming from an extra "long" at the end of the
357 * iobitmap. The limit is inclusive, i.e. the last valid byte.
358 */
359 # define __KERNEL_TSS_LIMIT \
360 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
361 sizeof(unsigned long) - 1)
362 #else
363 # define __KERNEL_TSS_LIMIT \
364 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
365 #endif
366
367 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */
368 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1)
369
370 struct entry_stack {
371 char stack[PAGE_SIZE];
372 };
373
374 struct entry_stack_page {
375 struct entry_stack stack;
376 } __aligned(PAGE_SIZE);
377
378 /*
379 * All IO bitmap related data stored in the TSS:
380 */
381 struct x86_io_bitmap {
382 /* The sequence number of the last active bitmap. */
383 u64 prev_sequence;
384
385 /*
386 * Store the dirty size of the last io bitmap offender. The next
387 * one will have to do the cleanup as the switch out to a non io
388 * bitmap user will just set x86_tss.io_bitmap_base to a value
389 * outside of the TSS limit. So for sane tasks there is no need to
390 * actually touch the io_bitmap at all.
391 */
392 unsigned int prev_max;
393
394 /*
395 * The extra 1 is there because the CPU will access an
396 * additional byte beyond the end of the IO permission
397 * bitmap. The extra byte must be all 1 bits, and must
398 * be within the limit.
399 */
400 unsigned long bitmap[IO_BITMAP_LONGS + 1];
401
402 /*
403 * Special I/O bitmap to emulate IOPL(3). All bytes zero,
404 * except the additional byte at the end.
405 */
406 unsigned long mapall[IO_BITMAP_LONGS + 1];
407 };
408
409 struct tss_struct {
410 /*
411 * The fixed hardware portion. This must not cross a page boundary
412 * at risk of violating the SDM's advice and potentially triggering
413 * errata.
414 */
415 struct x86_hw_tss x86_tss;
416
417 struct x86_io_bitmap io_bitmap;
418 } __aligned(PAGE_SIZE);
419
420 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
421
422 /* Per CPU interrupt stacks */
423 struct irq_stack {
424 char stack[IRQ_STACK_SIZE];
425 } __aligned(IRQ_STACK_SIZE);
426
427 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
428
429 #ifdef CONFIG_X86_64
430 struct fixed_percpu_data {
431 /*
432 * GCC hardcodes the stack canary as %gs:40. Since the
433 * irq_stack is the object at %gs:0, we reserve the bottom
434 * 48 bytes of the irq stack for the canary.
435 *
436 * Once we are willing to require -mstack-protector-guard-symbol=
437 * support for x86_64 stackprotector, we can get rid of this.
438 */
439 char gs_base[40];
440 unsigned long stack_canary;
441 };
442
443 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
444 DECLARE_INIT_PER_CPU(fixed_percpu_data);
445
cpu_kernelmode_gs_base(int cpu)446 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
447 {
448 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
449 }
450
451 DECLARE_PER_CPU(void *, hardirq_stack_ptr);
452 DECLARE_PER_CPU(bool, hardirq_stack_inuse);
453 extern asmlinkage void ignore_sysret(void);
454
455 /* Save actual FS/GS selectors and bases to current->thread */
456 void current_save_fsgs(void);
457 #else /* X86_64 */
458 #ifdef CONFIG_STACKPROTECTOR
459 DECLARE_PER_CPU(unsigned long, __stack_chk_guard);
460 #endif
461 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
462 DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr);
463 #endif /* !X86_64 */
464
465 struct perf_event;
466
467 struct thread_struct {
468 /* Cached TLS descriptors: */
469 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
470 #ifdef CONFIG_X86_32
471 unsigned long sp0;
472 #endif
473 unsigned long sp;
474 #ifdef CONFIG_X86_32
475 unsigned long sysenter_cs;
476 #else
477 unsigned short es;
478 unsigned short ds;
479 unsigned short fsindex;
480 unsigned short gsindex;
481 #endif
482
483 #ifdef CONFIG_X86_64
484 unsigned long fsbase;
485 unsigned long gsbase;
486 #else
487 /*
488 * XXX: this could presumably be unsigned short. Alternatively,
489 * 32-bit kernels could be taught to use fsindex instead.
490 */
491 unsigned long fs;
492 unsigned long gs;
493 #endif
494
495 /* Save middle states of ptrace breakpoints */
496 struct perf_event *ptrace_bps[HBP_NUM];
497 /* Debug status used for traps, single steps, etc... */
498 unsigned long virtual_dr6;
499 /* Keep track of the exact dr7 value set by the user */
500 unsigned long ptrace_dr7;
501 /* Fault info: */
502 unsigned long cr2;
503 unsigned long trap_nr;
504 unsigned long error_code;
505 #ifdef CONFIG_VM86
506 /* Virtual 86 mode info */
507 struct vm86 *vm86;
508 #endif
509 /* IO permissions: */
510 struct io_bitmap *io_bitmap;
511
512 /*
513 * IOPL. Privilege level dependent I/O permission which is
514 * emulated via the I/O bitmap to prevent user space from disabling
515 * interrupts.
516 */
517 unsigned long iopl_emul;
518
519 unsigned int iopl_warn:1;
520 unsigned int sig_on_uaccess_err:1;
521
522 /*
523 * Protection Keys Register for Userspace. Loaded immediately on
524 * context switch. Store it in thread_struct to avoid a lookup in
525 * the tasks's FPU xstate buffer. This value is only valid when a
526 * task is scheduled out. For 'current' the authoritative source of
527 * PKRU is the hardware itself.
528 */
529 u32 pkru;
530
531 /* Floating point and extended processor state */
532 struct fpu fpu;
533 /*
534 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
535 * the end.
536 */
537 };
538
539 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size);
540
arch_thread_struct_whitelist(unsigned long * offset,unsigned long * size)541 static inline void arch_thread_struct_whitelist(unsigned long *offset,
542 unsigned long *size)
543 {
544 fpu_thread_struct_whitelist(offset, size);
545 }
546
547 static inline void
native_load_sp0(unsigned long sp0)548 native_load_sp0(unsigned long sp0)
549 {
550 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
551 }
552
native_swapgs(void)553 static __always_inline void native_swapgs(void)
554 {
555 #ifdef CONFIG_X86_64
556 asm volatile("swapgs" ::: "memory");
557 #endif
558 }
559
current_top_of_stack(void)560 static inline unsigned long current_top_of_stack(void)
561 {
562 /*
563 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
564 * and around vm86 mode and sp0 on x86_64 is special because of the
565 * entry trampoline.
566 */
567 return this_cpu_read_stable(cpu_current_top_of_stack);
568 }
569
on_thread_stack(void)570 static inline bool on_thread_stack(void)
571 {
572 return (unsigned long)(current_top_of_stack() -
573 current_stack_pointer) < THREAD_SIZE;
574 }
575
576 #ifdef CONFIG_PARAVIRT_XXL
577 #include <asm/paravirt.h>
578 #else
579 #define __cpuid native_cpuid
580
load_sp0(unsigned long sp0)581 static inline void load_sp0(unsigned long sp0)
582 {
583 native_load_sp0(sp0);
584 }
585
586 #endif /* CONFIG_PARAVIRT_XXL */
587
588 /* Free all resources held by a thread. */
589 extern void release_thread(struct task_struct *);
590
591 unsigned long __get_wchan(struct task_struct *p);
592
593 /*
594 * Generic CPUID function
595 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
596 * resulting in stale register contents being returned.
597 */
cpuid(unsigned int op,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)598 static inline void cpuid(unsigned int op,
599 unsigned int *eax, unsigned int *ebx,
600 unsigned int *ecx, unsigned int *edx)
601 {
602 *eax = op;
603 *ecx = 0;
604 __cpuid(eax, ebx, ecx, edx);
605 }
606
607 /* Some CPUID calls want 'count' to be placed in ecx */
cpuid_count(unsigned int op,int count,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)608 static inline void cpuid_count(unsigned int op, int count,
609 unsigned int *eax, unsigned int *ebx,
610 unsigned int *ecx, unsigned int *edx)
611 {
612 *eax = op;
613 *ecx = count;
614 __cpuid(eax, ebx, ecx, edx);
615 }
616
617 /*
618 * CPUID functions returning a single datum
619 */
cpuid_eax(unsigned int op)620 static inline unsigned int cpuid_eax(unsigned int op)
621 {
622 unsigned int eax, ebx, ecx, edx;
623
624 cpuid(op, &eax, &ebx, &ecx, &edx);
625
626 return eax;
627 }
628
cpuid_ebx(unsigned int op)629 static inline unsigned int cpuid_ebx(unsigned int op)
630 {
631 unsigned int eax, ebx, ecx, edx;
632
633 cpuid(op, &eax, &ebx, &ecx, &edx);
634
635 return ebx;
636 }
637
cpuid_ecx(unsigned int op)638 static inline unsigned int cpuid_ecx(unsigned int op)
639 {
640 unsigned int eax, ebx, ecx, edx;
641
642 cpuid(op, &eax, &ebx, &ecx, &edx);
643
644 return ecx;
645 }
646
cpuid_edx(unsigned int op)647 static inline unsigned int cpuid_edx(unsigned int op)
648 {
649 unsigned int eax, ebx, ecx, edx;
650
651 cpuid(op, &eax, &ebx, &ecx, &edx);
652
653 return edx;
654 }
655
656 extern void select_idle_routine(const struct cpuinfo_x86 *c);
657 extern void amd_e400_c1e_apic_setup(void);
658
659 extern unsigned long boot_option_idle_override;
660
661 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
662 IDLE_POLL};
663
664 extern void enable_sep_cpu(void);
665 extern int sysenter_setup(void);
666
667
668 /* Defined in head.S */
669 extern struct desc_ptr early_gdt_descr;
670
671 extern void switch_to_new_gdt(int);
672 extern void load_direct_gdt(int);
673 extern void load_fixmap_gdt(int);
674 extern void load_percpu_segment(int);
675 extern void cpu_init(void);
676 extern void cpu_init_secondary(void);
677 extern void cpu_init_exception_handling(void);
678 extern void cr4_init(void);
679
get_debugctlmsr(void)680 static inline unsigned long get_debugctlmsr(void)
681 {
682 unsigned long debugctlmsr = 0;
683
684 #ifndef CONFIG_X86_DEBUGCTLMSR
685 if (boot_cpu_data.x86 < 6)
686 return 0;
687 #endif
688 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
689
690 return debugctlmsr;
691 }
692
update_debugctlmsr(unsigned long debugctlmsr)693 static inline void update_debugctlmsr(unsigned long debugctlmsr)
694 {
695 #ifndef CONFIG_X86_DEBUGCTLMSR
696 if (boot_cpu_data.x86 < 6)
697 return;
698 #endif
699 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
700 }
701
702 extern void set_task_blockstep(struct task_struct *task, bool on);
703
704 /* Boot loader type from the setup header: */
705 extern int bootloader_type;
706 extern int bootloader_version;
707
708 extern char ignore_fpu_irq;
709
710 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
711 #define ARCH_HAS_PREFETCHW
712 #define ARCH_HAS_SPINLOCK_PREFETCH
713
714 #ifdef CONFIG_X86_32
715 # define BASE_PREFETCH ""
716 # define ARCH_HAS_PREFETCH
717 #else
718 # define BASE_PREFETCH "prefetcht0 %P1"
719 #endif
720
721 /*
722 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
723 *
724 * It's not worth to care about 3dnow prefetches for the K6
725 * because they are microcoded there and very slow.
726 */
prefetch(const void * x)727 static inline void prefetch(const void *x)
728 {
729 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
730 X86_FEATURE_XMM,
731 "m" (*(const char *)x));
732 }
733
734 /*
735 * 3dnow prefetch to get an exclusive cache line.
736 * Useful for spinlocks to avoid one state transition in the
737 * cache coherency protocol:
738 */
prefetchw(const void * x)739 static __always_inline void prefetchw(const void *x)
740 {
741 alternative_input(BASE_PREFETCH, "prefetchw %P1",
742 X86_FEATURE_3DNOWPREFETCH,
743 "m" (*(const char *)x));
744 }
745
spin_lock_prefetch(const void * x)746 static inline void spin_lock_prefetch(const void *x)
747 {
748 prefetchw(x);
749 }
750
751 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
752 TOP_OF_KERNEL_STACK_PADDING)
753
754 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
755
756 #define task_pt_regs(task) \
757 ({ \
758 unsigned long __ptr = (unsigned long)task_stack_page(task); \
759 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
760 ((struct pt_regs *)__ptr) - 1; \
761 })
762
763 #ifdef CONFIG_X86_32
764 #define INIT_THREAD { \
765 .sp0 = TOP_OF_INIT_STACK, \
766 .sysenter_cs = __KERNEL_CS, \
767 }
768
769 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
770
771 #else
772 #define INIT_THREAD { }
773
774 extern unsigned long KSTK_ESP(struct task_struct *task);
775
776 #endif /* CONFIG_X86_64 */
777
778 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
779 unsigned long new_sp);
780
781 /*
782 * This decides where the kernel will search for a free chunk of vm
783 * space during mmap's.
784 */
785 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
786 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
787
788 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
789
790 /* Get/set a process' ability to use the timestamp counter instruction */
791 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
792 #define SET_TSC_CTL(val) set_tsc_mode((val))
793
794 extern int get_tsc_mode(unsigned long adr);
795 extern int set_tsc_mode(unsigned int val);
796
797 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
798
799 extern u16 get_llc_id(unsigned int cpu);
800
801 #ifdef CONFIG_CPU_SUP_AMD
802 extern u32 amd_get_nodes_per_socket(void);
803 extern u32 amd_get_highest_perf(void);
804 #else
amd_get_nodes_per_socket(void)805 static inline u32 amd_get_nodes_per_socket(void) { return 0; }
amd_get_highest_perf(void)806 static inline u32 amd_get_highest_perf(void) { return 0; }
807 #endif
808
809 #define for_each_possible_hypervisor_cpuid_base(function) \
810 for (function = 0x40000000; function < 0x40010000; function += 0x100)
811
hypervisor_cpuid_base(const char * sig,uint32_t leaves)812 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
813 {
814 uint32_t base, eax, signature[3];
815
816 for_each_possible_hypervisor_cpuid_base(base) {
817 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
818
819 if (!memcmp(sig, signature, 12) &&
820 (leaves == 0 || ((eax - base) >= leaves)))
821 return base;
822 }
823
824 return 0;
825 }
826
827 extern unsigned long arch_align_stack(unsigned long sp);
828 void free_init_pages(const char *what, unsigned long begin, unsigned long end);
829 extern void free_kernel_image_pages(const char *what, void *begin, void *end);
830
831 void default_idle(void);
832 #ifdef CONFIG_XEN
833 bool xen_set_default_idle(void);
834 #else
835 #define xen_set_default_idle 0
836 #endif
837
838 void stop_this_cpu(void *dummy);
839 void microcode_check(void);
840
841 enum l1tf_mitigations {
842 L1TF_MITIGATION_OFF,
843 L1TF_MITIGATION_FLUSH_NOWARN,
844 L1TF_MITIGATION_FLUSH,
845 L1TF_MITIGATION_FLUSH_NOSMT,
846 L1TF_MITIGATION_FULL,
847 L1TF_MITIGATION_FULL_FORCE
848 };
849
850 extern enum l1tf_mitigations l1tf_mitigation;
851
852 enum mds_mitigations {
853 MDS_MITIGATION_OFF,
854 MDS_MITIGATION_FULL,
855 MDS_MITIGATION_VMWERV,
856 };
857
858 #endif /* _ASM_X86_PROCESSOR_H */
859