1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/power/xlnx-zynqmp-power.h> 16#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 17 18/ { 19 compatible = "xlnx,zynqmp"; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 compatible = "arm,cortex-a53"; 29 device_type = "cpu"; 30 enable-method = "psci"; 31 operating-points-v2 = <&cpu_opp_table>; 32 reg = <0x0>; 33 cpu-idle-states = <&CPU_SLEEP_0>; 34 }; 35 36 cpu1: cpu@1 { 37 compatible = "arm,cortex-a53"; 38 device_type = "cpu"; 39 enable-method = "psci"; 40 reg = <0x1>; 41 operating-points-v2 = <&cpu_opp_table>; 42 cpu-idle-states = <&CPU_SLEEP_0>; 43 }; 44 45 cpu2: cpu@2 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 enable-method = "psci"; 49 reg = <0x2>; 50 operating-points-v2 = <&cpu_opp_table>; 51 cpu-idle-states = <&CPU_SLEEP_0>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 reg = <0x3>; 59 operating-points-v2 = <&cpu_opp_table>; 60 cpu-idle-states = <&CPU_SLEEP_0>; 61 }; 62 63 idle-states { 64 entry-method = "psci"; 65 66 CPU_SLEEP_0: cpu-sleep-0 { 67 compatible = "arm,idle-state"; 68 arm,psci-suspend-param = <0x40000000>; 69 local-timer-stop; 70 entry-latency-us = <300>; 71 exit-latency-us = <600>; 72 min-residency-us = <10000>; 73 }; 74 }; 75 }; 76 77 cpu_opp_table: cpu-opp-table { 78 compatible = "operating-points-v2"; 79 opp-shared; 80 opp00 { 81 opp-hz = /bits/ 64 <1199999988>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <500000>; 84 }; 85 opp01 { 86 opp-hz = /bits/ 64 <599999994>; 87 opp-microvolt = <1000000>; 88 clock-latency-ns = <500000>; 89 }; 90 opp02 { 91 opp-hz = /bits/ 64 <399999996>; 92 opp-microvolt = <1000000>; 93 clock-latency-ns = <500000>; 94 }; 95 opp03 { 96 opp-hz = /bits/ 64 <299999997>; 97 opp-microvolt = <1000000>; 98 clock-latency-ns = <500000>; 99 }; 100 }; 101 102 zynqmp_ipi { 103 u-boot,dm-pre-reloc; 104 compatible = "xlnx,zynqmp-ipi-mailbox"; 105 interrupt-parent = <&gic>; 106 interrupts = <0 35 4>; 107 xlnx,ipi-id = <0>; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges; 111 112 ipi_mailbox_pmu1: mailbox@ff990400 { 113 u-boot,dm-pre-reloc; 114 reg = <0x0 0xff9905c0 0x0 0x20>, 115 <0x0 0xff9905e0 0x0 0x20>, 116 <0x0 0xff990e80 0x0 0x20>, 117 <0x0 0xff990ea0 0x0 0x20>; 118 reg-names = "local_request_region", 119 "local_response_region", 120 "remote_request_region", 121 "remote_response_region"; 122 #mbox-cells = <1>; 123 xlnx,ipi-id = <4>; 124 }; 125 }; 126 127 dcc: dcc { 128 compatible = "arm,dcc"; 129 status = "disabled"; 130 u-boot,dm-pre-reloc; 131 }; 132 133 pmu { 134 compatible = "arm,armv8-pmuv3"; 135 interrupt-parent = <&gic>; 136 interrupts = <0 143 4>, 137 <0 144 4>, 138 <0 145 4>, 139 <0 146 4>; 140 }; 141 142 psci { 143 compatible = "arm,psci-0.2"; 144 method = "smc"; 145 }; 146 147 firmware { 148 zynqmp_firmware: zynqmp-firmware { 149 compatible = "xlnx,zynqmp-firmware"; 150 #power-domain-cells = <1>; 151 method = "smc"; 152 u-boot,dm-pre-reloc; 153 154 zynqmp_power: zynqmp-power { 155 u-boot,dm-pre-reloc; 156 compatible = "xlnx,zynqmp-power"; 157 interrupt-parent = <&gic>; 158 interrupts = <0 35 4>; 159 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 160 mbox-names = "tx", "rx"; 161 }; 162 163 zynqmp_pcap: pcap { 164 compatible = "xlnx,zynqmp-pcap-fpga"; 165 clock-names = "ref_clk"; 166 }; 167 168 zynqmp_reset: reset-controller { 169 compatible = "xlnx,zynqmp-reset"; 170 #reset-cells = <1>; 171 }; 172 173 pinctrl0: pinctrl { 174 compatible = "xlnx,zynqmp-pinctrl"; 175 status = "disabled"; 176 }; 177 }; 178 }; 179 180 timer { 181 compatible = "arm,armv8-timer"; 182 interrupt-parent = <&gic>; 183 interrupts = <1 13 0xf08>, 184 <1 14 0xf08>, 185 <1 11 0xf08>, 186 <1 10 0xf08>; 187 }; 188 189 edac { 190 compatible = "arm,cortex-a53-edac"; 191 }; 192 193 fpga_full: fpga-full { 194 compatible = "fpga-region"; 195 fpga-mgr = <&zynqmp_pcap>; 196 #address-cells = <2>; 197 #size-cells = <2>; 198 ranges; 199 }; 200 201 nvmem_firmware { 202 compatible = "xlnx,zynqmp-nvmem-fw"; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 206 soc_revision: soc_revision@0 { 207 reg = <0x0 0x4>; 208 }; 209 }; 210 211 amba: axi { 212 compatible = "simple-bus"; 213 u-boot,dm-pre-reloc; 214 #address-cells = <2>; 215 #size-cells = <2>; 216 ranges; 217 218 can0: can@ff060000 { 219 compatible = "xlnx,zynq-can-1.0"; 220 status = "disabled"; 221 clock-names = "can_clk", "pclk"; 222 reg = <0x0 0xff060000 0x0 0x1000>; 223 interrupts = <0 23 4>; 224 interrupt-parent = <&gic>; 225 tx-fifo-depth = <0x40>; 226 rx-fifo-depth = <0x40>; 227 power-domains = <&zynqmp_firmware PD_CAN_0>; 228 }; 229 230 can1: can@ff070000 { 231 compatible = "xlnx,zynq-can-1.0"; 232 status = "disabled"; 233 clock-names = "can_clk", "pclk"; 234 reg = <0x0 0xff070000 0x0 0x1000>; 235 interrupts = <0 24 4>; 236 interrupt-parent = <&gic>; 237 tx-fifo-depth = <0x40>; 238 rx-fifo-depth = <0x40>; 239 power-domains = <&zynqmp_firmware PD_CAN_1>; 240 }; 241 242 cci: cci@fd6e0000 { 243 compatible = "arm,cci-400"; 244 reg = <0x0 0xfd6e0000 0x0 0x9000>; 245 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 246 #address-cells = <1>; 247 #size-cells = <1>; 248 249 pmu@9000 { 250 compatible = "arm,cci-400-pmu,r1"; 251 reg = <0x9000 0x5000>; 252 interrupt-parent = <&gic>; 253 interrupts = <0 123 4>, 254 <0 123 4>, 255 <0 123 4>, 256 <0 123 4>, 257 <0 123 4>; 258 }; 259 }; 260 261 /* GDMA */ 262 fpd_dma_chan1: dma@fd500000 { 263 status = "disabled"; 264 compatible = "xlnx,zynqmp-dma-1.0"; 265 reg = <0x0 0xfd500000 0x0 0x1000>; 266 interrupt-parent = <&gic>; 267 interrupts = <0 124 4>; 268 clock-names = "clk_main", "clk_apb"; 269 xlnx,bus-width = <128>; 270 #stream-id-cells = <1>; 271 iommus = <&smmu 0x14e8>; 272 power-domains = <&zynqmp_firmware PD_GDMA>; 273 }; 274 275 fpd_dma_chan2: dma@fd510000 { 276 status = "disabled"; 277 compatible = "xlnx,zynqmp-dma-1.0"; 278 reg = <0x0 0xfd510000 0x0 0x1000>; 279 interrupt-parent = <&gic>; 280 interrupts = <0 125 4>; 281 clock-names = "clk_main", "clk_apb"; 282 xlnx,bus-width = <128>; 283 #stream-id-cells = <1>; 284 iommus = <&smmu 0x14e9>; 285 power-domains = <&zynqmp_firmware PD_GDMA>; 286 }; 287 288 fpd_dma_chan3: dma@fd520000 { 289 status = "disabled"; 290 compatible = "xlnx,zynqmp-dma-1.0"; 291 reg = <0x0 0xfd520000 0x0 0x1000>; 292 interrupt-parent = <&gic>; 293 interrupts = <0 126 4>; 294 clock-names = "clk_main", "clk_apb"; 295 xlnx,bus-width = <128>; 296 #stream-id-cells = <1>; 297 iommus = <&smmu 0x14ea>; 298 power-domains = <&zynqmp_firmware PD_GDMA>; 299 }; 300 301 fpd_dma_chan4: dma@fd530000 { 302 status = "disabled"; 303 compatible = "xlnx,zynqmp-dma-1.0"; 304 reg = <0x0 0xfd530000 0x0 0x1000>; 305 interrupt-parent = <&gic>; 306 interrupts = <0 127 4>; 307 clock-names = "clk_main", "clk_apb"; 308 xlnx,bus-width = <128>; 309 #stream-id-cells = <1>; 310 iommus = <&smmu 0x14eb>; 311 power-domains = <&zynqmp_firmware PD_GDMA>; 312 }; 313 314 fpd_dma_chan5: dma@fd540000 { 315 status = "disabled"; 316 compatible = "xlnx,zynqmp-dma-1.0"; 317 reg = <0x0 0xfd540000 0x0 0x1000>; 318 interrupt-parent = <&gic>; 319 interrupts = <0 128 4>; 320 clock-names = "clk_main", "clk_apb"; 321 xlnx,bus-width = <128>; 322 #stream-id-cells = <1>; 323 iommus = <&smmu 0x14ec>; 324 power-domains = <&zynqmp_firmware PD_GDMA>; 325 }; 326 327 fpd_dma_chan6: dma@fd550000 { 328 status = "disabled"; 329 compatible = "xlnx,zynqmp-dma-1.0"; 330 reg = <0x0 0xfd550000 0x0 0x1000>; 331 interrupt-parent = <&gic>; 332 interrupts = <0 129 4>; 333 clock-names = "clk_main", "clk_apb"; 334 xlnx,bus-width = <128>; 335 #stream-id-cells = <1>; 336 iommus = <&smmu 0x14ed>; 337 power-domains = <&zynqmp_firmware PD_GDMA>; 338 }; 339 340 fpd_dma_chan7: dma@fd560000 { 341 status = "disabled"; 342 compatible = "xlnx,zynqmp-dma-1.0"; 343 reg = <0x0 0xfd560000 0x0 0x1000>; 344 interrupt-parent = <&gic>; 345 interrupts = <0 130 4>; 346 clock-names = "clk_main", "clk_apb"; 347 xlnx,bus-width = <128>; 348 #stream-id-cells = <1>; 349 iommus = <&smmu 0x14ee>; 350 power-domains = <&zynqmp_firmware PD_GDMA>; 351 }; 352 353 fpd_dma_chan8: dma@fd570000 { 354 status = "disabled"; 355 compatible = "xlnx,zynqmp-dma-1.0"; 356 reg = <0x0 0xfd570000 0x0 0x1000>; 357 interrupt-parent = <&gic>; 358 interrupts = <0 131 4>; 359 clock-names = "clk_main", "clk_apb"; 360 xlnx,bus-width = <128>; 361 #stream-id-cells = <1>; 362 iommus = <&smmu 0x14ef>; 363 power-domains = <&zynqmp_firmware PD_GDMA>; 364 }; 365 366 gic: interrupt-controller@f9010000 { 367 compatible = "arm,gic-400"; 368 #interrupt-cells = <3>; 369 reg = <0x0 0xf9010000 0x0 0x10000>, 370 <0x0 0xf9020000 0x0 0x20000>, 371 <0x0 0xf9040000 0x0 0x20000>, 372 <0x0 0xf9060000 0x0 0x20000>; 373 interrupt-controller; 374 interrupt-parent = <&gic>; 375 interrupts = <1 9 0xf04>; 376 }; 377 378 gpu: gpu@fd4b0000 { 379 status = "disabled"; 380 compatible = "arm,mali-400", "arm,mali-utgard"; 381 reg = <0x0 0xfd4b0000 0x0 0x10000>; 382 interrupt-parent = <&gic>; 383 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; 384 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; 385 clock-names = "gpu", "gpu_pp0", "gpu_pp1"; 386 power-domains = <&zynqmp_firmware PD_GPU>; 387 }; 388 389 /* LPDDMA default allows only secured access. inorder to enable 390 * These dma channels, Users should ensure that these dma 391 * Channels are allowed for non secure access. 392 */ 393 lpd_dma_chan1: dma@ffa80000 { 394 status = "disabled"; 395 compatible = "xlnx,zynqmp-dma-1.0"; 396 reg = <0x0 0xffa80000 0x0 0x1000>; 397 interrupt-parent = <&gic>; 398 interrupts = <0 77 4>; 399 clock-names = "clk_main", "clk_apb"; 400 xlnx,bus-width = <64>; 401 #stream-id-cells = <1>; 402 iommus = <&smmu 0x868>; 403 power-domains = <&zynqmp_firmware PD_ADMA>; 404 }; 405 406 lpd_dma_chan2: dma@ffa90000 { 407 status = "disabled"; 408 compatible = "xlnx,zynqmp-dma-1.0"; 409 reg = <0x0 0xffa90000 0x0 0x1000>; 410 interrupt-parent = <&gic>; 411 interrupts = <0 78 4>; 412 clock-names = "clk_main", "clk_apb"; 413 xlnx,bus-width = <64>; 414 #stream-id-cells = <1>; 415 iommus = <&smmu 0x869>; 416 power-domains = <&zynqmp_firmware PD_ADMA>; 417 }; 418 419 lpd_dma_chan3: dma@ffaa0000 { 420 status = "disabled"; 421 compatible = "xlnx,zynqmp-dma-1.0"; 422 reg = <0x0 0xffaa0000 0x0 0x1000>; 423 interrupt-parent = <&gic>; 424 interrupts = <0 79 4>; 425 clock-names = "clk_main", "clk_apb"; 426 xlnx,bus-width = <64>; 427 #stream-id-cells = <1>; 428 iommus = <&smmu 0x86a>; 429 power-domains = <&zynqmp_firmware PD_ADMA>; 430 }; 431 432 lpd_dma_chan4: dma@ffab0000 { 433 status = "disabled"; 434 compatible = "xlnx,zynqmp-dma-1.0"; 435 reg = <0x0 0xffab0000 0x0 0x1000>; 436 interrupt-parent = <&gic>; 437 interrupts = <0 80 4>; 438 clock-names = "clk_main", "clk_apb"; 439 xlnx,bus-width = <64>; 440 #stream-id-cells = <1>; 441 iommus = <&smmu 0x86b>; 442 power-domains = <&zynqmp_firmware PD_ADMA>; 443 }; 444 445 lpd_dma_chan5: dma@ffac0000 { 446 status = "disabled"; 447 compatible = "xlnx,zynqmp-dma-1.0"; 448 reg = <0x0 0xffac0000 0x0 0x1000>; 449 interrupt-parent = <&gic>; 450 interrupts = <0 81 4>; 451 clock-names = "clk_main", "clk_apb"; 452 xlnx,bus-width = <64>; 453 #stream-id-cells = <1>; 454 iommus = <&smmu 0x86c>; 455 power-domains = <&zynqmp_firmware PD_ADMA>; 456 }; 457 458 lpd_dma_chan6: dma@ffad0000 { 459 status = "disabled"; 460 compatible = "xlnx,zynqmp-dma-1.0"; 461 reg = <0x0 0xffad0000 0x0 0x1000>; 462 interrupt-parent = <&gic>; 463 interrupts = <0 82 4>; 464 clock-names = "clk_main", "clk_apb"; 465 xlnx,bus-width = <64>; 466 #stream-id-cells = <1>; 467 iommus = <&smmu 0x86d>; 468 power-domains = <&zynqmp_firmware PD_ADMA>; 469 }; 470 471 lpd_dma_chan7: dma@ffae0000 { 472 status = "disabled"; 473 compatible = "xlnx,zynqmp-dma-1.0"; 474 reg = <0x0 0xffae0000 0x0 0x1000>; 475 interrupt-parent = <&gic>; 476 interrupts = <0 83 4>; 477 clock-names = "clk_main", "clk_apb"; 478 xlnx,bus-width = <64>; 479 #stream-id-cells = <1>; 480 iommus = <&smmu 0x86e>; 481 power-domains = <&zynqmp_firmware PD_ADMA>; 482 }; 483 484 lpd_dma_chan8: dma@ffaf0000 { 485 status = "disabled"; 486 compatible = "xlnx,zynqmp-dma-1.0"; 487 reg = <0x0 0xffaf0000 0x0 0x1000>; 488 interrupt-parent = <&gic>; 489 interrupts = <0 84 4>; 490 clock-names = "clk_main", "clk_apb"; 491 xlnx,bus-width = <64>; 492 #stream-id-cells = <1>; 493 iommus = <&smmu 0x86f>; 494 power-domains = <&zynqmp_firmware PD_ADMA>; 495 }; 496 497 mc: memory-controller@fd070000 { 498 compatible = "xlnx,zynqmp-ddrc-2.40a"; 499 reg = <0x0 0xfd070000 0x0 0x30000>; 500 interrupt-parent = <&gic>; 501 interrupts = <0 112 4>; 502 }; 503 504 nand0: nand@ff100000 { 505 compatible = "arasan,nfc-v3p10"; 506 status = "disabled"; 507 reg = <0x0 0xff100000 0x0 0x1000>; 508 clock-names = "clk_sys", "clk_flash"; 509 interrupt-parent = <&gic>; 510 interrupts = <0 14 4>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 #stream-id-cells = <1>; 514 iommus = <&smmu 0x872>; 515 power-domains = <&zynqmp_firmware PD_NAND>; 516 }; 517 518 gem0: ethernet@ff0b0000 { 519 compatible = "cdns,zynqmp-gem", "cdns,gem"; 520 status = "disabled"; 521 interrupt-parent = <&gic>; 522 interrupts = <0 57 4>, <0 57 4>; 523 reg = <0x0 0xff0b0000 0x0 0x1000>; 524 clock-names = "pclk", "hclk", "tx_clk"; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 #stream-id-cells = <1>; 528 iommus = <&smmu 0x874>; 529 power-domains = <&zynqmp_firmware PD_ETH_0>; 530 }; 531 532 gem1: ethernet@ff0c0000 { 533 compatible = "cdns,zynqmp-gem", "cdns,gem"; 534 status = "disabled"; 535 interrupt-parent = <&gic>; 536 interrupts = <0 59 4>, <0 59 4>; 537 reg = <0x0 0xff0c0000 0x0 0x1000>; 538 clock-names = "pclk", "hclk", "tx_clk"; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 #stream-id-cells = <1>; 542 iommus = <&smmu 0x875>; 543 power-domains = <&zynqmp_firmware PD_ETH_1>; 544 }; 545 546 gem2: ethernet@ff0d0000 { 547 compatible = "cdns,zynqmp-gem", "cdns,gem"; 548 status = "disabled"; 549 interrupt-parent = <&gic>; 550 interrupts = <0 61 4>, <0 61 4>; 551 reg = <0x0 0xff0d0000 0x0 0x1000>; 552 clock-names = "pclk", "hclk", "tx_clk"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 #stream-id-cells = <1>; 556 iommus = <&smmu 0x876>; 557 power-domains = <&zynqmp_firmware PD_ETH_2>; 558 }; 559 560 gem3: ethernet@ff0e0000 { 561 compatible = "cdns,zynqmp-gem", "cdns,gem"; 562 status = "disabled"; 563 interrupt-parent = <&gic>; 564 interrupts = <0 63 4>, <0 63 4>; 565 reg = <0x0 0xff0e0000 0x0 0x1000>; 566 clock-names = "pclk", "hclk", "tx_clk"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 #stream-id-cells = <1>; 570 iommus = <&smmu 0x877>; 571 power-domains = <&zynqmp_firmware PD_ETH_3>; 572 }; 573 574 gpio: gpio@ff0a0000 { 575 compatible = "xlnx,zynqmp-gpio-1.0"; 576 status = "disabled"; 577 #gpio-cells = <0x2>; 578 gpio-controller; 579 interrupt-parent = <&gic>; 580 interrupts = <0 16 4>; 581 interrupt-controller; 582 #interrupt-cells = <2>; 583 reg = <0x0 0xff0a0000 0x0 0x1000>; 584 power-domains = <&zynqmp_firmware PD_GPIO>; 585 }; 586 587 i2c0: i2c@ff020000 { 588 compatible = "cdns,i2c-r1p14"; 589 status = "disabled"; 590 interrupt-parent = <&gic>; 591 interrupts = <0 17 4>; 592 reg = <0x0 0xff020000 0x0 0x1000>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 power-domains = <&zynqmp_firmware PD_I2C_0>; 596 }; 597 598 i2c1: i2c@ff030000 { 599 compatible = "cdns,i2c-r1p14"; 600 status = "disabled"; 601 interrupt-parent = <&gic>; 602 interrupts = <0 18 4>; 603 reg = <0x0 0xff030000 0x0 0x1000>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 power-domains = <&zynqmp_firmware PD_I2C_1>; 607 }; 608 609 ocm: memory-controller@ff960000 { 610 compatible = "xlnx,zynqmp-ocmc-1.0"; 611 reg = <0x0 0xff960000 0x0 0x1000>; 612 interrupt-parent = <&gic>; 613 interrupts = <0 10 4>; 614 }; 615 616 pcie: pcie@fd0e0000 { 617 compatible = "xlnx,nwl-pcie-2.11"; 618 status = "disabled"; 619 #address-cells = <3>; 620 #size-cells = <2>; 621 #interrupt-cells = <1>; 622 msi-controller; 623 device_type = "pci"; 624 interrupt-parent = <&gic>; 625 interrupts = <0 118 4>, 626 <0 117 4>, 627 <0 116 4>, 628 <0 115 4>, /* MSI_1 [63...32] */ 629 <0 114 4>; /* MSI_0 [31...0] */ 630 interrupt-names = "misc", "dummy", "intx", 631 "msi1", "msi0"; 632 msi-parent = <&pcie>; 633 reg = <0x0 0xfd0e0000 0x0 0x1000>, 634 <0x0 0xfd480000 0x0 0x1000>, 635 <0x80 0x00000000 0x0 0x1000000>; 636 reg-names = "breg", "pcireg", "cfg"; 637 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 638 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 639 bus-range = <0x00 0xff>; 640 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 641 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 642 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 643 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 644 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 645 power-domains = <&zynqmp_firmware PD_PCIE>; 646 pcie_intc: legacy-interrupt-controller { 647 interrupt-controller; 648 #address-cells = <0>; 649 #interrupt-cells = <1>; 650 }; 651 }; 652 653 qspi: spi@ff0f0000 { 654 u-boot,dm-pre-reloc; 655 compatible = "xlnx,zynqmp-qspi-1.0"; 656 status = "disabled"; 657 clock-names = "ref_clk", "pclk"; 658 interrupts = <0 15 4>; 659 interrupt-parent = <&gic>; 660 num-cs = <1>; 661 reg = <0x0 0xff0f0000 0x0 0x1000>, 662 <0x0 0xc0000000 0x0 0x8000000>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 #stream-id-cells = <1>; 666 iommus = <&smmu 0x873>; 667 power-domains = <&zynqmp_firmware PD_QSPI>; 668 }; 669 670 rtc: rtc@ffa60000 { 671 compatible = "xlnx,zynqmp-rtc"; 672 status = "disabled"; 673 reg = <0x0 0xffa60000 0x0 0x100>; 674 interrupt-parent = <&gic>; 675 interrupts = <0 26 4>, <0 27 4>; 676 interrupt-names = "alarm", "sec"; 677 calibration = <0x8000>; 678 }; 679 680 serdes: zynqmp_phy@fd400000 { 681 compatible = "xlnx,zynqmp-psgtr"; 682 status = "disabled"; 683 reg = <0x0 0xfd400000 0x0 0x40000>, 684 <0x0 0xfd3d0000 0x0 0x1000>, 685 <0x0 0xff5e0000 0x0 0x1000>; 686 reg-names = "serdes", "siou", "lpd"; 687 nvmem-cells = <&soc_revision>; 688 nvmem-cell-names = "soc_revision"; 689 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>, 690 <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 691 <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 692 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 693 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 694 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>, 695 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, 696 <&zynqmp_reset ZYNQMP_RESET_DP>, 697 <&zynqmp_reset ZYNQMP_RESET_GEM0>, 698 <&zynqmp_reset ZYNQMP_RESET_GEM1>, 699 <&zynqmp_reset ZYNQMP_RESET_GEM2>, 700 <&zynqmp_reset ZYNQMP_RESET_GEM3>; 701 reset-names = "sata_rst", "usb0_crst", "usb1_crst", 702 "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", 703 "usb1_apbrst", "dp_rst", "gem0_rst", 704 "gem1_rst", "gem2_rst", "gem3_rst"; 705 lane0: lane0 { 706 #phy-cells = <4>; 707 }; 708 lane1: lane1 { 709 #phy-cells = <4>; 710 }; 711 lane2: lane2 { 712 #phy-cells = <4>; 713 }; 714 lane3: lane3 { 715 #phy-cells = <4>; 716 }; 717 }; 718 719 sata: ahci@fd0c0000 { 720 compatible = "ceva,ahci-1v84"; 721 status = "disabled"; 722 reg = <0x0 0xfd0c0000 0x0 0x2000>; 723 interrupt-parent = <&gic>; 724 interrupts = <0 133 4>; 725 power-domains = <&zynqmp_firmware PD_SATA>; 726 #stream-id-cells = <4>; 727 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, 728 <&smmu 0x4c2>, <&smmu 0x4c3>; 729 /* dma-coherent; */ 730 }; 731 732 sdhci0: mmc@ff160000 { 733 u-boot,dm-pre-reloc; 734 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 735 status = "disabled"; 736 interrupt-parent = <&gic>; 737 interrupts = <0 48 4>; 738 reg = <0x0 0xff160000 0x0 0x1000>; 739 clock-names = "clk_xin", "clk_ahb"; 740 xlnx,device_id = <0>; 741 #stream-id-cells = <1>; 742 iommus = <&smmu 0x870>; 743 power-domains = <&zynqmp_firmware PD_SD_0>; 744 nvmem-cells = <&soc_revision>; 745 nvmem-cell-names = "soc_revision"; 746 #clock-cells = <1>; 747 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 748 }; 749 750 sdhci1: mmc@ff170000 { 751 u-boot,dm-pre-reloc; 752 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 753 status = "disabled"; 754 interrupt-parent = <&gic>; 755 interrupts = <0 49 4>; 756 reg = <0x0 0xff170000 0x0 0x1000>; 757 clock-names = "clk_xin", "clk_ahb"; 758 xlnx,device_id = <1>; 759 #stream-id-cells = <1>; 760 iommus = <&smmu 0x871>; 761 power-domains = <&zynqmp_firmware PD_SD_1>; 762 nvmem-cells = <&soc_revision>; 763 nvmem-cell-names = "soc_revision"; 764 #clock-cells = <1>; 765 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 766 }; 767 768 smmu: iommu@fd800000 { 769 compatible = "arm,mmu-500"; 770 reg = <0x0 0xfd800000 0x0 0x20000>; 771 #iommu-cells = <1>; 772 status = "disabled"; 773 #global-interrupts = <1>; 774 interrupt-parent = <&gic>; 775 interrupts = <0 155 4>, 776 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 777 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 778 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 779 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 780 }; 781 782 spi0: spi@ff040000 { 783 compatible = "cdns,spi-r1p6"; 784 status = "disabled"; 785 interrupt-parent = <&gic>; 786 interrupts = <0 19 4>; 787 reg = <0x0 0xff040000 0x0 0x1000>; 788 clock-names = "ref_clk", "pclk"; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 power-domains = <&zynqmp_firmware PD_SPI_0>; 792 }; 793 794 spi1: spi@ff050000 { 795 compatible = "cdns,spi-r1p6"; 796 status = "disabled"; 797 interrupt-parent = <&gic>; 798 interrupts = <0 20 4>; 799 reg = <0x0 0xff050000 0x0 0x1000>; 800 clock-names = "ref_clk", "pclk"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 power-domains = <&zynqmp_firmware PD_SPI_1>; 804 }; 805 806 ttc0: timer@ff110000 { 807 compatible = "cdns,ttc"; 808 status = "disabled"; 809 interrupt-parent = <&gic>; 810 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 811 reg = <0x0 0xff110000 0x0 0x1000>; 812 timer-width = <32>; 813 power-domains = <&zynqmp_firmware PD_TTC_0>; 814 }; 815 816 ttc1: timer@ff120000 { 817 compatible = "cdns,ttc"; 818 status = "disabled"; 819 interrupt-parent = <&gic>; 820 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 821 reg = <0x0 0xff120000 0x0 0x1000>; 822 timer-width = <32>; 823 power-domains = <&zynqmp_firmware PD_TTC_1>; 824 }; 825 826 ttc2: timer@ff130000 { 827 compatible = "cdns,ttc"; 828 status = "disabled"; 829 interrupt-parent = <&gic>; 830 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 831 reg = <0x0 0xff130000 0x0 0x1000>; 832 timer-width = <32>; 833 power-domains = <&zynqmp_firmware PD_TTC_2>; 834 }; 835 836 ttc3: timer@ff140000 { 837 compatible = "cdns,ttc"; 838 status = "disabled"; 839 interrupt-parent = <&gic>; 840 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 841 reg = <0x0 0xff140000 0x0 0x1000>; 842 timer-width = <32>; 843 power-domains = <&zynqmp_firmware PD_TTC_3>; 844 }; 845 846 uart0: serial@ff000000 { 847 u-boot,dm-pre-reloc; 848 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 849 status = "disabled"; 850 interrupt-parent = <&gic>; 851 interrupts = <0 21 4>; 852 reg = <0x0 0xff000000 0x0 0x1000>; 853 clock-names = "uart_clk", "pclk"; 854 power-domains = <&zynqmp_firmware PD_UART_0>; 855 }; 856 857 uart1: serial@ff010000 { 858 u-boot,dm-pre-reloc; 859 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 860 status = "disabled"; 861 interrupt-parent = <&gic>; 862 interrupts = <0 22 4>; 863 reg = <0x0 0xff010000 0x0 0x1000>; 864 clock-names = "uart_clk", "pclk"; 865 power-domains = <&zynqmp_firmware PD_UART_1>; 866 }; 867 868 usb0: usb0@ff9d0000 { 869 #address-cells = <2>; 870 #size-cells = <2>; 871 status = "disabled"; 872 compatible = "xlnx,zynqmp-dwc3"; 873 reg = <0x0 0xff9d0000 0x0 0x100>; 874 clock-names = "bus_clk", "ref_clk"; 875 power-domains = <&zynqmp_firmware PD_USB_0>; 876 ranges; 877 nvmem-cells = <&soc_revision>; 878 nvmem-cell-names = "soc_revision"; 879 880 dwc3_0: dwc3@fe200000 { 881 compatible = "snps,dwc3"; 882 status = "disabled"; 883 reg = <0x0 0xfe200000 0x0 0x40000>; 884 interrupt-parent = <&gic>; 885 interrupts = <0 65 4>, <0 69 4>; 886 #stream-id-cells = <1>; 887 iommus = <&smmu 0x860>; 888 snps,quirk-frame-length-adjustment = <0x20>; 889 snps,refclk_fladj; 890 /* dma-coherent; */ 891 }; 892 }; 893 894 usb1: usb1@ff9e0000 { 895 #address-cells = <2>; 896 #size-cells = <2>; 897 status = "disabled"; 898 compatible = "xlnx,zynqmp-dwc3"; 899 reg = <0x0 0xff9e0000 0x0 0x100>; 900 clock-names = "bus_clk", "ref_clk"; 901 power-domains = <&zynqmp_firmware PD_USB_1>; 902 ranges; 903 nvmem-cells = <&soc_revision>; 904 nvmem-cell-names = "soc_revision"; 905 906 dwc3_1: dwc3@fe300000 { 907 compatible = "snps,dwc3"; 908 status = "disabled"; 909 reg = <0x0 0xfe300000 0x0 0x40000>; 910 interrupt-parent = <&gic>; 911 interrupts = <0 70 4>, <0 74 4>; 912 #stream-id-cells = <1>; 913 iommus = <&smmu 0x861>; 914 snps,quirk-frame-length-adjustment = <0x20>; 915 snps,refclk_fladj; 916 /* dma-coherent; */ 917 }; 918 }; 919 920 watchdog0: watchdog@fd4d0000 { 921 compatible = "cdns,wdt-r1p2"; 922 status = "disabled"; 923 interrupt-parent = <&gic>; 924 interrupts = <0 113 1>; 925 reg = <0x0 0xfd4d0000 0x0 0x1000>; 926 timeout-sec = <60>; 927 reset-on-timeout; 928 }; 929 930 lpd_watchdog: watchdog@ff150000 { 931 compatible = "cdns,wdt-r1p2"; 932 status = "disabled"; 933 interrupt-parent = <&gic>; 934 interrupts = <0 52 1>; 935 reg = <0x0 0xff150000 0x0 0x1000>; 936 timeout-sec = <10>; 937 }; 938 939 xilinx_ams: ams@ffa50000 { 940 compatible = "xlnx,zynqmp-ams"; 941 status = "disabled"; 942 interrupt-parent = <&gic>; 943 interrupts = <0 56 4>; 944 interrupt-names = "ams-irq"; 945 reg = <0x0 0xffa50000 0x0 0x800>; 946 reg-names = "ams-base"; 947 #address-cells = <2>; 948 #size-cells = <2>; 949 #io-channel-cells = <1>; 950 ranges; 951 952 ams_ps: ams_ps@ffa50800 { 953 compatible = "xlnx,zynqmp-ams-ps"; 954 status = "disabled"; 955 reg = <0x0 0xffa50800 0x0 0x400>; 956 }; 957 958 ams_pl: ams_pl@ffa50c00 { 959 compatible = "xlnx,zynqmp-ams-pl"; 960 status = "disabled"; 961 reg = <0x0 0xffa50c00 0x0 0x400>; 962 }; 963 }; 964 965 xlnx_dpdma: dma@fd4c0000 { 966 compatible = "xlnx,dpdma"; 967 status = "disabled"; 968 reg = <0x0 0xfd4c0000 0x0 0x1000>; 969 interrupts = <0 122 4>; 970 interrupt-parent = <&gic>; 971 clock-names = "axi_clk"; 972 power-domains = <&zynqmp_firmware PD_DP>; 973 dma-channels = <6>; 974 #dma-cells = <1>; 975 dma-video0channel { 976 compatible = "xlnx,video0"; 977 }; 978 dma-video1channel { 979 compatible = "xlnx,video1"; 980 }; 981 dma-video2channel { 982 compatible = "xlnx,video2"; 983 }; 984 dma-graphicschannel { 985 compatible = "xlnx,graphics"; 986 }; 987 dma-audio0channel { 988 compatible = "xlnx,audio0"; 989 }; 990 dma-audio1channel { 991 compatible = "xlnx,audio1"; 992 }; 993 }; 994 995 zynqmp_dpsub: zynqmp-display@fd4a0000 { 996 compatible = "xlnx,zynqmp-dpsub-1.7"; 997 status = "disabled"; 998 reg = <0x0 0xfd4a0000 0x0 0x1000>, 999 <0x0 0xfd4aa000 0x0 0x1000>, 1000 <0x0 0xfd4ab000 0x0 0x1000>, 1001 <0x0 0xfd4ac000 0x0 0x1000>; 1002 reg-names = "dp", "blend", "av_buf", "aud"; 1003 interrupts = <0 119 4>; 1004 interrupt-parent = <&gic>; 1005 1006 clock-names = "dp_apb_clk", "dp_aud_clk", 1007 "dp_vtc_pixel_clk_in"; 1008 1009 power-domains = <&zynqmp_firmware PD_DP>; 1010 1011 vid-layer { 1012 dma-names = "vid0", "vid1", "vid2"; 1013 dmas = <&xlnx_dpdma 0>, 1014 <&xlnx_dpdma 1>, 1015 <&xlnx_dpdma 2>; 1016 }; 1017 1018 gfx-layer { 1019 dma-names = "gfx0"; 1020 dmas = <&xlnx_dpdma 3>; 1021 }; 1022 1023 /* dummy node to indicate there's no child i2c device */ 1024 i2c-bus { 1025 }; 1026 1027 zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { 1028 compatible = "xlnx,dp-snd-codec"; 1029 clock-names = "aud_clk"; 1030 }; 1031 1032 zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { 1033 compatible = "xlnx,dp-snd-pcm"; 1034 dmas = <&xlnx_dpdma 4>; 1035 dma-names = "tx"; 1036 }; 1037 1038 zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { 1039 compatible = "xlnx,dp-snd-pcm"; 1040 dmas = <&xlnx_dpdma 5>; 1041 dma-names = "tx"; 1042 }; 1043 1044 zynqmp_dp_snd_card0: zynqmp_dp_snd_card { 1045 compatible = "xlnx,dp-snd-card"; 1046 xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, 1047 <&zynqmp_dp_snd_pcm1>; 1048 xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; 1049 }; 1050 }; 1051 }; 1052}; 1053