1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #include <assert.h>
8
9 #include <arch_helpers.h>
10 #include <bl31/bl31.h>
11 #include <common/debug.h>
12 #include <drivers/delay_timer.h>
13 #include <lib/mmio.h>
14 #include <lib/psci/psci.h>
15
16 #include <platform.h>
17 #include <platform_def.h>
18 #include <qti_cpu.h>
19 #include <qti_plat.h>
20 #include <qtiseclib_cb_interface.h>
21 #include <qtiseclib_defs_plat.h>
22 #include <qtiseclib_interface.h>
23
24 #define QTI_LOCAL_PSTATE_WIDTH 4
25 #define QTI_LOCAL_PSTATE_MASK ((1 << QTI_LOCAL_PSTATE_WIDTH) - 1)
26
27 /* Make composite power state parameter till level 0 */
28 #define qti_make_pwrstate_lvl0(lvl0_state, type) \
29 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
30
31 /* Make composite power state parameter till level 1 */
32 #define qti_make_pwrstate_lvl1(lvl1_state, lvl0_state, type) \
33 (((lvl1_state) << QTI_LOCAL_PSTATE_WIDTH) | \
34 qti_make_pwrstate_lvl0(lvl0_state, type))
35
36 /* Make composite power state parameter till level 2 */
37 #define qti_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, type) \
38 (((lvl2_state) << (QTI_LOCAL_PSTATE_WIDTH * 2)) | \
39 qti_make_pwrstate_lvl1(lvl1_state, lvl0_state, type))
40
41 /* Make composite power state parameter till level 3 */
42 #define qti_make_pwrstate_lvl3(lvl3_state, lvl2_state, lvl1_state, lvl0_state, type) \
43 (((lvl3_state) << (QTI_LOCAL_PSTATE_WIDTH * 3)) | \
44 qti_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, type))
45
46 /* QTI_CORE_PWRDN_EN_MASK happens to be same across all CPUs */
47 #define QTI_CORE_PWRDN_EN_MASK 1
48
49 /* cpu power control happens to be same across all CPUs */
50 _DEFINE_SYSREG_WRITE_FUNC(cpu_pwrctrl_val, S3_0_C15_C2_7)
51 _DEFINE_SYSREG_READ_FUNC(cpu_pwrctrl_val, S3_0_C15_C2_7)
52
53 const unsigned int qti_pm_idle_states[] = {
54 qti_make_pwrstate_lvl0(QTI_LOCAL_STATE_OFF,
55 PSTATE_TYPE_POWERDOWN),
56 qti_make_pwrstate_lvl0(QTI_LOCAL_STATE_DEEPOFF,
57 PSTATE_TYPE_POWERDOWN),
58 qti_make_pwrstate_lvl1(QTI_LOCAL_STATE_DEEPOFF,
59 QTI_LOCAL_STATE_DEEPOFF,
60 PSTATE_TYPE_POWERDOWN),
61 qti_make_pwrstate_lvl2(QTI_LOCAL_STATE_OFF,
62 QTI_LOCAL_STATE_DEEPOFF,
63 QTI_LOCAL_STATE_DEEPOFF,
64 PSTATE_TYPE_POWERDOWN),
65 qti_make_pwrstate_lvl3(QTI_LOCAL_STATE_OFF,
66 QTI_LOCAL_STATE_DEEPOFF,
67 QTI_LOCAL_STATE_DEEPOFF,
68 QTI_LOCAL_STATE_DEEPOFF,
69 PSTATE_TYPE_POWERDOWN),
70 0,
71 };
72
73 /*******************************************************************************
74 * QTI standard platform handler called to check the validity of the power
75 * state parameter. The power state parameter has to be a composite power
76 * state.
77 ******************************************************************************/
qti_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)78 int qti_validate_power_state(unsigned int power_state,
79 psci_power_state_t *req_state)
80 {
81 unsigned int state_id;
82 int i;
83
84 assert(req_state);
85
86 /*
87 * Currently we are using a linear search for finding the matching
88 * entry in the idle power state array. This can be made a binary
89 * search if the number of entries justify the additional complexity.
90 */
91 for (i = 0; !!qti_pm_idle_states[i]; i++) {
92 if (power_state == qti_pm_idle_states[i])
93 break;
94 }
95
96 /* Return error if entry not found in the idle state array */
97 if (!qti_pm_idle_states[i])
98 return PSCI_E_INVALID_PARAMS;
99
100 i = 0;
101 state_id = psci_get_pstate_id(power_state);
102
103 /* Parse the State ID and populate the state info parameter */
104 while (state_id) {
105 req_state->pwr_domain_state[i++] = state_id &
106 QTI_LOCAL_PSTATE_MASK;
107 state_id >>= QTI_LOCAL_PSTATE_WIDTH;
108 }
109
110 return PSCI_E_SUCCESS;
111 }
112
113 /*******************************************************************************
114 * PLATFORM FUNCTIONS
115 ******************************************************************************/
116
qti_set_cpupwrctlr_val(void)117 static void qti_set_cpupwrctlr_val(void)
118 {
119 unsigned long val;
120
121 val = read_cpu_pwrctrl_val();
122 val |= QTI_CORE_PWRDN_EN_MASK;
123 write_cpu_pwrctrl_val(val);
124
125 isb();
126 }
127
128 /**
129 * CPU power on function - ideally we want a wrapper since this function is
130 * target specific. But to unblock teams.
131 */
qti_cpu_power_on(u_register_t mpidr)132 static int qti_cpu_power_on(u_register_t mpidr)
133 {
134 int core_pos = plat_core_pos_by_mpidr(mpidr);
135
136 /* If not valid mpidr, return error */
137 if (core_pos < 0 || core_pos >= QTISECLIB_PLAT_CORE_COUNT) {
138 return PSCI_E_INVALID_PARAMS;
139 }
140
141 return qtiseclib_psci_node_power_on(mpidr);
142 }
143
is_cpu_off(const psci_power_state_t * target_state)144 static bool is_cpu_off(const psci_power_state_t *target_state)
145 {
146 if ((target_state->pwr_domain_state[QTI_PWR_LVL0] ==
147 QTI_LOCAL_STATE_OFF) ||
148 (target_state->pwr_domain_state[QTI_PWR_LVL0] ==
149 QTI_LOCAL_STATE_DEEPOFF)) {
150 return true;
151 } else {
152 return false;
153 }
154 }
155
qti_cpu_power_on_finish(const psci_power_state_t * target_state)156 static void qti_cpu_power_on_finish(const psci_power_state_t *target_state)
157 {
158 const uint8_t *pwr_states =
159 (const uint8_t *)target_state->pwr_domain_state;
160 qtiseclib_psci_node_on_finish(pwr_states);
161
162 if (is_cpu_off(target_state)) {
163 plat_qti_gic_cpuif_enable();
164 }
165 }
166
qti_cpu_standby(plat_local_state_t cpu_state)167 static void qti_cpu_standby(plat_local_state_t cpu_state)
168 {
169 }
170
qti_node_power_off(const psci_power_state_t * target_state)171 static void qti_node_power_off(const psci_power_state_t *target_state)
172 {
173 qtiseclib_psci_node_power_off((const uint8_t *)
174 target_state->pwr_domain_state);
175 if (is_cpu_off(target_state)) {
176 plat_qti_gic_cpuif_disable();
177 qti_set_cpupwrctlr_val();
178 }
179 }
180
qti_node_suspend(const psci_power_state_t * target_state)181 static void qti_node_suspend(const psci_power_state_t *target_state)
182 {
183 qtiseclib_psci_node_suspend((const uint8_t *)target_state->
184 pwr_domain_state);
185 if (is_cpu_off(target_state)) {
186 plat_qti_gic_cpuif_disable();
187 qti_set_cpupwrctlr_val();
188 }
189 }
190
qti_node_suspend_finish(const psci_power_state_t * target_state)191 static void qti_node_suspend_finish(const psci_power_state_t *target_state)
192 {
193 const uint8_t *pwr_states =
194 (const uint8_t *)target_state->pwr_domain_state;
195 qtiseclib_psci_node_suspend_finish(pwr_states);
196 if (is_cpu_off(target_state)) {
197 plat_qti_gic_cpuif_enable();
198 }
199 }
200
qti_domain_power_down_wfi(const psci_power_state_t * target_state)201 __dead2 void qti_domain_power_down_wfi(const psci_power_state_t *target_state)
202 {
203
204 /* For now just do WFI - add any target specific handling if needed */
205 psci_power_down_wfi();
206 /* We should never reach here */
207 }
208
assert_ps_hold(void)209 static __dead2 void assert_ps_hold(void)
210 {
211 mmio_write_32(QTI_PS_HOLD_REG, 0);
212 mdelay(1000);
213
214 /* Should be dead before reaching this. */
215 panic();
216 }
217
qti_system_off(void)218 __dead2 void qti_system_off(void)
219 {
220 qti_pmic_prepare_shutdown();
221 assert_ps_hold();
222 }
223
qti_system_reset(void)224 __dead2 void qti_system_reset(void)
225 {
226 qti_pmic_prepare_reset();
227 assert_ps_hold();
228 }
229
qti_get_sys_suspend_power_state(psci_power_state_t * req_state)230 void qti_get_sys_suspend_power_state(psci_power_state_t *req_state)
231 {
232 int i = 0;
233 unsigned int state_id, power_state;
234 int size = ARRAY_SIZE(qti_pm_idle_states);
235
236 /*
237 * Find deepest state.
238 * The arm_pm_idle_states[] array has last element by default 0,
239 * so the real deepest state is second last element of that array.
240 */
241 power_state = qti_pm_idle_states[size - 2];
242 state_id = psci_get_pstate_id(power_state);
243
244 /* Parse the State ID and populate the state info parameter */
245 while (state_id) {
246 req_state->pwr_domain_state[i++] =
247 state_id & QTI_LOCAL_PSTATE_MASK;
248 state_id >>= QTI_LOCAL_PSTATE_WIDTH;
249 }
250 }
251
252 /*
253 * Structure containing platform specific PSCI operations. Common
254 * PSCI layer will use this.
255 */
256 const plat_psci_ops_t plat_qti_psci_pm_ops = {
257 .pwr_domain_on = qti_cpu_power_on,
258 .pwr_domain_on_finish = qti_cpu_power_on_finish,
259 .cpu_standby = qti_cpu_standby,
260 .pwr_domain_off = qti_node_power_off,
261 .pwr_domain_suspend = qti_node_suspend,
262 .pwr_domain_suspend_finish = qti_node_suspend_finish,
263 .pwr_domain_pwr_down_wfi = qti_domain_power_down_wfi,
264 .system_off = qti_system_off,
265 .system_reset = qti_system_reset,
266 .get_node_hw_state = NULL,
267 .translate_power_state_by_mpidr = NULL,
268 .get_sys_suspend_power_state = qti_get_sys_suspend_power_state,
269 .validate_power_state = qti_validate_power_state,
270 };
271
272 /**
273 * The QTI Standard platform definition of platform porting API
274 * `plat_setup_psci_ops`.
275 */
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)276 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
277 const plat_psci_ops_t **psci_ops)
278 {
279 int err;
280
281 err = qtiseclib_psci_init((uintptr_t)bl31_warm_entrypoint);
282 if (err == PSCI_E_SUCCESS) {
283 *psci_ops = &plat_qti_psci_pm_ops;
284 }
285
286 return err;
287 }
288