1One-register-per-pin type device tree based pinctrl driver
2
3Required properties:
4- compatible : "pinctrl-single" or "pinconf-single".
5  "pinctrl-single" means that pinconf isn't supported.
6  "pinconf-single" means that generic pinconf is supported.
7
8- reg : offset and length of the register set for the mux registers
9
10- #pinctrl-cells : number of cells in addition to the index, set to 1
11  or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
12
13- pinctrl-single,register-width : pinmux register access width in bits
14
15- pinctrl-single,function-mask : mask of allowed pinmux function bits
16  in the pinmux register
17
18Optional properties:
19- pinctrl-single,function-off : function off mode for disabled state if
20  available and same for all registers; if not specified, disabling of
21  pin functions is ignored
22
23- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
24  more than one pin, for which "pinctrl-single,function-mask" property specifies
25 position mask of pin.
26
27- pinctrl-single,drive-strength : array of value that are used to configure
28  drive strength in the pinmux register. They're value of drive strength
29  current and drive strength mask.
30
31		/* drive strength current, mask */
32		pinctrl-single,power-source = <0x30 0xf0>;
33
34- pinctrl-single,bias-pullup : array of value that are used to configure the
35  input bias pullup in the pinmux register.
36
37		/* input, enabled pullup bits, disabled pullup bits, mask */
38		pinctrl-single,bias-pullup = <0 1 0 1>;
39
40- pinctrl-single,bias-pulldown : array of value that are used to configure the
41  input bias pulldown in the pinmux register.
42
43		/* input, enabled pulldown bits, disabled pulldown bits, mask */
44		pinctrl-single,bias-pulldown = <2 2 0 2>;
45
46  * Two bits to control input bias pullup and pulldown: User should use
47    pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
48    pullup, and the other one bit means pulldown.
49  * Three bits to control input bias enable, pullup and pulldown. User should
50    use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
51    enable bit should be included in pullup or pulldown bits.
52  * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
53    pinctrl-single,bias-disable. Because pinctrl single driver could implement
54    it by calling pulldown, pullup disabled.
55
56- pinctrl-single,input-schmitt : array of value that are used to configure
57  input schmitt in the pinmux register. In some silicons, there're two input
58  schmitt value (rising-edge & falling-edge) in the pinmux register.
59
60		/* input schmitt value, mask */
61		pinctrl-single,input-schmitt = <0x30 0x70>;
62
63- pinctrl-single,input-schmitt-enable : array of value that are used to
64  configure input schmitt enable or disable in the pinmux register.
65
66		/* input, enable bits, disable bits, mask */
67		pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
68
69- pinctrl-single,low-power-mode : array of value that are used to configure
70  low power mode of this pin. For some silicons, the low power mode will
71  control the output of the pin when the pad including the pin enter low
72  power mode.
73		/* low power mode value, mask */
74		pinctrl-single,low-power-mode = <0x288 0x388>;
75
76- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
77  range. They're value of subnode phandle, pin base in pinctrl device, pin
78  number in this range, GPIO function value of this GPIO range.
79  The number of parameters is depend on #pinctrl-single,gpio-range-cells
80  property.
81
82		/* pin base, nr pins & gpio function */
83		pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>;
84
85- interrupt-controller : standard interrupt controller binding if using
86  interrupts for wake-up events for example. In this case pinctrl-single
87  is set up as a chained interrupt controller and the wake-up interrupts
88  can be requested by the drivers using request_irq().
89
90- #interrupt-cells : standard interrupt binding if using interrupts
91
92This driver assumes that there is only one register for each pin (unless the
93pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
94specified in the pinctrl-bindings.txt document in this directory.
95
96The pin configuration nodes for pinctrl-single are specified as pinctrl
97register offset and values using pinctrl-single,pins. Only the bits specified
98in pinctrl-single,function-mask are updated.
99
100When #pinctrl-cells = 1, then setting a pin for a device could be done with:
101
102	pinctrl-single,pins = <0xdc 0x118>;
103
104Where 0xdc is the offset from the pinctrl register base address for the device
105pinctrl register, and 0x118 contains the desired value of the pinctrl register.
106
107When #pinctrl-cells = 2, then setting a pin for a device could be done with:
108
109	pinctrl-single,pins = <0xdc 0x30 0x07>;
110
111Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value.
112These two values are OR'd together to produce the value stored at offset 0xdc.
113See the device example and static board pins example below for more information.
114
115In case when one register changes more than one pin's mux the
116pinctrl-single,bits need to be used which takes three parameters:
117
118	pinctrl-single,bits = <0xdc 0x18 0xff>;
119
120Where 0xdc is the offset from the pinctrl register base address for the
121device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
122be used when applying this change to the register.
123
124
125Optional sub-node: In case some pins could be configured as GPIO in the pinmux
126register, those pins could be defined as a GPIO range. This sub-node is required
127by pinctrl-single,gpio-range property.
128
129Required properties in sub-node:
130- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
131  pinctrl-single,gpio-range property.
132
133	range: gpio-range {
134		#pinctrl-single,gpio-range-cells = <3>;
135	};
136
137
138Example:
139
140/* SoC common file */
141
142/* first controller instance for pins in core domain */
143pmx_core: pinmux@4a100040 {
144	compatible = "pinctrl-single";
145	reg = <0x4a100040 0x0196>;
146	#address-cells = <1>;
147	#size-cells = <0>;
148	#interrupt-cells = <1>;
149	interrupt-controller;
150	pinctrl-single,register-width = <16>;
151	pinctrl-single,function-mask = <0xffff>;
152};
153
154/* second controller instance for pins in wkup domain */
155pmx_wkup: pinmux@4a31e040 {
156	compatible = "pinctrl-single";
157	reg = <0x4a31e040 0x0038>;
158	#address-cells = <1>;
159	#size-cells = <0>;
160	#interrupt-cells = <1>;
161	interrupt-controller;
162	pinctrl-single,register-width = <16>;
163	pinctrl-single,function-mask = <0xffff>;
164};
165
166control_devconf0: pinmux@48002274 {
167	compatible = "pinctrl-single";
168	reg = <0x48002274 4>;	/* Single register */
169	#address-cells = <1>;
170	#size-cells = <0>;
171	pinctrl-single,bit-per-mux;
172	pinctrl-single,register-width = <32>;
173	pinctrl-single,function-mask = <0x5F>;
174};
175
176/* third controller instance for pins in gpio domain */
177pmx_gpio: pinmux@d401e000 {
178	compatible = "pinconf-single";
179	reg = <0xd401e000 0x0330>;
180	#address-cells = <1>;
181	#size-cells = <1>;
182	ranges;
183
184	pinctrl-single,register-width = <32>;
185	pinctrl-single,function-mask = <7>;
186
187	/* sparse GPIO range could be supported */
188	pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>,
189				    <&range 12 1 0>, <&range 13 29 1>,
190				    <&range 43 1 0>, <&range 44 49 1>,
191				    <&range 94 1 1>, <&range 96 2 1>;
192
193	range: gpio-range {
194		#pinctrl-single,gpio-range-cells = <3>;
195	};
196};
197
198
199/* board specific .dts file */
200
201&pmx_core {
202
203	/*
204	 * map all board specific static pins enabled by the pinctrl driver
205	 * itself during the boot (or just set them up in the bootloader)
206	 */
207	pinctrl-names = "default";
208	pinctrl-0 = <&board_pins>;
209
210	board_pins: pinmux_board_pins {
211		pinctrl-single,pins = <
212			0x6c 0xf
213			0x6e 0xf
214			0x70 0xf
215			0x72 0xf
216		>;
217	};
218
219	uart0_pins: pinmux_uart0_pins {
220		pinctrl-single,pins = <
221			0x208 0		/* UART0_RXD (IOCFG138) */
222			0x20c 0		/* UART0_TXD (IOCFG139) */
223		>;
224		pinctrl-single,bias-pulldown = <0 2 2>;
225		pinctrl-single,bias-pullup = <0 1 1>;
226	};
227
228	/* map uart2 pins */
229	uart2_pins: pinmux_uart2_pins {
230		pinctrl-single,pins = <
231			0xd8 0x118
232			0xda 0
233			0xdc 0x118
234			0xde 0
235		>;
236	};
237};
238
239&control_devconf0 {
240	mcbsp1_pins: pinmux_mcbsp1_pins {
241		pinctrl-single,bits = <
242			0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
243		>;
244	};
245
246	mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
247		pinctrl-single,bits = <
248			0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
249		>;
250	};
251
252};
253
254&uart1 {
255       pinctrl-names = "default";
256       pinctrl-0 = <&uart0_pins>;
257};
258
259&uart2 {
260       pinctrl-names = "default";
261       pinctrl-0 = <&uart2_pins>;
262};
263