1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2020 Intel Corporation. All rights reserved.
4 //
5 // Author: Fred Oh <fred.oh@linux.intel.com>
6 //
7 
8 /*
9  * Hardware interface for audio DSP on IceLake.
10  */
11 
12 #include <linux/kernel.h>
13 #include <linux/kconfig.h>
14 #include <linux/export.h>
15 #include <linux/bits.h>
16 #include "../ops.h"
17 #include "hda.h"
18 #include "hda-ipc.h"
19 #include "../sof-audio.h"
20 
21 static const struct snd_sof_debugfs_map icl_dsp_debugfs[] = {
22 	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
23 	{"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
24 	{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
25 };
26 
27 /* Icelake ops */
28 const struct snd_sof_dsp_ops sof_icl_ops = {
29 	/* probe/remove/shutdown */
30 	.probe		= hda_dsp_probe,
31 	.remove		= hda_dsp_remove,
32 	.shutdown	= hda_dsp_shutdown,
33 
34 	/* Register IO */
35 	.write		= sof_io_write,
36 	.read		= sof_io_read,
37 	.write64	= sof_io_write64,
38 	.read64		= sof_io_read64,
39 
40 	/* Block IO */
41 	.block_read	= sof_block_read,
42 	.block_write	= sof_block_write,
43 
44 	/* Mailbox IO */
45 	.mailbox_read	= sof_mailbox_read,
46 	.mailbox_write	= sof_mailbox_write,
47 
48 	/* doorbell */
49 	.irq_thread	= cnl_ipc_irq_thread,
50 
51 	/* ipc */
52 	.send_msg	= cnl_ipc_send_msg,
53 	.fw_ready	= sof_fw_ready,
54 	.get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
55 	.get_window_offset = hda_dsp_ipc_get_window_offset,
56 
57 	.ipc_msg_data	= hda_ipc_msg_data,
58 	.ipc_pcm_params	= hda_ipc_pcm_params,
59 
60 	/* machine driver */
61 	.machine_select = hda_machine_select,
62 	.machine_register = sof_machine_register,
63 	.machine_unregister = sof_machine_unregister,
64 	.set_mach_params = hda_set_mach_params,
65 
66 	/* debug */
67 	.debug_map	= icl_dsp_debugfs,
68 	.debug_map_count	= ARRAY_SIZE(icl_dsp_debugfs),
69 	.dbg_dump	= hda_dsp_dump,
70 	.ipc_dump	= cnl_ipc_dump,
71 	.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
72 
73 	/* stream callbacks */
74 	.pcm_open	= hda_dsp_pcm_open,
75 	.pcm_close	= hda_dsp_pcm_close,
76 	.pcm_hw_params	= hda_dsp_pcm_hw_params,
77 	.pcm_hw_free	= hda_dsp_stream_hw_free,
78 	.pcm_trigger	= hda_dsp_pcm_trigger,
79 	.pcm_pointer	= hda_dsp_pcm_pointer,
80 
81 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
82 	/* probe callbacks */
83 	.probe_assign	= hda_probe_compr_assign,
84 	.probe_free	= hda_probe_compr_free,
85 	.probe_set_params	= hda_probe_compr_set_params,
86 	.probe_trigger	= hda_probe_compr_trigger,
87 	.probe_pointer	= hda_probe_compr_pointer,
88 #endif
89 
90 	/* firmware loading */
91 	.load_firmware = snd_sof_load_firmware_raw,
92 
93 	/* pre/post fw run */
94 	.pre_fw_run = hda_dsp_pre_fw_run,
95 	.post_fw_run = hda_dsp_post_fw_run_icl,
96 
97 	/* parse platform specific extended manifest */
98 	.parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data,
99 
100 	/* dsp core power up/down */
101 	.core_power_up = hda_dsp_enable_core,
102 	.core_power_down = hda_dsp_core_reset_power_down,
103 
104 	/* firmware run */
105 	.run = hda_dsp_cl_boot_firmware_iccmax,
106 	.stall = hda_dsp_core_stall_icl,
107 
108 	/* trace callback */
109 	.trace_init = hda_dsp_trace_init,
110 	.trace_release = hda_dsp_trace_release,
111 	.trace_trigger = hda_dsp_trace_trigger,
112 
113 	/* DAI drivers */
114 	.drv		= skl_dai,
115 	.num_drv	= SOF_SKL_NUM_DAIS,
116 
117 	/* PM */
118 	.suspend		= hda_dsp_suspend,
119 	.resume			= hda_dsp_resume,
120 	.runtime_suspend	= hda_dsp_runtime_suspend,
121 	.runtime_resume		= hda_dsp_runtime_resume,
122 	.runtime_idle		= hda_dsp_runtime_idle,
123 	.set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
124 	.set_power_state	= hda_dsp_set_power_state,
125 
126 	/* ALSA HW info flags */
127 	.hw_info =	SNDRV_PCM_INFO_MMAP |
128 			SNDRV_PCM_INFO_MMAP_VALID |
129 			SNDRV_PCM_INFO_INTERLEAVED |
130 			SNDRV_PCM_INFO_PAUSE |
131 			SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
132 
133 	.dsp_arch_ops = &sof_xtensa_arch_ops,
134 };
135 EXPORT_SYMBOL_NS(sof_icl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
136 
137 const struct sof_intel_dsp_desc icl_chip_info = {
138 	/* Icelake */
139 	.cores_num = 4,
140 	.init_core_mask = 1,
141 	.host_managed_cores_mask = GENMASK(3, 0),
142 	.ipc_req = CNL_DSP_REG_HIPCIDR,
143 	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
144 	.ipc_ack = CNL_DSP_REG_HIPCIDA,
145 	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
146 	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
147 	.rom_init_timeout	= 300,
148 	.ssp_count = ICL_SSP_COUNT,
149 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
150 	.sdw_shim_base = SDW_SHIM_BASE,
151 	.sdw_alh_base = SDW_ALH_BASE,
152 	.check_sdw_irq	= hda_common_check_sdw_irq,
153 };
154 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
155