1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 *
5 * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
6 *
7 * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
8 * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
9 * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
10 * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
11 * Copyright (c) 2003	Kshitij <kshitij@ti.com>
12 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 */
14
15#include <asm-offsets.h>
16#include <config.h>
17#include <asm/system.h>
18#include <linux/linkage.h>
19#include <asm/armv7.h>
20
21/*************************************************************************
22 *
23 * Startup Code (reset vector)
24 *
25 * Do important init only if we don't start from memory!
26 * Setup memory and board specific bits prior to relocation.
27 * Relocate armboot to ram. Setup stack.
28 *
29 *************************************************************************/
30
31	.globl	reset
32	.globl	save_boot_params_ret
33	.type   save_boot_params_ret,%function
34#ifdef CONFIG_ARMV7_LPAE
35	.global	switch_to_hypervisor_ret
36#endif
37
38reset:
39	/* Allow the board to save important registers */
40	b	save_boot_params
41save_boot_params_ret:
42#ifdef CONFIG_ARMV7_LPAE
43/*
44 * check for Hypervisor support
45 */
46	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
47	and	r0, r0, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
48	cmp	r0, #(1 << CPUID_ARM_VIRT_SHIFT)
49	beq	switch_to_hypervisor
50switch_to_hypervisor_ret:
51#endif
52	/*
53	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
54	 * except if in HYP mode already
55	 */
56	mrs	r0, cpsr
57	and	r1, r0, #0x1f		@ mask mode bits
58	teq	r1, #0x1a		@ test for HYP mode
59	bicne	r0, r0, #0x1f		@ clear all mode bits
60	orrne	r0, r0, #0x13		@ set SVC mode
61	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
62	msr	cpsr,r0
63
64/*
65 * Setup vector:
66 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
67 * Continue to use ROM code vector only in OMAP4 spl)
68 */
69#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
70	/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
71	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTLR Register
72	bic	r0, #CR_V		@ V = 0
73	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTLR Register
74
75#ifdef CONFIG_HAS_VBAR
76	/* Set vector address in CP15 VBAR register */
77	ldr	r0, =_start
78	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
79#endif
80#endif
81
82	/* the mask ROM code should have PLL and others stable */
83#ifndef CONFIG_SKIP_LOWLEVEL_INIT
84#ifdef CONFIG_CPU_V7A
85	bl	cpu_init_cp15
86#endif
87#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
88	bl	cpu_init_crit
89#endif
90#endif
91
92	bl	_main
93
94/*------------------------------------------------------------------------------*/
95
96ENTRY(c_runtime_cpu_setup)
97/*
98 * If I-cache is enabled invalidate it
99 */
100#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
101	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
102	mcr     p15, 0, r0, c7, c10, 4	@ DSB
103	mcr     p15, 0, r0, c7, c5, 4	@ ISB
104#endif
105
106	bx	lr
107
108ENDPROC(c_runtime_cpu_setup)
109
110/*************************************************************************
111 *
112 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
113 *	__attribute__((weak));
114 *
115 * Stack pointer is not yet initialized at this moment
116 * Don't save anything to stack even if compiled with -O0
117 *
118 *************************************************************************/
119ENTRY(save_boot_params)
120	b	save_boot_params_ret		@ back to my caller
121ENDPROC(save_boot_params)
122	.weak	save_boot_params
123
124#ifdef CONFIG_ARMV7_LPAE
125ENTRY(switch_to_hypervisor)
126	b	switch_to_hypervisor_ret
127ENDPROC(switch_to_hypervisor)
128	.weak	switch_to_hypervisor
129#endif
130
131/*************************************************************************
132 *
133 * cpu_init_cp15
134 *
135 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
136 * CONFIG_SYS_ICACHE_OFF is defined.
137 *
138 *************************************************************************/
139ENTRY(cpu_init_cp15)
140	/*
141	 * Invalidate L1 I/D
142	 */
143	mov	r0, #0			@ set up for MCR
144	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
145	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
146	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
147	mcr     p15, 0, r0, c7, c10, 4	@ DSB
148	mcr     p15, 0, r0, c7, c5, 4	@ ISB
149
150	/*
151	 * disable MMU stuff and caches
152	 */
153	mrc	p15, 0, r0, c1, c0, 0
154	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
155	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
156	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
157	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
158#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
159	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
160#else
161	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
162#endif
163	mcr	p15, 0, r0, c1, c0, 0
164
165#ifdef CONFIG_ARM_ERRATA_716044
166	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
167	orr	r0, r0, #1 << 11	@ set bit #11
168	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
169#endif
170
171#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
172	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
173	orr	r0, r0, #1 << 4		@ set bit #4
174	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
175#endif
176
177#ifdef CONFIG_ARM_ERRATA_743622
178	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
179	orr	r0, r0, #1 << 6		@ set bit #6
180	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
181#endif
182
183#ifdef CONFIG_ARM_ERRATA_751472
184	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
185	orr	r0, r0, #1 << 11	@ set bit #11
186	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
187#endif
188#ifdef CONFIG_ARM_ERRATA_761320
189	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
190	orr	r0, r0, #1 << 21	@ set bit #21
191	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
192#endif
193
194#ifdef CONFIG_ARM_ERRATA_845369
195	mrc     p15, 0, r0, c15, c0, 1	@ read diagnostic register
196	orr     r0, r0, #1 << 22	@ set bit #22
197	mcr     p15, 0, r0, c15, c0, 1	@ write diagnostic register
198#endif
199
200	mov	r5, lr			@ Store my Caller
201	mrc	p15, 0, r1, c0, c0, 0	@ r1 has Read Main ID Register (MIDR)
202	mov	r3, r1, lsr #20		@ get variant field
203	and	r3, r3, #0xf		@ r3 has CPU variant
204	and	r4, r1, #0xf		@ r4 has CPU revision
205	mov	r2, r3, lsl #4		@ shift variant field for combined value
206	orr	r2, r4, r2		@ r2 has combined CPU variant + revision
207
208/* Early stack for ERRATA that needs into call C code */
209#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
210	ldr	r0, =(CONFIG_SPL_STACK)
211#else
212	ldr	r0, =(CONFIG_SYS_INIT_SP_ADDR)
213#endif
214	bic	r0, r0, #7	/* 8-byte alignment for ABI compliance */
215	mov	sp, r0
216
217#ifdef CONFIG_ARM_ERRATA_798870
218	cmp	r2, #0x30		@ Applies to lower than R3p0
219	bge	skip_errata_798870      @ skip if not affected rev
220	cmp	r2, #0x20		@ Applies to including and above R2p0
221	blt	skip_errata_798870      @ skip if not affected rev
222
223	mrc	p15, 1, r0, c15, c0, 0  @ read l2 aux ctrl reg
224	orr	r0, r0, #1 << 7         @ Enable hazard-detect timeout
225	push	{r1-r5}			@ Save the cpu info registers
226	bl	v7_arch_cp15_set_l2aux_ctrl
227	isb				@ Recommended ISB after l2actlr update
228	pop	{r1-r5}			@ Restore the cpu info - fall through
229skip_errata_798870:
230#endif
231
232#ifdef CONFIG_ARM_ERRATA_801819
233	cmp	r2, #0x24		@ Applies to lt including R2p4
234	bgt	skip_errata_801819      @ skip if not affected rev
235	cmp	r2, #0x20		@ Applies to including and above R2p0
236	blt	skip_errata_801819      @ skip if not affected rev
237	mrc	p15, 0, r0, c0, c0, 6	@ pick up REVIDR reg
238	and	r0, r0, #1 << 3		@ check REVIDR[3]
239	cmp	r0, #1 << 3
240	beq	skip_errata_801819	@ skip erratum if REVIDR[3] is set
241
242	mrc	p15, 0, r0, c1, c0, 1	@ read auxilary control register
243	orr	r0, r0, #3 << 27	@ Disables streaming. All write-allocate
244					@ lines allocate in the L1 or L2 cache.
245	orr	r0, r0, #3 << 25	@ Disables streaming. All write-allocate
246					@ lines allocate in the L1 cache.
247	push	{r1-r5}			@ Save the cpu info registers
248	bl	v7_arch_cp15_set_acr
249	pop	{r1-r5}			@ Restore the cpu info - fall through
250skip_errata_801819:
251#endif
252
253#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715
254	mrc	p15, 0, r0, c1, c0, 1	@ read auxilary control register
255	orr	r0, r0, #1 << 0		@ Enable invalidates of BTB
256	push	{r1-r5}			@ Save the cpu info registers
257	bl	v7_arch_cp15_set_acr
258	pop	{r1-r5}			@ Restore the cpu info - fall through
259#endif
260
261#ifdef CONFIG_ARM_ERRATA_454179
262	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
263
264	cmp	r2, #0x21		@ Only on < r2p1
265	orrlt	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
266
267	push	{r1-r5}			@ Save the cpu info registers
268	bl	v7_arch_cp15_set_acr
269	pop	{r1-r5}			@ Restore the cpu info - fall through
270#endif
271
272#if defined(CONFIG_ARM_ERRATA_430973) || defined (CONFIG_ARM_CORTEX_A8_CVE_2017_5715)
273	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
274
275#ifdef CONFIG_ARM_CORTEX_A8_CVE_2017_5715
276	orr	r0, r0, #(0x1 << 6)	@ Set IBE bit always to enable OS WA
277#else
278	cmp	r2, #0x21		@ Only on < r2p1
279	orrlt	r0, r0, #(0x1 << 6)	@ Set IBE bit
280#endif
281	push	{r1-r5}			@ Save the cpu info registers
282	bl	v7_arch_cp15_set_acr
283	pop	{r1-r5}			@ Restore the cpu info - fall through
284#endif
285
286#ifdef CONFIG_ARM_ERRATA_621766
287	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
288
289	cmp	r2, #0x21		@ Only on < r2p1
290	orrlt	r0, r0, #(0x1 << 5)	@ Set L1NEON bit
291
292	push	{r1-r5}			@ Save the cpu info registers
293	bl	v7_arch_cp15_set_acr
294	pop	{r1-r5}			@ Restore the cpu info - fall through
295#endif
296
297#ifdef CONFIG_ARM_ERRATA_725233
298	mrc	p15, 1, r0, c9, c0, 2	@ Read L2ACR
299
300	cmp	r2, #0x21		@ Only on < r2p1 (Cortex A8)
301	orrlt	r0, r0, #(0x1 << 27)	@ L2 PLD data forwarding disable
302
303	push	{r1-r5}			@ Save the cpu info registers
304	bl	v7_arch_cp15_set_l2aux_ctrl
305	pop	{r1-r5}			@ Restore the cpu info - fall through
306#endif
307
308#ifdef CONFIG_ARM_ERRATA_852421
309	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
310	orr	r0, r0, #1 << 24	@ set bit #24
311	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
312#endif
313
314#ifdef CONFIG_ARM_ERRATA_852423
315	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
316	orr	r0, r0, #1 << 12	@ set bit #12
317	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
318#endif
319
320	mov	pc, r5			@ back to my caller
321ENDPROC(cpu_init_cp15)
322
323#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
324	!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
325/*************************************************************************
326 *
327 * CPU_init_critical registers
328 *
329 * setup important registers
330 * setup memory timing
331 *
332 *************************************************************************/
333ENTRY(cpu_init_crit)
334	/*
335	 * Jump to board specific initialization...
336	 * The Mask ROM will have already initialized
337	 * basic memory. Go here to bump up clock rate and handle
338	 * wake up conditions.
339	 */
340	b	lowlevel_init		@ go setup pll,mux,memory
341ENDPROC(cpu_init_crit)
342#endif
343