1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * arch/arm/include/asm/io.h
4 *
5 * Copyright (C) 1996-2000 Russell King
6 *
7 * Modifications:
8 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
9 * constant addresses and variable addresses.
10 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
11 * specific IO header files.
12 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
13 * 04-Apr-1999 PJB Added check_signature.
14 * 12-Dec-1999 RMK More cleanups
15 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
16 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
17 */
18 #ifndef __ASM_ARM_IO_H
19 #define __ASM_ARM_IO_H
20
21 #ifdef __KERNEL__
22
23 #include <linux/string.h>
24 #include <linux/types.h>
25 #include <asm/byteorder.h>
26 #include <asm/memory.h>
27 #include <asm-generic/pci_iomap.h>
28
29 /*
30 * ISA I/O bus memory addresses are 1:1 with the physical address.
31 */
32 #define isa_virt_to_bus virt_to_phys
33 #define isa_bus_to_virt phys_to_virt
34
35 /*
36 * Atomic MMIO-wide IO modify
37 */
38 extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
39 extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
40
41 /*
42 * Generic IO read/write. These perform native-endian accesses. Note
43 * that some architectures will want to re-define __raw_{read,write}w.
44 */
45 void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
46 void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
47 void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
48
49 void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
50 void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
51 void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
52
53 #if __LINUX_ARM_ARCH__ < 6
54 /*
55 * Half-word accesses are problematic with RiscPC due to limitations of
56 * the bus. Rather than special-case the machine, just let the compiler
57 * generate the access for CPUs prior to ARMv6.
58 */
59 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
60 #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
61 #else
62 /*
63 * When running under a hypervisor, we want to avoid I/O accesses with
64 * writeback addressing modes as these incur a significant performance
65 * overhead (the address generation must be emulated in software).
66 */
67 #define __raw_writew __raw_writew
__raw_writew(u16 val,volatile void __iomem * addr)68 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
69 {
70 asm volatile("strh %1, %0"
71 : : "Q" (*(volatile u16 __force *)addr), "r" (val));
72 }
73
74 #define __raw_readw __raw_readw
__raw_readw(const volatile void __iomem * addr)75 static inline u16 __raw_readw(const volatile void __iomem *addr)
76 {
77 u16 val;
78 asm volatile("ldrh %0, %1"
79 : "=r" (val)
80 : "Q" (*(volatile u16 __force *)addr));
81 return val;
82 }
83 #endif
84
85 #define __raw_writeb __raw_writeb
__raw_writeb(u8 val,volatile void __iomem * addr)86 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
87 {
88 asm volatile("strb %1, %0"
89 : : "Qo" (*(volatile u8 __force *)addr), "r" (val));
90 }
91
92 #define __raw_writel __raw_writel
__raw_writel(u32 val,volatile void __iomem * addr)93 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
94 {
95 asm volatile("str %1, %0"
96 : : "Qo" (*(volatile u32 __force *)addr), "r" (val));
97 }
98
99 #define __raw_readb __raw_readb
__raw_readb(const volatile void __iomem * addr)100 static inline u8 __raw_readb(const volatile void __iomem *addr)
101 {
102 u8 val;
103 asm volatile("ldrb %0, %1"
104 : "=r" (val)
105 : "Qo" (*(volatile u8 __force *)addr));
106 return val;
107 }
108
109 #define __raw_readl __raw_readl
__raw_readl(const volatile void __iomem * addr)110 static inline u32 __raw_readl(const volatile void __iomem *addr)
111 {
112 u32 val;
113 asm volatile("ldr %0, %1"
114 : "=r" (val)
115 : "Qo" (*(volatile u32 __force *)addr));
116 return val;
117 }
118
119 /*
120 * Architecture ioremap implementation.
121 */
122 #define MT_DEVICE 0
123 #define MT_DEVICE_NONSHARED 1
124 #define MT_DEVICE_CACHED 2
125 #define MT_DEVICE_WC 3
126 /*
127 * types 4 onwards can be found in asm/mach/map.h and are undefined
128 * for ioremap
129 */
130
131 /*
132 * __arm_ioremap takes CPU physical address.
133 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
134 * The _caller variety takes a __builtin_return_address(0) value for
135 * /proc/vmalloc to use - and should only be used in non-inline functions.
136 */
137 extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
138 void *);
139 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
140 extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
141 void __arm_iomem_set_ro(void __iomem *ptr, size_t size);
142 extern void __iounmap(volatile void __iomem *addr);
143
144 extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
145 unsigned int, void *);
146 extern void (*arch_iounmap)(volatile void __iomem *);
147
148 /*
149 * Bad read/write accesses...
150 */
151 extern void __readwrite_bug(const char *fn);
152
153 /*
154 * A typesafe __io() helper
155 */
__typesafe_io(unsigned long addr)156 static inline void __iomem *__typesafe_io(unsigned long addr)
157 {
158 return (void __iomem *)addr;
159 }
160
161 #define IOMEM(x) ((void __force __iomem *)(x))
162
163 /* IO barriers */
164 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
165 #include <asm/barrier.h>
166 #define __iormb() rmb()
167 #define __iowmb() wmb()
168 #else
169 #define __iormb() do { } while (0)
170 #define __iowmb() do { } while (0)
171 #endif
172
173 /* PCI fixed i/o mapping */
174 #define PCI_IO_VIRT_BASE 0xfee00000
175 #define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
176
177 #if defined(CONFIG_PCI)
178 void pci_ioremap_set_mem_type(int mem_type);
179 #else
pci_ioremap_set_mem_type(int mem_type)180 static inline void pci_ioremap_set_mem_type(int mem_type) {}
181 #endif
182
183 extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
184
185 /*
186 * PCI configuration space mapping function.
187 *
188 * The PCI specification does not allow configuration write
189 * transactions to be posted. Add an arch specific
190 * pci_remap_cfgspace() definition that is implemented
191 * through strongly ordered memory mappings.
192 */
193 #define pci_remap_cfgspace pci_remap_cfgspace
194 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);
195 /*
196 * Now, pick up the machine-defined IO definitions
197 */
198 #ifdef CONFIG_NEED_MACH_IO_H
199 #include <mach/io.h>
200 #elif defined(CONFIG_PCI)
201 #define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
202 #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
203 #else
204 #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
205 #endif
206
207 /*
208 * This is the limit of PC card/PCI/ISA IO space, which is by default
209 * 64K if we have PC card, PCI or ISA support. Otherwise, default to
210 * zero to prevent ISA/PCI drivers claiming IO space (and potentially
211 * oopsing.)
212 *
213 * Only set this larger if you really need inb() et.al. to operate over
214 * a larger address space. Note that SOC_COMMON ioremaps each sockets
215 * IO space area, and so inb() et.al. must be defined to operate as per
216 * readb() et.al. on such platforms.
217 */
218 #ifndef IO_SPACE_LIMIT
219 #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
220 #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
221 #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
222 #define IO_SPACE_LIMIT ((resource_size_t)0xffff)
223 #else
224 #define IO_SPACE_LIMIT ((resource_size_t)0)
225 #endif
226 #endif
227
228 /*
229 * IO port access primitives
230 * -------------------------
231 *
232 * The ARM doesn't have special IO access instructions; all IO is memory
233 * mapped. Note that these are defined to perform little endian accesses
234 * only. Their primary purpose is to access PCI and ISA peripherals.
235 *
236 * Note that for a big endian machine, this implies that the following
237 * big endian mode connectivity is in place, as described by numerous
238 * ARM documents:
239 *
240 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
241 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
242 *
243 * The machine specific io.h include defines __io to translate an "IO"
244 * address to a memory address.
245 *
246 * Note that we prevent GCC re-ordering or caching values in expressions
247 * by introducing sequence points into the in*() definitions. Note that
248 * __raw_* do not guarantee this behaviour.
249 *
250 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
251 */
252 #ifdef __io
253 #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
254 #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
255 cpu_to_le16(v),__io(p)); })
256 #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
257 cpu_to_le32(v),__io(p)); })
258
259 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
260 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
261 __raw_readw(__io(p))); __iormb(); __v; })
262 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
263 __raw_readl(__io(p))); __iormb(); __v; })
264
265 #define outsb(p,d,l) __raw_writesb(__io(p),d,l)
266 #define outsw(p,d,l) __raw_writesw(__io(p),d,l)
267 #define outsl(p,d,l) __raw_writesl(__io(p),d,l)
268
269 #define insb(p,d,l) __raw_readsb(__io(p),d,l)
270 #define insw(p,d,l) __raw_readsw(__io(p),d,l)
271 #define insl(p,d,l) __raw_readsl(__io(p),d,l)
272 #endif
273
274 /*
275 * String version of IO memory access ops:
276 */
277 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
278 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
279 extern void _memset_io(volatile void __iomem *, int, size_t);
280
281 /*
282 * Memory access primitives
283 * ------------------------
284 *
285 * These perform PCI memory accesses via an ioremap region. They don't
286 * take an address as such, but a cookie.
287 *
288 * Again, these are defined to perform little endian accesses. See the
289 * IO port primitives for more information.
290 */
291 #ifndef readl
292 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
293 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
294 __raw_readw(c)); __r; })
295 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
296 __raw_readl(c)); __r; })
297
298 #define writeb_relaxed(v,c) __raw_writeb(v,c)
299 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
300 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
301
302 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
303 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
304 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
305
306 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
307 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
308 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
309
310 #define readsb(p,d,l) __raw_readsb(p,d,l)
311 #define readsw(p,d,l) __raw_readsw(p,d,l)
312 #define readsl(p,d,l) __raw_readsl(p,d,l)
313
314 #define writesb(p,d,l) __raw_writesb(p,d,l)
315 #define writesw(p,d,l) __raw_writesw(p,d,l)
316 #define writesl(p,d,l) __raw_writesl(p,d,l)
317
318 #ifndef __ARMBE__
memset_io(volatile void __iomem * dst,unsigned c,size_t count)319 static inline void memset_io(volatile void __iomem *dst, unsigned c,
320 size_t count)
321 {
322 extern void mmioset(void *, unsigned int, size_t);
323 mmioset((void __force *)dst, c, count);
324 }
325 #define memset_io(dst,c,count) memset_io(dst,c,count)
326
memcpy_fromio(void * to,const volatile void __iomem * from,size_t count)327 static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
328 size_t count)
329 {
330 extern void mmiocpy(void *, const void *, size_t);
331 mmiocpy(to, (const void __force *)from, count);
332 }
333 #define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count)
334
memcpy_toio(volatile void __iomem * to,const void * from,size_t count)335 static inline void memcpy_toio(volatile void __iomem *to, const void *from,
336 size_t count)
337 {
338 extern void mmiocpy(void *, const void *, size_t);
339 mmiocpy((void __force *)to, from, count);
340 }
341 #define memcpy_toio(to,from,count) memcpy_toio(to,from,count)
342
343 #else
344 #define memset_io(c,v,l) _memset_io(c,(v),(l))
345 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
346 #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
347 #endif
348
349 #endif /* readl */
350
351 /*
352 * ioremap() and friends.
353 *
354 * ioremap() takes a resource address, and size. Due to the ARM memory
355 * types, it is important to use the correct ioremap() function as each
356 * mapping has specific properties.
357 *
358 * Function Memory type Cacheability Cache hint
359 * ioremap() Device n/a n/a
360 * ioremap_cache() Normal Writeback Read allocate
361 * ioremap_wc() Normal Non-cacheable n/a
362 * ioremap_wt() Normal Non-cacheable n/a
363 *
364 * All device mappings have the following properties:
365 * - no access speculation
366 * - no repetition (eg, on return from an exception)
367 * - number, order and size of accesses are maintained
368 * - unaligned accesses are "unpredictable"
369 * - writes may be delayed before they hit the endpoint device
370 *
371 * All normal memory mappings have the following properties:
372 * - reads can be repeated with no side effects
373 * - repeated reads return the last value written
374 * - reads can fetch additional locations without side effects
375 * - writes can be repeated (in certain cases) with no side effects
376 * - writes can be merged before accessing the target
377 * - unaligned accesses can be supported
378 * - ordering is not guaranteed without explicit dependencies or barrier
379 * instructions
380 * - writes may be delayed before they hit the endpoint memory
381 *
382 * The cache hint is only a performance hint: CPUs may alias these hints.
383 * Eg, a CPU not implementing read allocate but implementing write allocate
384 * will provide a write allocate mapping instead.
385 */
386 void __iomem *ioremap(resource_size_t res_cookie, size_t size);
387 #define ioremap ioremap
388
389 /*
390 * Do not use ioremap_cache for mapping memory. Use memremap instead.
391 */
392 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
393 #define ioremap_cache ioremap_cache
394
395 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
396 #define ioremap_wc ioremap_wc
397 #define ioremap_wt ioremap_wc
398
399 void iounmap(volatile void __iomem *iomem_cookie);
400 #define iounmap iounmap
401
402 void *arch_memremap_wb(phys_addr_t phys_addr, size_t size);
403 #define arch_memremap_wb arch_memremap_wb
404
405 /*
406 * io{read,write}{16,32}be() macros
407 */
408 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
409 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
410
411 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
412 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
413
414 #ifndef ioport_map
415 #define ioport_map ioport_map
416 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
417 #endif
418 #ifndef ioport_unmap
419 #define ioport_unmap ioport_unmap
420 extern void ioport_unmap(void __iomem *addr);
421 #endif
422
423 struct pci_dev;
424
425 #define pci_iounmap pci_iounmap
426 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
427
428 /*
429 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
430 * access
431 */
432 #define xlate_dev_mem_ptr(p) __va(p)
433
434 #include <asm-generic/io.h>
435
436 #ifdef CONFIG_MMU
437 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
438 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
439 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
440 #endif
441
442 /*
443 * Register ISA memory and port locations for glibc iopl/inb/outb
444 * emulation.
445 */
446 extern void register_isa_ports(unsigned int mmio, unsigned int io,
447 unsigned int io_shift);
448
449 #endif /* __KERNEL__ */
450 #endif /* __ASM_ARM_IO_H */
451