1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/mt7620-clk.h>
3#include <dt-bindings/reset/mt7620-reset.h>
4
5/ {
6	#address-cells = <1>;
7	#size-cells = <1>;
8	compatible = "mediatek,mt7620-soc";
9
10	cpus {
11		#address-cells = <1>;
12		#size-cells = <0>;
13
14		cpu@0 {
15			compatible = "mti,mips24KEc";
16			device_type = "cpu";
17			reg = <0>;
18		};
19	};
20
21	clk48m: clk48m@0 {
22		compatible = "fixed-clock";
23
24		clock-frequency = <48000000>;
25
26		#clock-cells = <0>;
27	};
28
29	sysc: sysc@10000000 {
30		compatible = "mediatek,mt7620-sysc";
31		reg = <0x10000000 0x100>;
32	};
33
34	clkctrl: clkctrl@10000030 {
35		compatible = "mediatek,mt7620-clk";
36		mediatek,sysc = <&sysc>;
37
38		#clock-cells = <1>;
39	};
40
41	rstctrl: rstctrl@10000034 {
42		compatible = "mediatek,mtmips-reset";
43		reg = <0x10000034 0x4>;
44		#reset-cells = <1>;
45	};
46
47	reboot: resetctl-reboot {
48		compatible = "resetctl-reboot";
49
50		resets = <&rstctrl SYS_RST>;
51		reset-names = "sysreset";
52	};
53
54	uartfull: uartfull@10000500 {
55		compatible = "mediatek,mt7620-uart";
56		reg = <10000500 0x100>;
57
58		pinctrl-names = "default";
59		pinctrl-0 = <&uartf_gpio_pins>;
60
61		clocks = <&clkctrl CLK_UARTF>;
62
63		resets = <&rstctrl UARTF_RST>;
64		reset-names = "uartf";
65
66		clock-frequency = <40000000>;
67
68		status = "disabled";
69	};
70
71	uartlite: uartlite@10000c00 {
72		compatible = "mediatek,mt7620-uart";
73		reg = <0x10000c00 0x100>;
74
75		pinctrl-names = "default";
76		pinctrl-0 = <&uartl_pins>;
77
78		clocks = <&clkctrl CLK_UARTL>;
79
80		resets = <&rstctrl UARTL_RST>;
81		reset-names = "uartl";
82
83		clock-frequency = <40000000>;
84	};
85
86	pinctrl: pinctrl@10000060 {
87		compatible = "mediatek,mt7620-pinctrl";
88		reg = <0x10000060 0x4>;
89
90		pinctrl-names = "default";
91		pinctrl-0 = <&state_default>;
92
93		state_default: pin_state {
94			sutif_pins {
95				groups = "sutif";
96				function = "none";
97			};
98		};
99
100		nand_pins: nand_pins {
101			groups = "nand";
102			function = "nand";
103		};
104
105		sd_pins: sd_pins {
106			groups = "nand";
107			function = "sd";
108		};
109
110		spi_single_pins: spi_single_pins {
111			groups = "spi";
112			function = "spi";
113		};
114
115		spi_dual_pins: spi_dual_pins {
116			spi_master_pins {
117				groups = "spi";
118				function = "spi";
119			};
120
121			spi_cs1_pin {
122				groups = "spi cs1";
123				function = "spi cs1";
124			};
125		};
126
127		uartl_pins: uartl_pins {
128			groups = "uartl";
129			function = "uartl";
130		};
131
132		uartf_pins: uartf_pins {
133			groups = "uartf";
134			function = "uartf";
135		};
136
137		uartf_pcm_pins: uartf_pcm_pins {
138			groups = "uartf";
139			function = "uartf pcm";
140		};
141
142		uartf_i2s_pins: uartf_i2s_pins {
143			groups = "uartf";
144			function = "i2s uartf";
145		};
146
147		uartf_gpio_pins: uartf_gpio_pins {
148			groups = "uartf";
149			function = "uartf gpio";
150		};
151	};
152
153	watchdog: watchdog@10000120 {
154		compatible = "mediatek,mt7620-wdt";
155		reg = <0x10000120 0x10>;
156
157		resets = <&rstctrl TIMER_RST>;
158		reset-names = "wdt";
159	};
160
161	gpio0: gpio0@10000600 {
162		compatible = "mediatek,mt7620-gpio";
163		reg = <0x10000600 0x34>;
164
165		resets = <&rstctrl PIO_RST>;
166		reset-names = "pio";
167
168		mediatek,bank-name = "PIOA";
169		mediatek,gpio-num = <24>;
170		mediatek,register-map = <0x20 0x24 0x2c 0x30>;
171
172		gpio-controller;
173		#gpio-cells = <2>;
174	};
175
176	gpio1: gpio1@10000638 {
177		compatible = "mediatek,mt7620-gpio";
178		reg = <0x10000638 0x24>;
179
180		resets = <&rstctrl PIO_RST>;
181		reset-names = "pio";
182
183		mediatek,bank-name = "PIOB";
184		mediatek,gpio-num = <16>;
185		mediatek,register-map = <0x10 0x14 0x1c 0x20>;
186
187		gpio-controller;
188		#gpio-cells = <2>;
189	};
190
191	gpio2: gpio2@10000660 {
192		compatible = "mediatek,mt7620-gpio";
193		reg = <0x10000660 0x24>;
194
195		resets = <&rstctrl PIO_RST>;
196		reset-names = "pio";
197
198		mediatek,bank-name = "PIOC";
199		mediatek,gpio-num = <32>;
200		mediatek,register-map = <0x10 0x14 0x1c 0x20>;
201
202		gpio-controller;
203		#gpio-cells = <2>;
204	};
205
206	gpio3: gpio3@10000688 {
207		compatible = "mediatek,mt7620-gpio";
208		reg = <0x10000688 0x24>;
209
210		resets = <&rstctrl PIO_RST>;
211		reset-names = "pio";
212
213		mediatek,bank-name = "PIOD";
214		mediatek,gpio-num = <1>;
215		mediatek,register-map = <0x10 0x14 0x1c 0x20>;
216
217		gpio-controller;
218		#gpio-cells = <2>;
219	};
220
221	spi0: spi@10000b00 {
222		compatible = "mediatek,mt7620-spi";
223		reg = <0x10000b00 0x100>;
224
225		pinctrl-names = "default";
226		pinctrl-0 = <&spi_single_pins>;
227
228		resets = <&rstctrl SPI_RST>;
229		reset-names = "spi";
230
231		#address-cells = <1>;
232		#size-cells = <0>;
233
234		clocks = <&clkctrl CLK_SPI>;
235	};
236
237	eth: eth@10100000 {
238		compatible = "mediatek,mt7620-eth";
239		reg = <0x10100000 0x10000
240		       0x10110000 0x8000>;
241		reg-names = "fe", "esw";
242
243		mediatek,sysc = <&sysc>;
244
245		resets = <&rstctrl EPHY_RST>,
246			 <&rstctrl ESW_RST>,
247			 <&rstctrl FE_RST>;
248		reset-names = "ephy", "esw", "fe";
249
250		clocks = <&clkctrl CLK_EPHY>,
251			 <&clkctrl CLK_ESW>,
252			 <&clkctrl CLK_FE>;
253		clock-names = "ephy", "esw", "fe";
254
255		status = "disabled";
256	};
257
258	usb_phy: mt7620-usb-phy {
259		compatible = "mediatek,mt7620-usbphy";
260
261		#phy-cells = <0>;
262
263		mediatek,sysc = <&sysc>;
264
265		clocks = <&clkctrl CLK_UPHY_48M>, <&clkctrl CLK_UPHY_12M>;
266		clock-names = "uphy48m", "uphy12m";
267
268		resets = <&rstctrl UHST_RST>, <&rstctrl UDEV_RST>;
269		reset-names = "uhst", "udev";
270	};
271
272	ehci@101c0000 {
273		compatible = "generic-ehci";
274		reg = <0x101c0000 0x1000>;
275
276		phys = <&usb_phy>;
277		phy-names = "usb";
278	};
279
280	mmc: mmc@10130000 {
281		compatible = "mediatek,mt7620-mmc";
282		reg = <0x10130000 0x4000>;
283		builtin-cd = <1>;
284		r_smpl = <1>;
285
286		pinctrl-names = "default";
287		pinctrl-0 = <&sd_pins>;
288
289		clocks = <&clk48m>, <&clkctrl CLK_SDHC>;
290		clock-names = "source", "hclk";
291
292		resets = <&rstctrl SDHC_RST>;
293
294		status = "disabled";
295	};
296};
297