1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Device Tree Source for the Socrates board (MPC8544).
4 *
5 * Copyright (c) 2008 Emcraft Systems.
6 * Sergei Poselenov, <sposelenov@emcraft.com>
7 *
8 */
9
10/dts-v1/;
11
12/ {
13	model = "abb,socrates";
14	compatible = "abb,socrates";
15	#address-cells = <1>;
16	#size-cells = <1>;
17
18	aliases {
19		ethernet0 = &enet0;
20		ethernet1 = &enet1;
21		serial0 = &serial0;
22		serial1 = &serial1;
23		pci0 = &pci0;
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		PowerPC,8544@0 {
31			device_type = "cpu";
32			reg = <0>;
33			d-cache-line-size = <32>;
34			i-cache-line-size = <32>;
35			d-cache-size = <0x8000>;	// L1, 32K
36			i-cache-size = <0x8000>;	// L1, 32K
37			timebase-frequency = <0>;
38			bus-frequency = <0>;
39			clock-frequency = <0>;
40			next-level-cache = <&L2>;
41		};
42	};
43
44	memory {
45		device_type = "memory";
46		reg = <0x00000000 0x00000000>;	// Filled in by U-Boot
47	};
48
49	soc8544@e0000000 {
50		#address-cells = <1>;
51		#size-cells = <1>;
52		device_type = "soc";
53
54		ranges = <0x00000000 0xe0000000 0x00100000>;
55		bus-frequency = <0>;		// Filled in by U-Boot
56		compatible = "fsl,mpc8544-immr", "simple-bus";
57
58		ecm-law@0 {
59			compatible = "fsl,ecm-law";
60			reg = <0x0 0x1000>;
61			fsl,num-laws = <10>;
62		};
63
64		ecm@1000 {
65			compatible = "fsl,mpc8544-ecm", "fsl,ecm";
66			reg = <0x1000 0x1000>;
67			interrupts = <17 2>;
68			interrupt-parent = <&mpic>;
69		};
70
71		memory-controller@2000 {
72			compatible = "fsl,mpc8544-memory-controller";
73			reg = <0x2000 0x1000>;
74			interrupt-parent = <&mpic>;
75			interrupts = <18 2>;
76		};
77
78		L2: l2-cache-controller@20000 {
79			compatible = "fsl,mpc8544-l2-cache-controller";
80			reg = <0x20000 0x1000>;
81			cache-line-size = <32>;
82			cache-size = <0x40000>;	// L2, 256K
83			interrupt-parent = <&mpic>;
84			interrupts = <16 2>;
85		};
86
87		i2c@3000 {
88			#address-cells = <1>;
89			#size-cells = <0>;
90			cell-index = <0>;
91			compatible = "fsl,mpc8544-i2c", "fsl-i2c";
92			reg = <0x3000 0x100>;
93			interrupts = <43 2>;
94			interrupt-parent = <&mpic>;
95			fsl,preserve-clocking;
96
97			dtt@28 {
98				compatible = "winbond,w83782d";
99				reg = <0x28>;
100			};
101			rtc@32 {
102				compatible = "epson,rx8025";
103				reg = <0x32>;
104				interrupts = <7 1>;
105				interrupt-parent = <&mpic>;
106			};
107			dtt@4c {
108				compatible = "dallas,ds75";
109				reg = <0x4c>;
110			};
111			ts@4a {
112				compatible = "ti,tsc2003";
113				reg = <0x4a>;
114				interrupt-parent = <&mpic>;
115				interrupts = <8 1>;
116			};
117		};
118
119		i2c@3100 {
120			#address-cells = <1>;
121			#size-cells = <0>;
122			cell-index = <1>;
123			compatible = "fsl,mpc8544-i2c", "fsl-i2c";
124			reg = <0x3100 0x100>;
125			interrupts = <43 2>;
126			interrupt-parent = <&mpic>;
127			fsl,preserve-clocking;
128		};
129
130		enet0: ethernet@24000 {
131			#address-cells = <1>;
132			#size-cells = <1>;
133			cell-index = <0>;
134			device_type = "network";
135			model = "eTSEC";
136			compatible = "gianfar";
137			reg = <0x24000 0x1000>;
138			ranges = <0x0 0x24000 0x1000>;
139			local-mac-address = [ 00 00 00 00 00 00 ];
140			interrupts = <29 2 30 2 34 2>;
141			interrupt-parent = <&mpic>;
142			phy-handle = <&phy0>;
143			tbi-handle = <&tbi0>;
144			phy-connection-type = "rgmii-id";
145
146			mdio@520 {
147				#address-cells = <1>;
148				#size-cells = <0>;
149				compatible = "fsl,gianfar-mdio";
150				reg = <0x520 0x20>;
151
152				phy0: ethernet-phy@0 {
153					interrupt-parent = <&mpic>;
154					interrupts = <0 1>;
155					reg = <0>;
156				};
157				phy1: ethernet-phy@1 {
158					interrupt-parent = <&mpic>;
159					interrupts = <0 1>;
160					reg = <1>;
161				};
162				tbi0: tbi-phy@11 {
163					reg = <0x11>;
164				};
165			};
166		};
167
168		enet1: ethernet@26000 {
169			#address-cells = <1>;
170			#size-cells = <1>;
171			cell-index = <1>;
172			device_type = "network";
173			model = "eTSEC";
174			compatible = "gianfar";
175			reg = <0x26000 0x1000>;
176			ranges = <0x0 0x26000 0x1000>;
177			local-mac-address = [ 00 00 00 00 00 00 ];
178			interrupts = <31 2 32 2 33 2>;
179			interrupt-parent = <&mpic>;
180			phy-handle = <&phy1>;
181			tbi-handle = <&tbi1>;
182			phy-connection-type = "rgmii-id";
183
184			mdio@520 {
185				#address-cells = <1>;
186				#size-cells = <0>;
187				compatible = "fsl,gianfar-tbi";
188				reg = <0x520 0x20>;
189
190				tbi1: tbi-phy@11 {
191					reg = <0x11>;
192				};
193			};
194		};
195
196		serial0: serial@4500 {
197			cell-index = <0>;
198			device_type = "serial";
199			compatible = "fsl,ns16550", "ns16550";
200			reg = <0x4500 0x100>;
201			clock-frequency = <0>;
202			interrupts = <42 2>;
203			interrupt-parent = <&mpic>;
204		};
205
206		serial1: serial@4600 {
207			cell-index = <1>;
208			device_type = "serial";
209			compatible = "fsl,ns16550", "ns16550";
210			reg = <0x4600 0x100>;
211			clock-frequency = <0>;
212			interrupts = <42 2>;
213			interrupt-parent = <&mpic>;
214		};
215
216		global-utilities@e0000 {	//global utilities block
217			compatible = "fsl,mpc8548-guts";
218			reg = <0xe0000 0x1000>;
219			fsl,has-rstcr;
220		};
221
222		mpic: pic@40000 {
223			interrupt-controller;
224			#address-cells = <0>;
225			#interrupt-cells = <2>;
226			reg = <0x40000 0x40000>;
227			compatible = "chrp,open-pic";
228			device_type = "open-pic";
229		};
230	};
231
232
233	localbus {
234		compatible = "fsl,mpc8544-localbus",
235		             "fsl,pq3-localbus",
236			     "simple-bus";
237		#address-cells = <2>;
238		#size-cells = <1>;
239		reg = <0xe0005000 0x40>;
240		interrupt-parent = <&mpic>;
241		interrupts = <19 2>;
242
243		ranges = <0 0 0xfc000000 0x04000000
244			  2 0 0xc8000000 0x04000000
245			  3 0 0xc0000000 0x00100000
246			>; /* Overwritten by U-Boot */
247
248		nor_flash@0,0 {
249			compatible = "amd,s29gl256n", "cfi-flash";
250			bank-width = <2>;
251			reg = <0x0 0x000000 0x4000000>;
252			#address-cells = <1>;
253			#size-cells = <1>;
254			partition@0 {
255				label = "kernel";
256				reg = <0x0 0x1e0000>;
257				read-only;
258			};
259			partition@1e0000 {
260				label = "dtb";
261				reg = <0x1e0000 0x20000>;
262			};
263			partition@200000 {
264				label = "root";
265				reg = <0x200000 0x200000>;
266			};
267			partition@400000 {
268				label = "user";
269				reg = <0x400000 0x3b80000>;
270			};
271			partition@3f80000 {
272				label = "env";
273				reg = <0x3f80000 0x40000>;
274				read-only;
275			};
276			partition@3fc0000 {
277				label = "u-boot";
278				reg = <0x3fc0000 0x40000>;
279				read-only;
280			};
281		};
282
283		display@2,0 {
284			compatible = "fujitsu,lime";
285			reg = <2 0x0 0x4000000>;
286			interrupt-parent = <&mpic>;
287			interrupts = <6 1>;
288		};
289
290		fpga_pic: fpga-pic@3,10 {
291			compatible = "abb,socrates-fpga-pic";
292			reg = <3 0x10 0x10>;
293			interrupt-controller;
294			/* IRQs 2, 10, 11, active low, level-sensitive */
295			interrupts = <2 1 10 1 11 1>;
296			interrupt-parent = <&mpic>;
297			#interrupt-cells = <3>;
298		};
299
300		spi@3,60 {
301			compatible = "abb,socrates-spi";
302			reg = <3 0x60 0x10>;
303			interrupts = <8 4 0>;	// number, type, routing
304			interrupt-parent = <&fpga_pic>;
305		};
306
307		nand@3,70 {
308			compatible = "abb,socrates-nand";
309			reg = <3 0x70 0x04>;
310			bank-width = <1>;
311			#address-cells = <1>;
312			#size-cells = <1>;
313			data@0 {
314				label = "data";
315				reg = <0x0 0x40000000>;
316			};
317		};
318
319		can@3,100 {
320			compatible = "philips,sja1000";
321			reg = <3 0x100 0x80>;
322			interrupts = <2 8 1>;	// number, type, routing
323			interrupt-parent = <&fpga_pic>;
324		};
325	};
326
327	pci0: pci@e0008000 {
328		#interrupt-cells = <1>;
329		#size-cells = <2>;
330		#address-cells = <3>;
331		compatible = "fsl,mpc8540-pci";
332		device_type = "pci";
333		reg = <0xe0008000 0x1000>;
334		clock-frequency = <66666666>;
335
336		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
337		interrupt-map = <
338				/* IDSEL 0x11 */
339				 0x8800 0x0 0x0 1 &mpic 5 1
340				/* IDSEL 0x12 */
341				 0x9000 0x0 0x0 1 &mpic 4 1>;
342		interrupt-parent = <&mpic>;
343		interrupts = <24 2>;
344		bus-range = <0x0 0x0>;
345		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
346			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
347	};
348
349};
350