1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * arch/sh/kernel/cpu/sh2a/opcode_helper.c
4  *
5  * Helper for the SH-2A 32-bit opcodes.
6  *
7  *  Copyright (C) 2007  Paul Mundt
8  */
9 #include <linux/kernel.h>
10 
11 /*
12  * Instructions on SH are generally fixed at 16-bits, however, SH-2A
13  * introduces some 32-bit instructions. Since there are no real
14  * constraints on their use (and they can be mixed and matched), we need
15  * to check the instruction encoding to work out if it's a true 32-bit
16  * instruction or not.
17  *
18  * Presently, 32-bit opcodes have only slight variations in what the
19  * actual encoding looks like in the first-half of the instruction, which
20  * makes it fairly straightforward to differentiate from the 16-bit ones.
21  *
22  * First 16-bits of encoding		Used by
23  *
24  *	0011nnnnmmmm0001	mov.b, mov.w, mov.l, fmov.d,
25  *				fmov.s, movu.b, movu.w
26  *
27  *	0011nnnn0iii1001        bclr.b, bld.b, bset.b, bst.b, band.b,
28  *				bandnot.b, bldnot.b, bor.b, bornot.b,
29  *				bxor.b
30  *
31  *	0000nnnniiii0000        movi20
32  *	0000nnnniiii0001        movi20s
33  */
instruction_size(unsigned int insn)34 unsigned int instruction_size(unsigned int insn)
35 {
36 	/* Look for the common cases */
37 	switch ((insn & 0xf00f)) {
38 	case 0x0000:	/* movi20 */
39 	case 0x0001:	/* movi20s */
40 	case 0x3001:	/* 32-bit mov/fmov/movu variants */
41 		return 4;
42 	}
43 
44 	/* And the special cases.. */
45 	switch ((insn & 0xf08f)) {
46 	case 0x3009:	/* 32-bit b*.b bit operations */
47 		return 4;
48 	}
49 
50 	return 2;
51 }
52