1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_H 7 #define _ASM_ARCH_SDRAM_H 8 9 enum { 10 DDR4 = 0, 11 DDR3 = 0x3, 12 LPDDR2 = 0x5, 13 LPDDR3 = 0x6, 14 LPDDR4 = 0x7, 15 UNUSED = 0xFF 16 }; 17 18 /* 19 * sys_reg2 bitfield struct 20 * [31] row_3_4_ch1 21 * [30] row_3_4_ch0 22 * [29:28] chinfo 23 * [27] rank_ch1 24 * [26:25] col_ch1 25 * [24] bk_ch1 26 * [23:22] low bits of cs0_row_ch1 27 * [21:20] low bits of cs1_row_ch1 28 * [19:18] bw_ch1 29 * [17:16] dbw_ch1; 30 * [15:13] ddrtype 31 * [12] channelnum 32 * [11] rank_ch0 33 * [10:9] col_ch0, 34 * [8] bk_ch0 35 * [7:6] low bits of cs0_row_ch0 36 * [5:4] low bits of cs1_row_ch0 37 * [3:2] bw_ch0 38 * [1:0] dbw_ch0 39 */ 40 #define SYS_REG_DDRTYPE_SHIFT 13 41 #define SYS_REG_DDRTYPE_MASK 7 42 #define SYS_REG_NUM_CH_SHIFT 12 43 #define SYS_REG_NUM_CH_MASK 1 44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) 45 #define SYS_REG_ROW_3_4_MASK 1 46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) 47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) 48 #define SYS_REG_RANK_MASK 1 49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) 50 #define SYS_REG_COL_MASK 3 51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) 52 #define SYS_REG_BK_MASK 1 53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) 54 #define SYS_REG_CS0_ROW_MASK 3 55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) 56 #define SYS_REG_CS1_ROW_MASK 3 57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) 58 #define SYS_REG_BW_MASK 3 59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) 60 #define SYS_REG_DBW_MASK 3 61 62 /* 63 * sys_reg3 bitfield struct 64 * [7] high bit of cs0_row_ch1 65 * [6] high bit of cs1_row_ch1 66 * [5] high bit of cs0_row_ch0 67 * [4] high bit of cs1_row_ch0 68 * [3:2] cs1_col_ch1 69 * [1:0] cs1_col_ch0 70 */ 71 #define SYS_REG_VERSION_SHIFT 28 72 #define SYS_REG_VERSION_MASK 0xf 73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) 74 #define SYS_REG_EXTEND_CS0_ROW_MASK 1 75 #define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2) 76 #define SYS_REG_EXTEND_CS1_ROW_MASK 1 77 #define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2) 78 #define SYS_REG_CS1_COL_MASK 3 79 80 /* Get sdram size decode from reg */ 81 size_t rockchip_sdram_size(phys_addr_t reg); 82 83 /* Called by U-Boot board_init_r for Rockchip SoCs */ 84 int dram_init(void); 85 86 #endif 87