1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2500"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&vic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 serial0 = &uart1; 28 serial1 = &uart2; 29 serial2 = &uart3; 30 serial3 = &uart4; 31 serial4 = &uart5; 32 serial5 = &vuart; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,arm1176jzf-s"; 41 device_type = "cpu"; 42 reg = <0>; 43 }; 44 }; 45 46 memory@80000000 { 47 device_type = "memory"; 48 reg = <0x80000000 0>; 49 }; 50 51 ahb { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges; 56 57 fmc: spi@1e620000 { 58 reg = < 0x1e620000 0xc4 59 0x20000000 0x10000000 >; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 compatible = "aspeed,ast2500-fmc"; 63 clocks = <&syscon ASPEED_CLK_AHB>; 64 status = "disabled"; 65 interrupts = <19>; 66 flash@0 { 67 reg = < 0 >; 68 compatible = "jedec,spi-nor"; 69 spi-max-frequency = <50000000>; 70 status = "disabled"; 71 }; 72 flash@1 { 73 reg = < 1 >; 74 compatible = "jedec,spi-nor"; 75 spi-max-frequency = <50000000>; 76 status = "disabled"; 77 }; 78 flash@2 { 79 reg = < 2 >; 80 compatible = "jedec,spi-nor"; 81 spi-max-frequency = <50000000>; 82 status = "disabled"; 83 }; 84 }; 85 86 spi1: spi@1e630000 { 87 reg = < 0x1e630000 0xc4 88 0x30000000 0x08000000 >; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 compatible = "aspeed,ast2500-spi"; 92 clocks = <&syscon ASPEED_CLK_AHB>; 93 status = "disabled"; 94 flash@0 { 95 reg = < 0 >; 96 compatible = "jedec,spi-nor"; 97 spi-max-frequency = <50000000>; 98 status = "disabled"; 99 }; 100 flash@1 { 101 reg = < 1 >; 102 compatible = "jedec,spi-nor"; 103 spi-max-frequency = <50000000>; 104 status = "disabled"; 105 }; 106 }; 107 108 spi2: spi@1e631000 { 109 reg = < 0x1e631000 0xc4 110 0x38000000 0x08000000 >; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 compatible = "aspeed,ast2500-spi"; 114 clocks = <&syscon ASPEED_CLK_AHB>; 115 status = "disabled"; 116 flash@0 { 117 reg = < 0 >; 118 compatible = "jedec,spi-nor"; 119 spi-max-frequency = <50000000>; 120 status = "disabled"; 121 }; 122 flash@1 { 123 reg = < 1 >; 124 compatible = "jedec,spi-nor"; 125 spi-max-frequency = <50000000>; 126 status = "disabled"; 127 }; 128 }; 129 130 vic: interrupt-controller@1e6c0080 { 131 compatible = "aspeed,ast2400-vic"; 132 interrupt-controller; 133 #interrupt-cells = <1>; 134 valid-sources = <0xfefff7ff 0x0807ffff>; 135 reg = <0x1e6c0080 0x80>; 136 }; 137 138 cvic: copro-interrupt-controller@1e6c2000 { 139 compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; 140 valid-sources = <0xffffffff>; 141 copro-sw-interrupts = <1>; 142 reg = <0x1e6c2000 0x80>; 143 }; 144 145 mac0: ethernet@1e660000 { 146 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 147 reg = <0x1e660000 0x180>; 148 interrupts = <2>; 149 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 150 status = "disabled"; 151 }; 152 153 mac1: ethernet@1e680000 { 154 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 155 reg = <0x1e680000 0x180>; 156 interrupts = <3>; 157 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 158 status = "disabled"; 159 }; 160 161 ehci0: usb@1e6a1000 { 162 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 163 reg = <0x1e6a1000 0x100>; 164 interrupts = <5>; 165 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_usb2ah_default>; 168 status = "disabled"; 169 }; 170 171 ehci1: usb@1e6a3000 { 172 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 173 reg = <0x1e6a3000 0x100>; 174 interrupts = <13>; 175 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_usb2bh_default>; 178 status = "disabled"; 179 }; 180 181 uhci: usb@1e6b0000 { 182 compatible = "aspeed,ast2500-uhci", "generic-uhci"; 183 reg = <0x1e6b0000 0x100>; 184 interrupts = <14>; 185 #ports = <2>; 186 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 187 status = "disabled"; 188 /* 189 * No default pinmux, it will follow EHCI, use an explicit pinmux 190 * override if you don't enable EHCI 191 */ 192 }; 193 194 vhub: usb-vhub@1e6a0000 { 195 compatible = "aspeed,ast2500-usb-vhub"; 196 reg = <0x1e6a0000 0x300>; 197 interrupts = <5>; 198 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 199 aspeed,vhub-downstream-ports = <5>; 200 aspeed,vhub-generic-endpoints = <15>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_usb2ad_default>; 203 status = "disabled"; 204 }; 205 206 apb { 207 compatible = "simple-bus"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 edac: memory-controller@1e6e0000 { 213 compatible = "aspeed,ast2500-sdram-edac"; 214 reg = <0x1e6e0000 0x174>; 215 interrupts = <0>; 216 status = "disabled"; 217 }; 218 219 syscon: syscon@1e6e2000 { 220 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; 221 reg = <0x1e6e2000 0x1a8>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0x1e6e2000 0x1000>; 225 #clock-cells = <1>; 226 #reset-cells = <1>; 227 228 scu_ic: interrupt-controller@18 { 229 #interrupt-cells = <1>; 230 compatible = "aspeed,ast2500-scu-ic"; 231 reg = <0x18 0x4>; 232 interrupts = <21>; 233 interrupt-controller; 234 }; 235 236 p2a: p2a-control@2c { 237 compatible = "aspeed,ast2500-p2a-ctrl"; 238 reg = <0x2c 0x4>; 239 status = "disabled"; 240 }; 241 242 silicon-id@7c { 243 compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; 244 reg = <0x7c 0x4 0x150 0x8>; 245 }; 246 247 pinctrl: pinctrl@80 { 248 compatible = "aspeed,ast2500-pinctrl"; 249 reg = <0x80 0x18>, <0xa0 0x10>; 250 aspeed,external-nodes = <&gfx>, <&lhc>; 251 }; 252 }; 253 254 rng: hwrng@1e6e2078 { 255 compatible = "timeriomem_rng"; 256 reg = <0x1e6e2078 0x4>; 257 period = <1>; 258 quality = <100>; 259 }; 260 261 gfx: display@1e6e6000 { 262 compatible = "aspeed,ast2500-gfx", "syscon"; 263 reg = <0x1e6e6000 0x1000>; 264 reg-io-width = <4>; 265 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; 266 resets = <&syscon ASPEED_RESET_CRT1>; 267 syscon = <&syscon>; 268 status = "disabled"; 269 interrupts = <0x19>; 270 }; 271 272 xdma: xdma@1e6e7000 { 273 compatible = "aspeed,ast2500-xdma"; 274 reg = <0x1e6e7000 0x100>; 275 clocks = <&syscon ASPEED_CLK_GATE_BCLK>; 276 resets = <&syscon ASPEED_RESET_XDMA>; 277 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; 278 aspeed,pcie-device = "bmc"; 279 aspeed,scu = <&syscon>; 280 status = "disabled"; 281 }; 282 283 adc: adc@1e6e9000 { 284 compatible = "aspeed,ast2500-adc"; 285 reg = <0x1e6e9000 0xb0>; 286 clocks = <&syscon ASPEED_CLK_APB>; 287 resets = <&syscon ASPEED_RESET_ADC>; 288 #io-channel-cells = <1>; 289 status = "disabled"; 290 }; 291 292 video: video@1e700000 { 293 compatible = "aspeed,ast2500-video-engine"; 294 reg = <0x1e700000 0x1000>; 295 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 296 <&syscon ASPEED_CLK_GATE_ECLK>; 297 clock-names = "vclk", "eclk"; 298 interrupts = <7>; 299 status = "disabled"; 300 }; 301 302 sram: sram@1e720000 { 303 compatible = "mmio-sram"; 304 reg = <0x1e720000 0x9000>; // 36K 305 }; 306 307 sdmmc: sd-controller@1e740000 { 308 compatible = "aspeed,ast2500-sd-controller"; 309 reg = <0x1e740000 0x100>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges = <0 0x1e740000 0x10000>; 313 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 314 status = "disabled"; 315 316 sdhci0: sdhci@100 { 317 compatible = "aspeed,ast2500-sdhci"; 318 reg = <0x100 0x100>; 319 interrupts = <26>; 320 sdhci,auto-cmd12; 321 clocks = <&syscon ASPEED_CLK_SDIO>; 322 status = "disabled"; 323 }; 324 325 sdhci1: sdhci@200 { 326 compatible = "aspeed,ast2500-sdhci"; 327 reg = <0x200 0x100>; 328 interrupts = <26>; 329 sdhci,auto-cmd12; 330 clocks = <&syscon ASPEED_CLK_SDIO>; 331 status = "disabled"; 332 }; 333 }; 334 335 gpio: gpio@1e780000 { 336 #gpio-cells = <2>; 337 gpio-controller; 338 compatible = "aspeed,ast2500-gpio"; 339 reg = <0x1e780000 0x200>; 340 interrupts = <20>; 341 gpio-ranges = <&pinctrl 0 0 232>; 342 clocks = <&syscon ASPEED_CLK_APB>; 343 interrupt-controller; 344 #interrupt-cells = <2>; 345 }; 346 347 sgpio: sgpio@1e780200 { 348 #gpio-cells = <2>; 349 compatible = "aspeed,ast2500-sgpio"; 350 gpio-controller; 351 interrupts = <40>; 352 reg = <0x1e780200 0x0100>; 353 clocks = <&syscon ASPEED_CLK_APB>; 354 interrupt-controller; 355 bus-frequency = <12000000>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_sgpm_default>; 358 status = "disabled"; 359 }; 360 361 rtc: rtc@1e781000 { 362 compatible = "aspeed,ast2500-rtc"; 363 reg = <0x1e781000 0x18>; 364 status = "disabled"; 365 }; 366 367 timer: timer@1e782000 { 368 /* This timer is a Faraday FTTMR010 derivative */ 369 compatible = "aspeed,ast2400-timer"; 370 reg = <0x1e782000 0x90>; 371 interrupts = <16 17 18 35 36 37 38 39>; 372 clocks = <&syscon ASPEED_CLK_APB>; 373 clock-names = "PCLK"; 374 }; 375 376 uart1: serial@1e783000 { 377 compatible = "ns16550a"; 378 reg = <0x1e783000 0x20>; 379 reg-shift = <2>; 380 interrupts = <9>; 381 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 382 resets = <&lpc_reset 4>; 383 no-loopback-test; 384 status = "disabled"; 385 }; 386 387 uart5: serial@1e784000 { 388 compatible = "ns16550a"; 389 reg = <0x1e784000 0x20>; 390 reg-shift = <2>; 391 interrupts = <10>; 392 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 393 no-loopback-test; 394 status = "disabled"; 395 }; 396 397 wdt1: watchdog@1e785000 { 398 compatible = "aspeed,ast2500-wdt"; 399 reg = <0x1e785000 0x20>; 400 clocks = <&syscon ASPEED_CLK_APB>; 401 }; 402 403 wdt2: watchdog@1e785020 { 404 compatible = "aspeed,ast2500-wdt"; 405 reg = <0x1e785020 0x20>; 406 clocks = <&syscon ASPEED_CLK_APB>; 407 }; 408 409 wdt3: watchdog@1e785040 { 410 compatible = "aspeed,ast2500-wdt"; 411 reg = <0x1e785040 0x20>; 412 clocks = <&syscon ASPEED_CLK_APB>; 413 status = "disabled"; 414 }; 415 416 pwm_tacho: pwm-tacho-controller@1e786000 { 417 compatible = "aspeed,ast2500-pwm-tacho"; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 reg = <0x1e786000 0x1000>; 421 clocks = <&syscon ASPEED_CLK_24M>; 422 resets = <&syscon ASPEED_RESET_PWM>; 423 status = "disabled"; 424 }; 425 426 vuart: serial@1e787000 { 427 compatible = "aspeed,ast2500-vuart"; 428 reg = <0x1e787000 0x40>; 429 reg-shift = <2>; 430 interrupts = <8>; 431 clocks = <&syscon ASPEED_CLK_APB>; 432 no-loopback-test; 433 status = "disabled"; 434 }; 435 436 lpc: lpc@1e789000 { 437 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; 438 reg = <0x1e789000 0x1000>; 439 reg-io-width = <4>; 440 441 #address-cells = <1>; 442 #size-cells = <1>; 443 ranges = <0x0 0x1e789000 0x1000>; 444 445 kcs1: kcs@24 { 446 compatible = "aspeed,ast2500-kcs-bmc-v2"; 447 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; 448 interrupts = <8>; 449 status = "disabled"; 450 }; 451 452 kcs2: kcs@28 { 453 compatible = "aspeed,ast2500-kcs-bmc-v2"; 454 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; 455 interrupts = <8>; 456 status = "disabled"; 457 }; 458 459 kcs3: kcs@2c { 460 compatible = "aspeed,ast2500-kcs-bmc-v2"; 461 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; 462 interrupts = <8>; 463 status = "disabled"; 464 }; 465 466 kcs4: kcs@114 { 467 compatible = "aspeed,ast2500-kcs-bmc-v2"; 468 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; 469 interrupts = <8>; 470 status = "disabled"; 471 }; 472 473 lpc_ctrl: lpc-ctrl@80 { 474 compatible = "aspeed,ast2500-lpc-ctrl"; 475 reg = <0x80 0x10>; 476 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 477 status = "disabled"; 478 }; 479 480 lpc_snoop: lpc-snoop@90 { 481 compatible = "aspeed,ast2500-lpc-snoop"; 482 reg = <0x90 0x8>; 483 interrupts = <8>; 484 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 485 status = "disabled"; 486 }; 487 488 lpc_reset: reset-controller@98 { 489 compatible = "aspeed,ast2500-lpc-reset"; 490 reg = <0x98 0x4>; 491 #reset-cells = <1>; 492 }; 493 494 uart_routing: uart-routing@9c { 495 compatible = "aspeed,ast2500-uart-routing"; 496 reg = <0x9c 0x4>; 497 status = "disabled"; 498 }; 499 500 lhc: lhc@a0 { 501 compatible = "aspeed,ast2500-lhc"; 502 reg = <0xa0 0x24 0xc8 0x8>; 503 }; 504 505 506 ibt: ibt@140 { 507 compatible = "aspeed,ast2500-ibt-bmc"; 508 reg = <0x140 0x18>; 509 interrupts = <8>; 510 status = "disabled"; 511 }; 512 }; 513 514 uart2: serial@1e78d000 { 515 compatible = "ns16550a"; 516 reg = <0x1e78d000 0x20>; 517 reg-shift = <2>; 518 interrupts = <32>; 519 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 520 resets = <&lpc_reset 5>; 521 no-loopback-test; 522 status = "disabled"; 523 }; 524 525 uart3: serial@1e78e000 { 526 compatible = "ns16550a"; 527 reg = <0x1e78e000 0x20>; 528 reg-shift = <2>; 529 interrupts = <33>; 530 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 531 resets = <&lpc_reset 6>; 532 no-loopback-test; 533 status = "disabled"; 534 }; 535 536 uart4: serial@1e78f000 { 537 compatible = "ns16550a"; 538 reg = <0x1e78f000 0x20>; 539 reg-shift = <2>; 540 interrupts = <34>; 541 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 542 resets = <&lpc_reset 7>; 543 no-loopback-test; 544 status = "disabled"; 545 }; 546 547 i2c: bus@1e78a000 { 548 compatible = "simple-bus"; 549 #address-cells = <1>; 550 #size-cells = <1>; 551 ranges = <0 0x1e78a000 0x1000>; 552 }; 553 }; 554 }; 555}; 556 557&i2c { 558 i2c_ic: interrupt-controller@0 { 559 #interrupt-cells = <1>; 560 compatible = "aspeed,ast2500-i2c-ic"; 561 reg = <0x0 0x40>; 562 interrupts = <12>; 563 interrupt-controller; 564 }; 565 566 i2c0: i2c-bus@40 { 567 #address-cells = <1>; 568 #size-cells = <0>; 569 #interrupt-cells = <1>; 570 571 reg = <0x40 0x40>; 572 compatible = "aspeed,ast2500-i2c-bus"; 573 clocks = <&syscon ASPEED_CLK_APB>; 574 resets = <&syscon ASPEED_RESET_I2C>; 575 bus-frequency = <100000>; 576 interrupts = <0>; 577 interrupt-parent = <&i2c_ic>; 578 status = "disabled"; 579 /* Does not need pinctrl properties */ 580 }; 581 582 i2c1: i2c-bus@80 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 #interrupt-cells = <1>; 586 587 reg = <0x80 0x40>; 588 compatible = "aspeed,ast2500-i2c-bus"; 589 clocks = <&syscon ASPEED_CLK_APB>; 590 resets = <&syscon ASPEED_RESET_I2C>; 591 bus-frequency = <100000>; 592 interrupts = <1>; 593 interrupt-parent = <&i2c_ic>; 594 status = "disabled"; 595 /* Does not need pinctrl properties */ 596 }; 597 598 i2c2: i2c-bus@c0 { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 #interrupt-cells = <1>; 602 603 reg = <0xc0 0x40>; 604 compatible = "aspeed,ast2500-i2c-bus"; 605 clocks = <&syscon ASPEED_CLK_APB>; 606 resets = <&syscon ASPEED_RESET_I2C>; 607 bus-frequency = <100000>; 608 interrupts = <2>; 609 interrupt-parent = <&i2c_ic>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pinctrl_i2c3_default>; 612 status = "disabled"; 613 }; 614 615 i2c3: i2c-bus@100 { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #interrupt-cells = <1>; 619 620 reg = <0x100 0x40>; 621 compatible = "aspeed,ast2500-i2c-bus"; 622 clocks = <&syscon ASPEED_CLK_APB>; 623 resets = <&syscon ASPEED_RESET_I2C>; 624 bus-frequency = <100000>; 625 interrupts = <3>; 626 interrupt-parent = <&i2c_ic>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&pinctrl_i2c4_default>; 629 status = "disabled"; 630 }; 631 632 i2c4: i2c-bus@140 { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 #interrupt-cells = <1>; 636 637 reg = <0x140 0x40>; 638 compatible = "aspeed,ast2500-i2c-bus"; 639 clocks = <&syscon ASPEED_CLK_APB>; 640 resets = <&syscon ASPEED_RESET_I2C>; 641 bus-frequency = <100000>; 642 interrupts = <4>; 643 interrupt-parent = <&i2c_ic>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pinctrl_i2c5_default>; 646 status = "disabled"; 647 }; 648 649 i2c5: i2c-bus@180 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 #interrupt-cells = <1>; 653 654 reg = <0x180 0x40>; 655 compatible = "aspeed,ast2500-i2c-bus"; 656 clocks = <&syscon ASPEED_CLK_APB>; 657 resets = <&syscon ASPEED_RESET_I2C>; 658 bus-frequency = <100000>; 659 interrupts = <5>; 660 interrupt-parent = <&i2c_ic>; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&pinctrl_i2c6_default>; 663 status = "disabled"; 664 }; 665 666 i2c6: i2c-bus@1c0 { 667 #address-cells = <1>; 668 #size-cells = <0>; 669 #interrupt-cells = <1>; 670 671 reg = <0x1c0 0x40>; 672 compatible = "aspeed,ast2500-i2c-bus"; 673 clocks = <&syscon ASPEED_CLK_APB>; 674 resets = <&syscon ASPEED_RESET_I2C>; 675 bus-frequency = <100000>; 676 interrupts = <6>; 677 interrupt-parent = <&i2c_ic>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pinctrl_i2c7_default>; 680 status = "disabled"; 681 }; 682 683 i2c7: i2c-bus@300 { 684 #address-cells = <1>; 685 #size-cells = <0>; 686 #interrupt-cells = <1>; 687 688 reg = <0x300 0x40>; 689 compatible = "aspeed,ast2500-i2c-bus"; 690 clocks = <&syscon ASPEED_CLK_APB>; 691 resets = <&syscon ASPEED_RESET_I2C>; 692 bus-frequency = <100000>; 693 interrupts = <7>; 694 interrupt-parent = <&i2c_ic>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&pinctrl_i2c8_default>; 697 status = "disabled"; 698 }; 699 700 i2c8: i2c-bus@340 { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 #interrupt-cells = <1>; 704 705 reg = <0x340 0x40>; 706 compatible = "aspeed,ast2500-i2c-bus"; 707 clocks = <&syscon ASPEED_CLK_APB>; 708 resets = <&syscon ASPEED_RESET_I2C>; 709 bus-frequency = <100000>; 710 interrupts = <8>; 711 interrupt-parent = <&i2c_ic>; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&pinctrl_i2c9_default>; 714 status = "disabled"; 715 }; 716 717 i2c9: i2c-bus@380 { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 #interrupt-cells = <1>; 721 722 reg = <0x380 0x40>; 723 compatible = "aspeed,ast2500-i2c-bus"; 724 clocks = <&syscon ASPEED_CLK_APB>; 725 resets = <&syscon ASPEED_RESET_I2C>; 726 bus-frequency = <100000>; 727 interrupts = <9>; 728 interrupt-parent = <&i2c_ic>; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&pinctrl_i2c10_default>; 731 status = "disabled"; 732 }; 733 734 i2c10: i2c-bus@3c0 { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 #interrupt-cells = <1>; 738 739 reg = <0x3c0 0x40>; 740 compatible = "aspeed,ast2500-i2c-bus"; 741 clocks = <&syscon ASPEED_CLK_APB>; 742 resets = <&syscon ASPEED_RESET_I2C>; 743 bus-frequency = <100000>; 744 interrupts = <10>; 745 interrupt-parent = <&i2c_ic>; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&pinctrl_i2c11_default>; 748 status = "disabled"; 749 }; 750 751 i2c11: i2c-bus@400 { 752 #address-cells = <1>; 753 #size-cells = <0>; 754 #interrupt-cells = <1>; 755 756 reg = <0x400 0x40>; 757 compatible = "aspeed,ast2500-i2c-bus"; 758 clocks = <&syscon ASPEED_CLK_APB>; 759 resets = <&syscon ASPEED_RESET_I2C>; 760 bus-frequency = <100000>; 761 interrupts = <11>; 762 interrupt-parent = <&i2c_ic>; 763 pinctrl-names = "default"; 764 pinctrl-0 = <&pinctrl_i2c12_default>; 765 status = "disabled"; 766 }; 767 768 i2c12: i2c-bus@440 { 769 #address-cells = <1>; 770 #size-cells = <0>; 771 #interrupt-cells = <1>; 772 773 reg = <0x440 0x40>; 774 compatible = "aspeed,ast2500-i2c-bus"; 775 clocks = <&syscon ASPEED_CLK_APB>; 776 resets = <&syscon ASPEED_RESET_I2C>; 777 bus-frequency = <100000>; 778 interrupts = <12>; 779 interrupt-parent = <&i2c_ic>; 780 pinctrl-names = "default"; 781 pinctrl-0 = <&pinctrl_i2c13_default>; 782 status = "disabled"; 783 }; 784 785 i2c13: i2c-bus@480 { 786 #address-cells = <1>; 787 #size-cells = <0>; 788 #interrupt-cells = <1>; 789 790 reg = <0x480 0x40>; 791 compatible = "aspeed,ast2500-i2c-bus"; 792 clocks = <&syscon ASPEED_CLK_APB>; 793 resets = <&syscon ASPEED_RESET_I2C>; 794 bus-frequency = <100000>; 795 interrupts = <13>; 796 interrupt-parent = <&i2c_ic>; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&pinctrl_i2c14_default>; 799 status = "disabled"; 800 }; 801}; 802 803&pinctrl { 804 pinctrl_acpi_default: acpi_default { 805 function = "ACPI"; 806 groups = "ACPI"; 807 }; 808 809 pinctrl_adc0_default: adc0_default { 810 function = "ADC0"; 811 groups = "ADC0"; 812 }; 813 814 pinctrl_adc1_default: adc1_default { 815 function = "ADC1"; 816 groups = "ADC1"; 817 }; 818 819 pinctrl_adc10_default: adc10_default { 820 function = "ADC10"; 821 groups = "ADC10"; 822 }; 823 824 pinctrl_adc11_default: adc11_default { 825 function = "ADC11"; 826 groups = "ADC11"; 827 }; 828 829 pinctrl_adc12_default: adc12_default { 830 function = "ADC12"; 831 groups = "ADC12"; 832 }; 833 834 pinctrl_adc13_default: adc13_default { 835 function = "ADC13"; 836 groups = "ADC13"; 837 }; 838 839 pinctrl_adc14_default: adc14_default { 840 function = "ADC14"; 841 groups = "ADC14"; 842 }; 843 844 pinctrl_adc15_default: adc15_default { 845 function = "ADC15"; 846 groups = "ADC15"; 847 }; 848 849 pinctrl_adc2_default: adc2_default { 850 function = "ADC2"; 851 groups = "ADC2"; 852 }; 853 854 pinctrl_adc3_default: adc3_default { 855 function = "ADC3"; 856 groups = "ADC3"; 857 }; 858 859 pinctrl_adc4_default: adc4_default { 860 function = "ADC4"; 861 groups = "ADC4"; 862 }; 863 864 pinctrl_adc5_default: adc5_default { 865 function = "ADC5"; 866 groups = "ADC5"; 867 }; 868 869 pinctrl_adc6_default: adc6_default { 870 function = "ADC6"; 871 groups = "ADC6"; 872 }; 873 874 pinctrl_adc7_default: adc7_default { 875 function = "ADC7"; 876 groups = "ADC7"; 877 }; 878 879 pinctrl_adc8_default: adc8_default { 880 function = "ADC8"; 881 groups = "ADC8"; 882 }; 883 884 pinctrl_adc9_default: adc9_default { 885 function = "ADC9"; 886 groups = "ADC9"; 887 }; 888 889 pinctrl_bmcint_default: bmcint_default { 890 function = "BMCINT"; 891 groups = "BMCINT"; 892 }; 893 894 pinctrl_ddcclk_default: ddcclk_default { 895 function = "DDCCLK"; 896 groups = "DDCCLK"; 897 }; 898 899 pinctrl_ddcdat_default: ddcdat_default { 900 function = "DDCDAT"; 901 groups = "DDCDAT"; 902 }; 903 904 pinctrl_espi_default: espi_default { 905 function = "ESPI"; 906 groups = "ESPI"; 907 }; 908 909 pinctrl_fwspics1_default: fwspics1_default { 910 function = "FWSPICS1"; 911 groups = "FWSPICS1"; 912 }; 913 914 pinctrl_fwspics2_default: fwspics2_default { 915 function = "FWSPICS2"; 916 groups = "FWSPICS2"; 917 }; 918 919 pinctrl_gpid0_default: gpid0_default { 920 function = "GPID0"; 921 groups = "GPID0"; 922 }; 923 924 pinctrl_gpid2_default: gpid2_default { 925 function = "GPID2"; 926 groups = "GPID2"; 927 }; 928 929 pinctrl_gpid4_default: gpid4_default { 930 function = "GPID4"; 931 groups = "GPID4"; 932 }; 933 934 pinctrl_gpid6_default: gpid6_default { 935 function = "GPID6"; 936 groups = "GPID6"; 937 }; 938 939 pinctrl_gpie0_default: gpie0_default { 940 function = "GPIE0"; 941 groups = "GPIE0"; 942 }; 943 944 pinctrl_gpie2_default: gpie2_default { 945 function = "GPIE2"; 946 groups = "GPIE2"; 947 }; 948 949 pinctrl_gpie4_default: gpie4_default { 950 function = "GPIE4"; 951 groups = "GPIE4"; 952 }; 953 954 pinctrl_gpie6_default: gpie6_default { 955 function = "GPIE6"; 956 groups = "GPIE6"; 957 }; 958 959 pinctrl_i2c10_default: i2c10_default { 960 function = "I2C10"; 961 groups = "I2C10"; 962 }; 963 964 pinctrl_i2c11_default: i2c11_default { 965 function = "I2C11"; 966 groups = "I2C11"; 967 }; 968 969 pinctrl_i2c12_default: i2c12_default { 970 function = "I2C12"; 971 groups = "I2C12"; 972 }; 973 974 pinctrl_i2c13_default: i2c13_default { 975 function = "I2C13"; 976 groups = "I2C13"; 977 }; 978 979 pinctrl_i2c14_default: i2c14_default { 980 function = "I2C14"; 981 groups = "I2C14"; 982 }; 983 984 pinctrl_i2c3_default: i2c3_default { 985 function = "I2C3"; 986 groups = "I2C3"; 987 }; 988 989 pinctrl_i2c4_default: i2c4_default { 990 function = "I2C4"; 991 groups = "I2C4"; 992 }; 993 994 pinctrl_i2c5_default: i2c5_default { 995 function = "I2C5"; 996 groups = "I2C5"; 997 }; 998 999 pinctrl_i2c6_default: i2c6_default { 1000 function = "I2C6"; 1001 groups = "I2C6"; 1002 }; 1003 1004 pinctrl_i2c7_default: i2c7_default { 1005 function = "I2C7"; 1006 groups = "I2C7"; 1007 }; 1008 1009 pinctrl_i2c8_default: i2c8_default { 1010 function = "I2C8"; 1011 groups = "I2C8"; 1012 }; 1013 1014 pinctrl_i2c9_default: i2c9_default { 1015 function = "I2C9"; 1016 groups = "I2C9"; 1017 }; 1018 1019 pinctrl_lad0_default: lad0_default { 1020 function = "LAD0"; 1021 groups = "LAD0"; 1022 }; 1023 1024 pinctrl_lad1_default: lad1_default { 1025 function = "LAD1"; 1026 groups = "LAD1"; 1027 }; 1028 1029 pinctrl_lad2_default: lad2_default { 1030 function = "LAD2"; 1031 groups = "LAD2"; 1032 }; 1033 1034 pinctrl_lad3_default: lad3_default { 1035 function = "LAD3"; 1036 groups = "LAD3"; 1037 }; 1038 1039 pinctrl_lclk_default: lclk_default { 1040 function = "LCLK"; 1041 groups = "LCLK"; 1042 }; 1043 1044 pinctrl_lframe_default: lframe_default { 1045 function = "LFRAME"; 1046 groups = "LFRAME"; 1047 }; 1048 1049 pinctrl_lpchc_default: lpchc_default { 1050 function = "LPCHC"; 1051 groups = "LPCHC"; 1052 }; 1053 1054 pinctrl_lpcpd_default: lpcpd_default { 1055 function = "LPCPD"; 1056 groups = "LPCPD"; 1057 }; 1058 1059 pinctrl_lpcplus_default: lpcplus_default { 1060 function = "LPCPLUS"; 1061 groups = "LPCPLUS"; 1062 }; 1063 1064 pinctrl_lpcpme_default: lpcpme_default { 1065 function = "LPCPME"; 1066 groups = "LPCPME"; 1067 }; 1068 1069 pinctrl_lpcrst_default: lpcrst_default { 1070 function = "LPCRST"; 1071 groups = "LPCRST"; 1072 }; 1073 1074 pinctrl_lpcsmi_default: lpcsmi_default { 1075 function = "LPCSMI"; 1076 groups = "LPCSMI"; 1077 }; 1078 1079 pinctrl_lsirq_default: lsirq_default { 1080 function = "LSIRQ"; 1081 groups = "LSIRQ"; 1082 }; 1083 1084 pinctrl_mac1link_default: mac1link_default { 1085 function = "MAC1LINK"; 1086 groups = "MAC1LINK"; 1087 }; 1088 1089 pinctrl_mac2link_default: mac2link_default { 1090 function = "MAC2LINK"; 1091 groups = "MAC2LINK"; 1092 }; 1093 1094 pinctrl_mdio1_default: mdio1_default { 1095 function = "MDIO1"; 1096 groups = "MDIO1"; 1097 }; 1098 1099 pinctrl_mdio2_default: mdio2_default { 1100 function = "MDIO2"; 1101 groups = "MDIO2"; 1102 }; 1103 1104 pinctrl_ncts1_default: ncts1_default { 1105 function = "NCTS1"; 1106 groups = "NCTS1"; 1107 }; 1108 1109 pinctrl_ncts2_default: ncts2_default { 1110 function = "NCTS2"; 1111 groups = "NCTS2"; 1112 }; 1113 1114 pinctrl_ncts3_default: ncts3_default { 1115 function = "NCTS3"; 1116 groups = "NCTS3"; 1117 }; 1118 1119 pinctrl_ncts4_default: ncts4_default { 1120 function = "NCTS4"; 1121 groups = "NCTS4"; 1122 }; 1123 1124 pinctrl_ndcd1_default: ndcd1_default { 1125 function = "NDCD1"; 1126 groups = "NDCD1"; 1127 }; 1128 1129 pinctrl_ndcd2_default: ndcd2_default { 1130 function = "NDCD2"; 1131 groups = "NDCD2"; 1132 }; 1133 1134 pinctrl_ndcd3_default: ndcd3_default { 1135 function = "NDCD3"; 1136 groups = "NDCD3"; 1137 }; 1138 1139 pinctrl_ndcd4_default: ndcd4_default { 1140 function = "NDCD4"; 1141 groups = "NDCD4"; 1142 }; 1143 1144 pinctrl_ndsr1_default: ndsr1_default { 1145 function = "NDSR1"; 1146 groups = "NDSR1"; 1147 }; 1148 1149 pinctrl_ndsr2_default: ndsr2_default { 1150 function = "NDSR2"; 1151 groups = "NDSR2"; 1152 }; 1153 1154 pinctrl_ndsr3_default: ndsr3_default { 1155 function = "NDSR3"; 1156 groups = "NDSR3"; 1157 }; 1158 1159 pinctrl_ndsr4_default: ndsr4_default { 1160 function = "NDSR4"; 1161 groups = "NDSR4"; 1162 }; 1163 1164 pinctrl_ndtr1_default: ndtr1_default { 1165 function = "NDTR1"; 1166 groups = "NDTR1"; 1167 }; 1168 1169 pinctrl_ndtr2_default: ndtr2_default { 1170 function = "NDTR2"; 1171 groups = "NDTR2"; 1172 }; 1173 1174 pinctrl_ndtr3_default: ndtr3_default { 1175 function = "NDTR3"; 1176 groups = "NDTR3"; 1177 }; 1178 1179 pinctrl_ndtr4_default: ndtr4_default { 1180 function = "NDTR4"; 1181 groups = "NDTR4"; 1182 }; 1183 1184 pinctrl_nri1_default: nri1_default { 1185 function = "NRI1"; 1186 groups = "NRI1"; 1187 }; 1188 1189 pinctrl_nri2_default: nri2_default { 1190 function = "NRI2"; 1191 groups = "NRI2"; 1192 }; 1193 1194 pinctrl_nri3_default: nri3_default { 1195 function = "NRI3"; 1196 groups = "NRI3"; 1197 }; 1198 1199 pinctrl_nri4_default: nri4_default { 1200 function = "NRI4"; 1201 groups = "NRI4"; 1202 }; 1203 1204 pinctrl_nrts1_default: nrts1_default { 1205 function = "NRTS1"; 1206 groups = "NRTS1"; 1207 }; 1208 1209 pinctrl_nrts2_default: nrts2_default { 1210 function = "NRTS2"; 1211 groups = "NRTS2"; 1212 }; 1213 1214 pinctrl_nrts3_default: nrts3_default { 1215 function = "NRTS3"; 1216 groups = "NRTS3"; 1217 }; 1218 1219 pinctrl_nrts4_default: nrts4_default { 1220 function = "NRTS4"; 1221 groups = "NRTS4"; 1222 }; 1223 1224 pinctrl_oscclk_default: oscclk_default { 1225 function = "OSCCLK"; 1226 groups = "OSCCLK"; 1227 }; 1228 1229 pinctrl_pewake_default: pewake_default { 1230 function = "PEWAKE"; 1231 groups = "PEWAKE"; 1232 }; 1233 1234 pinctrl_pnor_default: pnor_default { 1235 function = "PNOR"; 1236 groups = "PNOR"; 1237 }; 1238 1239 pinctrl_pwm0_default: pwm0_default { 1240 function = "PWM0"; 1241 groups = "PWM0"; 1242 }; 1243 1244 pinctrl_pwm1_default: pwm1_default { 1245 function = "PWM1"; 1246 groups = "PWM1"; 1247 }; 1248 1249 pinctrl_pwm2_default: pwm2_default { 1250 function = "PWM2"; 1251 groups = "PWM2"; 1252 }; 1253 1254 pinctrl_pwm3_default: pwm3_default { 1255 function = "PWM3"; 1256 groups = "PWM3"; 1257 }; 1258 1259 pinctrl_pwm4_default: pwm4_default { 1260 function = "PWM4"; 1261 groups = "PWM4"; 1262 }; 1263 1264 pinctrl_pwm5_default: pwm5_default { 1265 function = "PWM5"; 1266 groups = "PWM5"; 1267 }; 1268 1269 pinctrl_pwm6_default: pwm6_default { 1270 function = "PWM6"; 1271 groups = "PWM6"; 1272 }; 1273 1274 pinctrl_pwm7_default: pwm7_default { 1275 function = "PWM7"; 1276 groups = "PWM7"; 1277 }; 1278 1279 pinctrl_rgmii1_default: rgmii1_default { 1280 function = "RGMII1"; 1281 groups = "RGMII1"; 1282 }; 1283 1284 pinctrl_rgmii2_default: rgmii2_default { 1285 function = "RGMII2"; 1286 groups = "RGMII2"; 1287 }; 1288 1289 pinctrl_rmii1_default: rmii1_default { 1290 function = "RMII1"; 1291 groups = "RMII1"; 1292 }; 1293 1294 pinctrl_rmii2_default: rmii2_default { 1295 function = "RMII2"; 1296 groups = "RMII2"; 1297 }; 1298 1299 pinctrl_rxd1_default: rxd1_default { 1300 function = "RXD1"; 1301 groups = "RXD1"; 1302 }; 1303 1304 pinctrl_rxd2_default: rxd2_default { 1305 function = "RXD2"; 1306 groups = "RXD2"; 1307 }; 1308 1309 pinctrl_rxd3_default: rxd3_default { 1310 function = "RXD3"; 1311 groups = "RXD3"; 1312 }; 1313 1314 pinctrl_rxd4_default: rxd4_default { 1315 function = "RXD4"; 1316 groups = "RXD4"; 1317 }; 1318 1319 pinctrl_salt1_default: salt1_default { 1320 function = "SALT1"; 1321 groups = "SALT1"; 1322 }; 1323 1324 pinctrl_salt10_default: salt10_default { 1325 function = "SALT10"; 1326 groups = "SALT10"; 1327 }; 1328 1329 pinctrl_salt11_default: salt11_default { 1330 function = "SALT11"; 1331 groups = "SALT11"; 1332 }; 1333 1334 pinctrl_salt12_default: salt12_default { 1335 function = "SALT12"; 1336 groups = "SALT12"; 1337 }; 1338 1339 pinctrl_salt13_default: salt13_default { 1340 function = "SALT13"; 1341 groups = "SALT13"; 1342 }; 1343 1344 pinctrl_salt14_default: salt14_default { 1345 function = "SALT14"; 1346 groups = "SALT14"; 1347 }; 1348 1349 pinctrl_salt2_default: salt2_default { 1350 function = "SALT2"; 1351 groups = "SALT2"; 1352 }; 1353 1354 pinctrl_salt3_default: salt3_default { 1355 function = "SALT3"; 1356 groups = "SALT3"; 1357 }; 1358 1359 pinctrl_salt4_default: salt4_default { 1360 function = "SALT4"; 1361 groups = "SALT4"; 1362 }; 1363 1364 pinctrl_salt5_default: salt5_default { 1365 function = "SALT5"; 1366 groups = "SALT5"; 1367 }; 1368 1369 pinctrl_salt6_default: salt6_default { 1370 function = "SALT6"; 1371 groups = "SALT6"; 1372 }; 1373 1374 pinctrl_salt7_default: salt7_default { 1375 function = "SALT7"; 1376 groups = "SALT7"; 1377 }; 1378 1379 pinctrl_salt8_default: salt8_default { 1380 function = "SALT8"; 1381 groups = "SALT8"; 1382 }; 1383 1384 pinctrl_salt9_default: salt9_default { 1385 function = "SALT9"; 1386 groups = "SALT9"; 1387 }; 1388 1389 pinctrl_scl1_default: scl1_default { 1390 function = "SCL1"; 1391 groups = "SCL1"; 1392 }; 1393 1394 pinctrl_scl2_default: scl2_default { 1395 function = "SCL2"; 1396 groups = "SCL2"; 1397 }; 1398 1399 pinctrl_sd1_default: sd1_default { 1400 function = "SD1"; 1401 groups = "SD1"; 1402 }; 1403 1404 pinctrl_sd2_default: sd2_default { 1405 function = "SD2"; 1406 groups = "SD2"; 1407 }; 1408 1409 pinctrl_sda1_default: sda1_default { 1410 function = "SDA1"; 1411 groups = "SDA1"; 1412 }; 1413 1414 pinctrl_sda2_default: sda2_default { 1415 function = "SDA2"; 1416 groups = "SDA2"; 1417 }; 1418 1419 pinctrl_sgpm_default: sgpm_default { 1420 function = "SGPM"; 1421 groups = "SGPM"; 1422 }; 1423 1424 pinctrl_sgps1_default: sgps1_default { 1425 function = "SGPS1"; 1426 groups = "SGPS1"; 1427 }; 1428 1429 pinctrl_sgps2_default: sgps2_default { 1430 function = "SGPS2"; 1431 groups = "SGPS2"; 1432 }; 1433 1434 pinctrl_sioonctrl_default: sioonctrl_default { 1435 function = "SIOONCTRL"; 1436 groups = "SIOONCTRL"; 1437 }; 1438 1439 pinctrl_siopbi_default: siopbi_default { 1440 function = "SIOPBI"; 1441 groups = "SIOPBI"; 1442 }; 1443 1444 pinctrl_siopbo_default: siopbo_default { 1445 function = "SIOPBO"; 1446 groups = "SIOPBO"; 1447 }; 1448 1449 pinctrl_siopwreq_default: siopwreq_default { 1450 function = "SIOPWREQ"; 1451 groups = "SIOPWREQ"; 1452 }; 1453 1454 pinctrl_siopwrgd_default: siopwrgd_default { 1455 function = "SIOPWRGD"; 1456 groups = "SIOPWRGD"; 1457 }; 1458 1459 pinctrl_sios3_default: sios3_default { 1460 function = "SIOS3"; 1461 groups = "SIOS3"; 1462 }; 1463 1464 pinctrl_sios5_default: sios5_default { 1465 function = "SIOS5"; 1466 groups = "SIOS5"; 1467 }; 1468 1469 pinctrl_siosci_default: siosci_default { 1470 function = "SIOSCI"; 1471 groups = "SIOSCI"; 1472 }; 1473 1474 pinctrl_spi1_default: spi1_default { 1475 function = "SPI1"; 1476 groups = "SPI1"; 1477 }; 1478 1479 pinctrl_spi1cs1_default: spi1cs1_default { 1480 function = "SPI1CS1"; 1481 groups = "SPI1CS1"; 1482 }; 1483 1484 pinctrl_spi1debug_default: spi1debug_default { 1485 function = "SPI1DEBUG"; 1486 groups = "SPI1DEBUG"; 1487 }; 1488 1489 pinctrl_spi1passthru_default: spi1passthru_default { 1490 function = "SPI1PASSTHRU"; 1491 groups = "SPI1PASSTHRU"; 1492 }; 1493 1494 pinctrl_spi2ck_default: spi2ck_default { 1495 function = "SPI2CK"; 1496 groups = "SPI2CK"; 1497 }; 1498 1499 pinctrl_spi2cs0_default: spi2cs0_default { 1500 function = "SPI2CS0"; 1501 groups = "SPI2CS0"; 1502 }; 1503 1504 pinctrl_spi2cs1_default: spi2cs1_default { 1505 function = "SPI2CS1"; 1506 groups = "SPI2CS1"; 1507 }; 1508 1509 pinctrl_spi2miso_default: spi2miso_default { 1510 function = "SPI2MISO"; 1511 groups = "SPI2MISO"; 1512 }; 1513 1514 pinctrl_spi2mosi_default: spi2mosi_default { 1515 function = "SPI2MOSI"; 1516 groups = "SPI2MOSI"; 1517 }; 1518 1519 pinctrl_timer3_default: timer3_default { 1520 function = "TIMER3"; 1521 groups = "TIMER3"; 1522 }; 1523 1524 pinctrl_timer4_default: timer4_default { 1525 function = "TIMER4"; 1526 groups = "TIMER4"; 1527 }; 1528 1529 pinctrl_timer5_default: timer5_default { 1530 function = "TIMER5"; 1531 groups = "TIMER5"; 1532 }; 1533 1534 pinctrl_timer6_default: timer6_default { 1535 function = "TIMER6"; 1536 groups = "TIMER6"; 1537 }; 1538 1539 pinctrl_timer7_default: timer7_default { 1540 function = "TIMER7"; 1541 groups = "TIMER7"; 1542 }; 1543 1544 pinctrl_timer8_default: timer8_default { 1545 function = "TIMER8"; 1546 groups = "TIMER8"; 1547 }; 1548 1549 pinctrl_txd1_default: txd1_default { 1550 function = "TXD1"; 1551 groups = "TXD1"; 1552 }; 1553 1554 pinctrl_txd2_default: txd2_default { 1555 function = "TXD2"; 1556 groups = "TXD2"; 1557 }; 1558 1559 pinctrl_txd3_default: txd3_default { 1560 function = "TXD3"; 1561 groups = "TXD3"; 1562 }; 1563 1564 pinctrl_txd4_default: txd4_default { 1565 function = "TXD4"; 1566 groups = "TXD4"; 1567 }; 1568 1569 pinctrl_uart6_default: uart6_default { 1570 function = "UART6"; 1571 groups = "UART6"; 1572 }; 1573 1574 pinctrl_usbcki_default: usbcki_default { 1575 function = "USBCKI"; 1576 groups = "USBCKI"; 1577 }; 1578 1579 pinctrl_usb2ah_default: usb2ah_default { 1580 function = "USB2AH"; 1581 groups = "USB2AH"; 1582 }; 1583 1584 pinctrl_usb2ad_default: usb2ad_default { 1585 function = "USB2AD"; 1586 groups = "USB2AD"; 1587 }; 1588 1589 pinctrl_usb11bhid_default: usb11bhid_default { 1590 function = "USB11BHID"; 1591 groups = "USB11BHID"; 1592 }; 1593 1594 pinctrl_usb2bh_default: usb2bh_default { 1595 function = "USB2BH"; 1596 groups = "USB2BH"; 1597 }; 1598 1599 pinctrl_vgabiosrom_default: vgabiosrom_default { 1600 function = "VGABIOSROM"; 1601 groups = "VGABIOSROM"; 1602 }; 1603 1604 pinctrl_vgahs_default: vgahs_default { 1605 function = "VGAHS"; 1606 groups = "VGAHS"; 1607 }; 1608 1609 pinctrl_vgavs_default: vgavs_default { 1610 function = "VGAVS"; 1611 groups = "VGAVS"; 1612 }; 1613 1614 pinctrl_vpi24_default: vpi24_default { 1615 function = "VPI24"; 1616 groups = "VPI24"; 1617 }; 1618 1619 pinctrl_vpo_default: vpo_default { 1620 function = "VPO"; 1621 groups = "VPO"; 1622 }; 1623 1624 pinctrl_wdtrst1_default: wdtrst1_default { 1625 function = "WDTRST1"; 1626 groups = "WDTRST1"; 1627 }; 1628 1629 pinctrl_wdtrst2_default: wdtrst2_default { 1630 function = "WDTRST2"; 1631 groups = "WDTRST2"; 1632 }; 1633}; 1634