1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 *
6 * Refer docs/README.imxmage for more details about how-to configure
7 * and create imximage boot image
8 *
9 * The syntax is taken as close as possible with the kwbimage
10 */
11
12#define __ASSEMBLY__
13#include <config.h>
14
15/* image version */
16
17IMAGE_VERSION 2
18
19/*
20 * Boot Device : sd
21 */
22
23BOOT_FROM	sd
24
25/*
26 * Secure boot support
27 */
28#ifdef CONFIG_IMX_HAB
29CSF CONFIG_CSF_SIZE
30#endif
31
32/*
33 * Device Configuration Data (DCD)
34 *
35 * Each entry must have the format:
36 * Addr-type           Address        Value
37 *
38 * where:
39 *	Addr-type register length (1,2 or 4 bytes)
40 *	Address	  absolute address of the register
41 *	value	  value to be stored in the register
42 */
43
44/* Enable OCRAM EPDC */
45DATA 4 0x30340004 0x4F400005
46
47/* =============================================================================
48 * DDR Controller Registers
49 * =============================================================================
50 * Memory type:           DDR3
51 * Manufacturer:          ISSI
52 * Device Part Number:    IS43TR16256AL-125KBL
53 * Clock Freq.:           533MHz
54 * Density per CS in Gb:  4
55 * Chip Selects used:     1
56 * Number of Banks:       8
57 * Row address:          15
58 * Column address:       10
59 * Data bus width:       16
60 * ROW-BANK interleave:  ENABLED
61 * =============================================================================
62 */
63
64DATA 4 0x30391000 0x00000002    // deassert presetn
65DATA 4 0x307A0000 0x01041001    // DDRC_MSTR
66DATA 4 0x307A0064 0x00400046    // DDRC_RFSHTMG
67DATA 4 0x307a0490 0x00000001    // DDRC_PCTRL_0
68DATA 4 0x307A00D4 0x00690000    // DDRC_INIT1
69DATA 4 0x307A00D0 0x00020083    // DDRC_INIT0
70DATA 4 0x307A00DC 0x09300004    // DDRC_INIT3
71DATA 4 0x307A00E0 0x04080000    // DDRC_INIT4
72DATA 4 0x307A00E4 0x00100004    // DDRC_INIT5
73DATA 4 0x307A00F4 0x0000033F    // DDRC_RANKCTL
74DATA 4 0x307A0100 0x090B1109    // DDRC_DRAMTMG0
75DATA 4 0x307A0104 0x0007020D    // DDRC_DRAMTMG1
76DATA 4 0x307A0108 0x03040407    // DDRC_DRAMTMG2
77DATA 4 0x307A010C 0x00002006    // DDRC_DRAMTMG3
78DATA 4 0x307A0110 0x04020205    // DDRC_DRAMTMG4
79DATA 4 0x307A0114 0x03030202    // DDRC_DRAMTMG5
80DATA 4 0x307A0120 0x00000803    // DDRC_DRAMTMG8
81DATA 4 0x307A0180 0x00800020    // DDRC_ZQCTL0
82DATA 4 0x307A0190 0x02098204    // DDRC_DFITMG0
83DATA 4 0x307A0194 0x00030303    // DDRC_DFITMG1
84DATA 4 0x307A01A0 0x80400003    // DDRC_DFIUPD0
85DATA 4 0x307A01A4 0x00100020    // DDRC_DFIUPD1
86DATA 4 0x307A01A8 0x80100004    // DDRC_DFIUPD2
87DATA 4 0x307A0200 0x00000015    // DDRC_ADDRMAP0
88DATA 4 0x307A0204 0x00070707    // DDRC_ADDRMAP1
89DATA 4 0x307A0210 0x00000F0F    // DDRC_ADDRMAP4
90DATA 4 0x307A0214 0x06060606    // DDRC_ADDRMAP5
91DATA 4 0x307A0218 0x0F060606    // DDRC_ADDRMAP6
92DATA 4 0x307A0240 0x06000604    // DDRC_ODTCFG
93DATA 4 0x307A0244 0x00000001    // DDRC_ODTMAP
94
95
96/* =============================================================================
97 * PHY Control Register
98 * =============================================================================
99 */
100
101DATA 4 0x30391000 0x00000000    // deassert presetn
102DATA 4 0x30790000 0x17420F40    // DDR_PHY_PHY_CON0
103DATA 4 0x30790004 0x10210100    // DDR_PHY_PHY_CON1
104DATA 4 0x30790010 0x00060807    // DDR_PHY_PHY_CON4
105DATA 4 0x307900B0 0x1010007E    // DDR_PHY_MDLL_CON0
106DATA 4 0x3079009C 0x00000D6E    // DDR_PHY_DRVDS_CON0
107DATA 4 0x30790030 0x08080808    // DDR_PHY_OFFSET_WR_CON0
108DATA 4 0x30790020 0x08080808    // DDR_PHY_OFFSET_RD_CON0
109DATA 4 0x30790050 0x01000010    // DDR_PHY_OFFSETD_CON0
110DATA 4 0x30790050 0x00000010    // DDR_PHY_OFFSETD_CON0
111DATA 4 0x30790018 0x0000000F    // DDR_PHY_LP_CON0
112DATA 4 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - Start Manual ZQ
113DATA 4 0x307900C0 0x0E447304
114DATA 4 0x307900C0 0x0E447306
115DATA 4 0x307900C0 0x0E447304    // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
116DATA 4 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - End Manual ZQ
117
118
119/* =============================================================================
120 * Final Initialization start sequence
121 * =============================================================================
122 */
123
124DATA 4 0x30384130 0x00000000    // Disable Clock
125DATA 4 0x30340020 0x00000178    // IOMUX_GRP_GRP8 - Start input to PHY
126DATA 4 0x30384130 0x00000002    // Enable Clock
127/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */
128