1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright 2018-2020 NXP
4  *
5  * Brief   CAAM Controller Hardware Abstration Layer header.
6  */
7 #ifndef __CAAM_HAL_CTRL_H__
8 #define __CAAM_HAL_CTRL_H__
9 
10 #include <types_ext.h>
11 
12 /*
13  * Initializes the CAAM HW Controller
14  *
15  * @baseaddr  Controller base address
16  */
17 void caam_hal_ctrl_init(vaddr_t baseaddr);
18 
19 /*
20  * Returns the number of Job Ring supported
21  *
22  * @baseaddr  Controller base address
23  */
24 uint8_t caam_hal_ctrl_jrnum(vaddr_t baseaddr);
25 
26 /*
27  * If Hash operation is supported, returns the Maximum Hash Algorithm
28  * supported by the HW else UINT8_MAX
29  *
30  * @baseaddr  Controller base address
31  */
32 uint8_t caam_hal_ctrl_hash_limit(vaddr_t baseaddr);
33 
34 /*
35  * Returns the number of Public Key module supported
36  *
37  * @baseaddr  Controller base address
38  */
39 uint8_t caam_hal_ctrl_pknum(vaddr_t baseaddr);
40 
41 /*
42  * Returns if the HW support the split key operation.
43  *
44  * @baseaddr  Controller base address
45  */
46 bool caam_hal_ctrl_splitkey_support(vaddr_t baseaddr);
47 
48 /*
49  * Returns the CAAM Era
50  *
51  * @baseaddr  Controller base address
52  */
53 uint8_t caam_hal_ctrl_era(vaddr_t baseaddr);
54 
55 /*
56  * Increment the CAAM PRIBLOB field
57  *
58  * @baseaddr  Controller base address
59  */
60 void caam_hal_ctrl_inc_priblob(vaddr_t baseaddr);
61 #endif /* __CAAM_HAL_CTRL_H__ */
62