1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/reset.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24
25 #include "gpiolib.h"
26 #include "gpiolib-acpi.h"
27
28 #define GPIO_SWPORTA_DR 0x00
29 #define GPIO_SWPORTA_DDR 0x04
30 #define GPIO_SWPORTB_DR 0x0c
31 #define GPIO_SWPORTB_DDR 0x10
32 #define GPIO_SWPORTC_DR 0x18
33 #define GPIO_SWPORTC_DDR 0x1c
34 #define GPIO_SWPORTD_DR 0x24
35 #define GPIO_SWPORTD_DDR 0x28
36 #define GPIO_INTEN 0x30
37 #define GPIO_INTMASK 0x34
38 #define GPIO_INTTYPE_LEVEL 0x38
39 #define GPIO_INT_POLARITY 0x3c
40 #define GPIO_INTSTATUS 0x40
41 #define GPIO_PORTA_DEBOUNCE 0x48
42 #define GPIO_PORTA_EOI 0x4c
43 #define GPIO_EXT_PORTA 0x50
44 #define GPIO_EXT_PORTB 0x54
45 #define GPIO_EXT_PORTC 0x58
46 #define GPIO_EXT_PORTD 0x5c
47
48 #define DWAPB_DRIVER_NAME "gpio-dwapb"
49 #define DWAPB_MAX_PORTS 4
50 #define DWAPB_MAX_GPIOS 32
51
52 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
53 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
54 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
55
56 #define GPIO_REG_OFFSET_V2 1
57
58 #define GPIO_INTMASK_V2 0x44
59 #define GPIO_INTTYPE_LEVEL_V2 0x34
60 #define GPIO_INT_POLARITY_V2 0x38
61 #define GPIO_INTSTATUS_V2 0x3c
62 #define GPIO_PORTA_EOI_V2 0x40
63
64 #define DWAPB_NR_CLOCKS 2
65
66 struct dwapb_gpio;
67
68 struct dwapb_port_property {
69 struct fwnode_handle *fwnode;
70 unsigned int idx;
71 unsigned int ngpio;
72 unsigned int gpio_base;
73 int irq[DWAPB_MAX_GPIOS];
74 };
75
76 struct dwapb_platform_data {
77 struct dwapb_port_property *properties;
78 unsigned int nports;
79 };
80
81 #ifdef CONFIG_PM_SLEEP
82 /* Store GPIO context across system-wide suspend/resume transitions */
83 struct dwapb_context {
84 u32 data;
85 u32 dir;
86 u32 ext;
87 u32 int_en;
88 u32 int_mask;
89 u32 int_type;
90 u32 int_pol;
91 u32 int_deb;
92 u32 wake_en;
93 };
94 #endif
95
96 struct dwapb_gpio_port_irqchip {
97 struct irq_chip irqchip;
98 unsigned int nr_irqs;
99 unsigned int irq[DWAPB_MAX_GPIOS];
100 };
101
102 struct dwapb_gpio_port {
103 struct gpio_chip gc;
104 struct dwapb_gpio_port_irqchip *pirq;
105 struct dwapb_gpio *gpio;
106 #ifdef CONFIG_PM_SLEEP
107 struct dwapb_context *ctx;
108 #endif
109 unsigned int idx;
110 };
111 #define to_dwapb_gpio(_gc) \
112 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
113
114 struct dwapb_gpio {
115 struct device *dev;
116 void __iomem *regs;
117 struct dwapb_gpio_port *ports;
118 unsigned int nr_ports;
119 unsigned int flags;
120 struct reset_control *rst;
121 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
122 };
123
gpio_reg_v2_convert(unsigned int offset)124 static inline u32 gpio_reg_v2_convert(unsigned int offset)
125 {
126 switch (offset) {
127 case GPIO_INTMASK:
128 return GPIO_INTMASK_V2;
129 case GPIO_INTTYPE_LEVEL:
130 return GPIO_INTTYPE_LEVEL_V2;
131 case GPIO_INT_POLARITY:
132 return GPIO_INT_POLARITY_V2;
133 case GPIO_INTSTATUS:
134 return GPIO_INTSTATUS_V2;
135 case GPIO_PORTA_EOI:
136 return GPIO_PORTA_EOI_V2;
137 }
138
139 return offset;
140 }
141
gpio_reg_convert(struct dwapb_gpio * gpio,unsigned int offset)142 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
143 {
144 if (gpio->flags & GPIO_REG_OFFSET_V2)
145 return gpio_reg_v2_convert(offset);
146
147 return offset;
148 }
149
dwapb_read(struct dwapb_gpio * gpio,unsigned int offset)150 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
151 {
152 struct gpio_chip *gc = &gpio->ports[0].gc;
153 void __iomem *reg_base = gpio->regs;
154
155 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
156 }
157
dwapb_write(struct dwapb_gpio * gpio,unsigned int offset,u32 val)158 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
159 u32 val)
160 {
161 struct gpio_chip *gc = &gpio->ports[0].gc;
162 void __iomem *reg_base = gpio->regs;
163
164 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
165 }
166
dwapb_offs_to_port(struct dwapb_gpio * gpio,unsigned int offs)167 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
168 {
169 struct dwapb_gpio_port *port;
170 int i;
171
172 for (i = 0; i < gpio->nr_ports; i++) {
173 port = &gpio->ports[i];
174 if (port->idx == offs / DWAPB_MAX_GPIOS)
175 return port;
176 }
177
178 return NULL;
179 }
180
dwapb_toggle_trigger(struct dwapb_gpio * gpio,unsigned int offs)181 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
182 {
183 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
184 struct gpio_chip *gc;
185 u32 pol;
186 int val;
187
188 if (!port)
189 return;
190 gc = &port->gc;
191
192 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
193 /* Just read the current value right out of the data register */
194 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
195 if (val)
196 pol &= ~BIT(offs);
197 else
198 pol |= BIT(offs);
199
200 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
201 }
202
dwapb_do_irq(struct dwapb_gpio * gpio)203 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
204 {
205 struct gpio_chip *gc = &gpio->ports[0].gc;
206 unsigned long irq_status;
207 irq_hw_number_t hwirq;
208
209 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
210 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
211 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
212 u32 irq_type = irq_get_trigger_type(gpio_irq);
213
214 generic_handle_irq(gpio_irq);
215
216 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
217 dwapb_toggle_trigger(gpio, hwirq);
218 }
219
220 return irq_status;
221 }
222
dwapb_irq_handler(struct irq_desc * desc)223 static void dwapb_irq_handler(struct irq_desc *desc)
224 {
225 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
226 struct irq_chip *chip = irq_desc_get_chip(desc);
227
228 chained_irq_enter(chip, desc);
229 dwapb_do_irq(gpio);
230 chained_irq_exit(chip, desc);
231 }
232
dwapb_irq_handler_mfd(int irq,void * dev_id)233 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
234 {
235 return IRQ_RETVAL(dwapb_do_irq(dev_id));
236 }
237
dwapb_irq_ack(struct irq_data * d)238 static void dwapb_irq_ack(struct irq_data *d)
239 {
240 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
241 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
242 u32 val = BIT(irqd_to_hwirq(d));
243 unsigned long flags;
244
245 spin_lock_irqsave(&gc->bgpio_lock, flags);
246 dwapb_write(gpio, GPIO_PORTA_EOI, val);
247 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
248 }
249
dwapb_irq_mask(struct irq_data * d)250 static void dwapb_irq_mask(struct irq_data *d)
251 {
252 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
253 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
254 unsigned long flags;
255 u32 val;
256
257 spin_lock_irqsave(&gc->bgpio_lock, flags);
258 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
259 dwapb_write(gpio, GPIO_INTMASK, val);
260 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
261 }
262
dwapb_irq_unmask(struct irq_data * d)263 static void dwapb_irq_unmask(struct irq_data *d)
264 {
265 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
266 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
267 unsigned long flags;
268 u32 val;
269
270 spin_lock_irqsave(&gc->bgpio_lock, flags);
271 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
272 dwapb_write(gpio, GPIO_INTMASK, val);
273 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
274 }
275
dwapb_irq_enable(struct irq_data * d)276 static void dwapb_irq_enable(struct irq_data *d)
277 {
278 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
279 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
280 unsigned long flags;
281 u32 val;
282
283 spin_lock_irqsave(&gc->bgpio_lock, flags);
284 val = dwapb_read(gpio, GPIO_INTEN);
285 val |= BIT(irqd_to_hwirq(d));
286 dwapb_write(gpio, GPIO_INTEN, val);
287 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
288 }
289
dwapb_irq_disable(struct irq_data * d)290 static void dwapb_irq_disable(struct irq_data *d)
291 {
292 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
293 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
294 unsigned long flags;
295 u32 val;
296
297 spin_lock_irqsave(&gc->bgpio_lock, flags);
298 val = dwapb_read(gpio, GPIO_INTEN);
299 val &= ~BIT(irqd_to_hwirq(d));
300 dwapb_write(gpio, GPIO_INTEN, val);
301 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
302 }
303
dwapb_irq_set_type(struct irq_data * d,u32 type)304 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
305 {
306 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
307 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
308 irq_hw_number_t bit = irqd_to_hwirq(d);
309 unsigned long level, polarity, flags;
310
311 spin_lock_irqsave(&gc->bgpio_lock, flags);
312 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
313 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
314
315 switch (type) {
316 case IRQ_TYPE_EDGE_BOTH:
317 level |= BIT(bit);
318 dwapb_toggle_trigger(gpio, bit);
319 break;
320 case IRQ_TYPE_EDGE_RISING:
321 level |= BIT(bit);
322 polarity |= BIT(bit);
323 break;
324 case IRQ_TYPE_EDGE_FALLING:
325 level |= BIT(bit);
326 polarity &= ~BIT(bit);
327 break;
328 case IRQ_TYPE_LEVEL_HIGH:
329 level &= ~BIT(bit);
330 polarity |= BIT(bit);
331 break;
332 case IRQ_TYPE_LEVEL_LOW:
333 level &= ~BIT(bit);
334 polarity &= ~BIT(bit);
335 break;
336 }
337
338 if (type & IRQ_TYPE_LEVEL_MASK)
339 irq_set_handler_locked(d, handle_level_irq);
340 else if (type & IRQ_TYPE_EDGE_BOTH)
341 irq_set_handler_locked(d, handle_edge_irq);
342
343 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
344 if (type != IRQ_TYPE_EDGE_BOTH)
345 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
346 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
347
348 return 0;
349 }
350
351 #ifdef CONFIG_PM_SLEEP
dwapb_irq_set_wake(struct irq_data * d,unsigned int enable)352 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
353 {
354 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
355 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
356 struct dwapb_context *ctx = gpio->ports[0].ctx;
357 irq_hw_number_t bit = irqd_to_hwirq(d);
358
359 if (enable)
360 ctx->wake_en |= BIT(bit);
361 else
362 ctx->wake_en &= ~BIT(bit);
363
364 return 0;
365 }
366 #endif
367
dwapb_gpio_set_debounce(struct gpio_chip * gc,unsigned offset,unsigned debounce)368 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
369 unsigned offset, unsigned debounce)
370 {
371 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
372 struct dwapb_gpio *gpio = port->gpio;
373 unsigned long flags, val_deb;
374 unsigned long mask = BIT(offset);
375
376 spin_lock_irqsave(&gc->bgpio_lock, flags);
377
378 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
379 if (debounce)
380 val_deb |= mask;
381 else
382 val_deb &= ~mask;
383 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
384
385 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
386
387 return 0;
388 }
389
dwapb_gpio_set_config(struct gpio_chip * gc,unsigned offset,unsigned long config)390 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
391 unsigned long config)
392 {
393 u32 debounce;
394
395 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
396 return -ENOTSUPP;
397
398 debounce = pinconf_to_config_argument(config);
399 return dwapb_gpio_set_debounce(gc, offset, debounce);
400 }
401
dwapb_convert_irqs(struct dwapb_gpio_port_irqchip * pirq,struct dwapb_port_property * pp)402 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
403 struct dwapb_port_property *pp)
404 {
405 int i;
406
407 /* Group all available IRQs into an array of parental IRQs. */
408 for (i = 0; i < pp->ngpio; ++i) {
409 if (!pp->irq[i])
410 continue;
411
412 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
413 }
414
415 return pirq->nr_irqs ? 0 : -ENOENT;
416 }
417
dwapb_configure_irqs(struct dwapb_gpio * gpio,struct dwapb_gpio_port * port,struct dwapb_port_property * pp)418 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
419 struct dwapb_gpio_port *port,
420 struct dwapb_port_property *pp)
421 {
422 struct dwapb_gpio_port_irqchip *pirq;
423 struct gpio_chip *gc = &port->gc;
424 struct gpio_irq_chip *girq;
425 int err;
426
427 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
428 if (!pirq)
429 return;
430
431 if (dwapb_convert_irqs(pirq, pp)) {
432 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
433 goto err_kfree_pirq;
434 }
435
436 girq = &gc->irq;
437 girq->handler = handle_bad_irq;
438 girq->default_type = IRQ_TYPE_NONE;
439
440 port->pirq = pirq;
441 pirq->irqchip.name = DWAPB_DRIVER_NAME;
442 pirq->irqchip.irq_ack = dwapb_irq_ack;
443 pirq->irqchip.irq_mask = dwapb_irq_mask;
444 pirq->irqchip.irq_unmask = dwapb_irq_unmask;
445 pirq->irqchip.irq_set_type = dwapb_irq_set_type;
446 pirq->irqchip.irq_enable = dwapb_irq_enable;
447 pirq->irqchip.irq_disable = dwapb_irq_disable;
448 #ifdef CONFIG_PM_SLEEP
449 pirq->irqchip.irq_set_wake = dwapb_irq_set_wake;
450 #endif
451
452 /*
453 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
454 * IRQ lane shared between several devices. In that case the parental
455 * IRQ has to be handled in the shared way so to be properly delivered
456 * to all the connected devices.
457 */
458 if (has_acpi_companion(gpio->dev)) {
459 girq->num_parents = 0;
460 girq->parents = NULL;
461 girq->parent_handler = NULL;
462
463 err = devm_request_irq(gpio->dev, pp->irq[0],
464 dwapb_irq_handler_mfd,
465 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
466 if (err) {
467 dev_err(gpio->dev, "error requesting IRQ\n");
468 goto err_kfree_pirq;
469 }
470 } else {
471 girq->num_parents = pirq->nr_irqs;
472 girq->parents = pirq->irq;
473 girq->parent_handler_data = gpio;
474 girq->parent_handler = dwapb_irq_handler;
475 }
476
477 girq->chip = &pirq->irqchip;
478
479 return;
480
481 err_kfree_pirq:
482 devm_kfree(gpio->dev, pirq);
483 }
484
dwapb_gpio_add_port(struct dwapb_gpio * gpio,struct dwapb_port_property * pp,unsigned int offs)485 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
486 struct dwapb_port_property *pp,
487 unsigned int offs)
488 {
489 struct dwapb_gpio_port *port;
490 void __iomem *dat, *set, *dirout;
491 int err;
492
493 port = &gpio->ports[offs];
494 port->gpio = gpio;
495 port->idx = pp->idx;
496
497 #ifdef CONFIG_PM_SLEEP
498 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
499 if (!port->ctx)
500 return -ENOMEM;
501 #endif
502
503 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
504 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
505 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
506
507 /* This registers 32 GPIO lines per port */
508 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
509 NULL, 0);
510 if (err) {
511 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
512 port->idx);
513 return err;
514 }
515
516 #ifdef CONFIG_OF_GPIO
517 port->gc.of_node = to_of_node(pp->fwnode);
518 #endif
519 port->gc.ngpio = pp->ngpio;
520 port->gc.base = pp->gpio_base;
521
522 /* Only port A support debounce */
523 if (pp->idx == 0)
524 port->gc.set_config = dwapb_gpio_set_config;
525
526 /* Only port A can provide interrupts in all configurations of the IP */
527 if (pp->idx == 0)
528 dwapb_configure_irqs(gpio, port, pp);
529
530 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
531 if (err) {
532 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
533 port->idx);
534 return err;
535 }
536
537 return 0;
538 }
539
dwapb_get_irq(struct device * dev,struct fwnode_handle * fwnode,struct dwapb_port_property * pp)540 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
541 struct dwapb_port_property *pp)
542 {
543 int irq, j;
544
545 for (j = 0; j < pp->ngpio; j++) {
546 if (has_acpi_companion(dev))
547 irq = platform_get_irq_optional(to_platform_device(dev), j);
548 else
549 irq = fwnode_irq_get(fwnode, j);
550 if (irq > 0)
551 pp->irq[j] = irq;
552 }
553 }
554
dwapb_gpio_get_pdata(struct device * dev)555 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
556 {
557 struct fwnode_handle *fwnode;
558 struct dwapb_platform_data *pdata;
559 struct dwapb_port_property *pp;
560 int nports;
561 int i;
562
563 nports = device_get_child_node_count(dev);
564 if (nports == 0)
565 return ERR_PTR(-ENODEV);
566
567 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
568 if (!pdata)
569 return ERR_PTR(-ENOMEM);
570
571 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
572 if (!pdata->properties)
573 return ERR_PTR(-ENOMEM);
574
575 pdata->nports = nports;
576
577 i = 0;
578 device_for_each_child_node(dev, fwnode) {
579 pp = &pdata->properties[i++];
580 pp->fwnode = fwnode;
581
582 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
583 pp->idx >= DWAPB_MAX_PORTS) {
584 dev_err(dev,
585 "missing/invalid port index for port%d\n", i);
586 fwnode_handle_put(fwnode);
587 return ERR_PTR(-EINVAL);
588 }
589
590 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
591 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
592 dev_info(dev,
593 "failed to get number of gpios for port%d\n",
594 i);
595 pp->ngpio = DWAPB_MAX_GPIOS;
596 }
597
598 pp->gpio_base = -1;
599
600 /* For internal use only, new platforms mustn't exercise this */
601 if (is_software_node(fwnode))
602 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
603
604 /*
605 * Only port A can provide interrupts in all configurations of
606 * the IP.
607 */
608 if (pp->idx == 0)
609 dwapb_get_irq(dev, fwnode, pp);
610 }
611
612 return pdata;
613 }
614
dwapb_assert_reset(void * data)615 static void dwapb_assert_reset(void *data)
616 {
617 struct dwapb_gpio *gpio = data;
618
619 reset_control_assert(gpio->rst);
620 }
621
dwapb_get_reset(struct dwapb_gpio * gpio)622 static int dwapb_get_reset(struct dwapb_gpio *gpio)
623 {
624 int err;
625
626 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
627 if (IS_ERR(gpio->rst))
628 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
629 "Cannot get reset descriptor\n");
630
631 err = reset_control_deassert(gpio->rst);
632 if (err) {
633 dev_err(gpio->dev, "Cannot deassert reset lane\n");
634 return err;
635 }
636
637 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
638 }
639
dwapb_disable_clks(void * data)640 static void dwapb_disable_clks(void *data)
641 {
642 struct dwapb_gpio *gpio = data;
643
644 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
645 }
646
dwapb_get_clks(struct dwapb_gpio * gpio)647 static int dwapb_get_clks(struct dwapb_gpio *gpio)
648 {
649 int err;
650
651 /* Optional bus and debounce clocks */
652 gpio->clks[0].id = "bus";
653 gpio->clks[1].id = "db";
654 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
655 gpio->clks);
656 if (err) {
657 dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n");
658 return err;
659 }
660
661 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
662 if (err) {
663 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
664 return err;
665 }
666
667 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
668 }
669
670 static const struct of_device_id dwapb_of_match[] = {
671 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
672 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
673 { /* Sentinel */ }
674 };
675 MODULE_DEVICE_TABLE(of, dwapb_of_match);
676
677 static const struct acpi_device_id dwapb_acpi_match[] = {
678 {"HISI0181", 0},
679 {"APMC0D07", 0},
680 {"APMC0D81", GPIO_REG_OFFSET_V2},
681 { }
682 };
683 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
684
dwapb_gpio_probe(struct platform_device * pdev)685 static int dwapb_gpio_probe(struct platform_device *pdev)
686 {
687 unsigned int i;
688 struct dwapb_gpio *gpio;
689 int err;
690 struct dwapb_platform_data *pdata;
691 struct device *dev = &pdev->dev;
692
693 pdata = dwapb_gpio_get_pdata(dev);
694 if (IS_ERR(pdata))
695 return PTR_ERR(pdata);
696
697 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
698 if (!gpio)
699 return -ENOMEM;
700
701 gpio->dev = &pdev->dev;
702 gpio->nr_ports = pdata->nports;
703
704 err = dwapb_get_reset(gpio);
705 if (err)
706 return err;
707
708 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
709 sizeof(*gpio->ports), GFP_KERNEL);
710 if (!gpio->ports)
711 return -ENOMEM;
712
713 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
714 if (IS_ERR(gpio->regs))
715 return PTR_ERR(gpio->regs);
716
717 err = dwapb_get_clks(gpio);
718 if (err)
719 return err;
720
721 gpio->flags = (uintptr_t)device_get_match_data(dev);
722
723 for (i = 0; i < gpio->nr_ports; i++) {
724 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
725 if (err)
726 return err;
727 }
728
729 platform_set_drvdata(pdev, gpio);
730
731 return 0;
732 }
733
734 #ifdef CONFIG_PM_SLEEP
dwapb_gpio_suspend(struct device * dev)735 static int dwapb_gpio_suspend(struct device *dev)
736 {
737 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
738 struct gpio_chip *gc = &gpio->ports[0].gc;
739 unsigned long flags;
740 int i;
741
742 spin_lock_irqsave(&gc->bgpio_lock, flags);
743 for (i = 0; i < gpio->nr_ports; i++) {
744 unsigned int offset;
745 unsigned int idx = gpio->ports[i].idx;
746 struct dwapb_context *ctx = gpio->ports[i].ctx;
747
748 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
749 ctx->dir = dwapb_read(gpio, offset);
750
751 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
752 ctx->data = dwapb_read(gpio, offset);
753
754 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
755 ctx->ext = dwapb_read(gpio, offset);
756
757 /* Only port A can provide interrupts */
758 if (idx == 0) {
759 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
760 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
761 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
762 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
763 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
764
765 /* Mask out interrupts */
766 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
767 }
768 }
769 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
770
771 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
772
773 return 0;
774 }
775
dwapb_gpio_resume(struct device * dev)776 static int dwapb_gpio_resume(struct device *dev)
777 {
778 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
779 struct gpio_chip *gc = &gpio->ports[0].gc;
780 unsigned long flags;
781 int i, err;
782
783 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
784 if (err) {
785 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
786 return err;
787 }
788
789 spin_lock_irqsave(&gc->bgpio_lock, flags);
790 for (i = 0; i < gpio->nr_ports; i++) {
791 unsigned int offset;
792 unsigned int idx = gpio->ports[i].idx;
793 struct dwapb_context *ctx = gpio->ports[i].ctx;
794
795 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
796 dwapb_write(gpio, offset, ctx->data);
797
798 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
799 dwapb_write(gpio, offset, ctx->dir);
800
801 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
802 dwapb_write(gpio, offset, ctx->ext);
803
804 /* Only port A can provide interrupts */
805 if (idx == 0) {
806 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
807 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
808 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
809 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
810 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
811
812 /* Clear out spurious interrupts */
813 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
814 }
815 }
816 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
817
818 return 0;
819 }
820 #endif
821
822 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
823 dwapb_gpio_resume);
824
825 static struct platform_driver dwapb_gpio_driver = {
826 .driver = {
827 .name = DWAPB_DRIVER_NAME,
828 .pm = &dwapb_gpio_pm_ops,
829 .of_match_table = dwapb_of_match,
830 .acpi_match_table = dwapb_acpi_match,
831 },
832 .probe = dwapb_gpio_probe,
833 };
834
835 module_platform_driver(dwapb_gpio_driver);
836
837 MODULE_LICENSE("GPL");
838 MODULE_AUTHOR("Jamie Iles");
839 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
840 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
841