1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 */
6
7 #define LOG_CATEGORY UCLASS_GPIO
8
9 #include <common.h>
10 #include <clk.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <log.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/stm32.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <dm/device_compat.h>
19 #include <linux/bitops.h>
20 #include <linux/errno.h>
21 #include <linux/io.h>
22
23 #define STM32_GPIOS_PER_BANK 16
24
25 #define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
26 #define MODE_BITS_MASK 3
27 #define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
28
29 #define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
30 #define PUPD_MASK 3
31
32 #define OTYPE_BITS(gpio_pin) (gpio_pin)
33 #define OTYPE_MSK 1
34
stm32_gpio_set_moder(struct stm32_gpio_regs * regs,int idx,int mode)35 static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
36 int idx,
37 int mode)
38 {
39 int bits_index;
40 int mask;
41
42 bits_index = MODE_BITS(idx);
43 mask = MODE_BITS_MASK << bits_index;
44
45 clrsetbits_le32(®s->moder, mask, mode << bits_index);
46 }
47
stm32_gpio_get_moder(struct stm32_gpio_regs * regs,int idx)48 static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
49 {
50 return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
51 }
52
stm32_gpio_set_otype(struct stm32_gpio_regs * regs,int idx,enum stm32_gpio_otype otype)53 static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
54 int idx,
55 enum stm32_gpio_otype otype)
56 {
57 int bits;
58
59 bits = OTYPE_BITS(idx);
60 clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
61 }
62
stm32_gpio_get_otype(struct stm32_gpio_regs * regs,int idx)63 static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
64 int idx)
65 {
66 return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
67 }
68
stm32_gpio_set_pupd(struct stm32_gpio_regs * regs,int idx,enum stm32_gpio_pupd pupd)69 static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
70 int idx,
71 enum stm32_gpio_pupd pupd)
72 {
73 int bits;
74
75 bits = PUPD_BITS(idx);
76 clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
77 }
78
stm32_gpio_get_pupd(struct stm32_gpio_regs * regs,int idx)79 static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
80 int idx)
81 {
82 return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
83 }
84
85 /*
86 * convert gpio offset to gpio index taking into account gpio holes
87 * into gpio bank
88 */
stm32_offset_to_index(struct udevice * dev,unsigned int offset)89 int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
90 {
91 struct stm32_gpio_priv *priv = dev_get_priv(dev);
92 unsigned int idx = 0;
93 int i;
94
95 for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
96 if (priv->gpio_range & BIT(i)) {
97 if (idx == offset)
98 return idx;
99 idx++;
100 }
101 }
102 /* shouldn't happen */
103 return -EINVAL;
104 }
105
stm32_gpio_direction_input(struct udevice * dev,unsigned offset)106 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
107 {
108 struct stm32_gpio_priv *priv = dev_get_priv(dev);
109 struct stm32_gpio_regs *regs = priv->regs;
110 int idx;
111
112 idx = stm32_offset_to_index(dev, offset);
113 if (idx < 0)
114 return idx;
115
116 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
117
118 return 0;
119 }
120
stm32_gpio_direction_output(struct udevice * dev,unsigned offset,int value)121 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
122 int value)
123 {
124 struct stm32_gpio_priv *priv = dev_get_priv(dev);
125 struct stm32_gpio_regs *regs = priv->regs;
126 int idx;
127
128 idx = stm32_offset_to_index(dev, offset);
129 if (idx < 0)
130 return idx;
131
132 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
133
134 writel(BSRR_BIT(idx, value), ®s->bsrr);
135
136 return 0;
137 }
138
stm32_gpio_get_value(struct udevice * dev,unsigned offset)139 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
140 {
141 struct stm32_gpio_priv *priv = dev_get_priv(dev);
142 struct stm32_gpio_regs *regs = priv->regs;
143 int idx;
144
145 idx = stm32_offset_to_index(dev, offset);
146 if (idx < 0)
147 return idx;
148
149 return readl(®s->idr) & BIT(idx) ? 1 : 0;
150 }
151
stm32_gpio_set_value(struct udevice * dev,unsigned offset,int value)152 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
153 {
154 struct stm32_gpio_priv *priv = dev_get_priv(dev);
155 struct stm32_gpio_regs *regs = priv->regs;
156 int idx;
157
158 idx = stm32_offset_to_index(dev, offset);
159 if (idx < 0)
160 return idx;
161
162 writel(BSRR_BIT(idx, value), ®s->bsrr);
163
164 return 0;
165 }
166
stm32_gpio_get_function(struct udevice * dev,unsigned int offset)167 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
168 {
169 struct stm32_gpio_priv *priv = dev_get_priv(dev);
170 struct stm32_gpio_regs *regs = priv->regs;
171 int bits_index;
172 int mask;
173 int idx;
174 u32 mode;
175
176 idx = stm32_offset_to_index(dev, offset);
177 if (idx < 0)
178 return idx;
179
180 bits_index = MODE_BITS(idx);
181 mask = MODE_BITS_MASK << bits_index;
182
183 mode = (readl(®s->moder) & mask) >> bits_index;
184 if (mode == STM32_GPIO_MODE_OUT)
185 return GPIOF_OUTPUT;
186 if (mode == STM32_GPIO_MODE_IN)
187 return GPIOF_INPUT;
188 if (mode == STM32_GPIO_MODE_AN)
189 return GPIOF_UNUSED;
190
191 return GPIOF_FUNC;
192 }
193
stm32_gpio_set_dir_flags(struct udevice * dev,unsigned int offset,ulong flags)194 static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
195 ulong flags)
196 {
197 struct stm32_gpio_priv *priv = dev_get_priv(dev);
198 struct stm32_gpio_regs *regs = priv->regs;
199 int idx;
200
201 idx = stm32_offset_to_index(dev, offset);
202 if (idx < 0)
203 return idx;
204
205 if (flags & GPIOD_IS_OUT) {
206 int value = GPIOD_FLAGS_OUTPUT(flags);
207
208 if (flags & GPIOD_OPEN_DRAIN)
209 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
210 else
211 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
212 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
213 writel(BSRR_BIT(idx, value), ®s->bsrr);
214
215 } else if (flags & GPIOD_IS_IN) {
216 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
217 }
218 if (flags & GPIOD_PULL_UP)
219 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
220 else if (flags & GPIOD_PULL_DOWN)
221 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
222
223 return 0;
224 }
225
stm32_gpio_get_dir_flags(struct udevice * dev,unsigned int offset,ulong * flags)226 static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
227 ulong *flags)
228 {
229 struct stm32_gpio_priv *priv = dev_get_priv(dev);
230 struct stm32_gpio_regs *regs = priv->regs;
231 int idx;
232 ulong dir_flags = 0;
233
234 idx = stm32_offset_to_index(dev, offset);
235 if (idx < 0)
236 return idx;
237
238 switch (stm32_gpio_get_moder(regs, idx)) {
239 case STM32_GPIO_MODE_OUT:
240 dir_flags |= GPIOD_IS_OUT;
241 if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
242 dir_flags |= GPIOD_OPEN_DRAIN;
243 if (readl(®s->idr) & BIT(idx))
244 dir_flags |= GPIOD_IS_OUT_ACTIVE;
245 break;
246 case STM32_GPIO_MODE_IN:
247 dir_flags |= GPIOD_IS_IN;
248 break;
249 default:
250 break;
251 }
252 switch (stm32_gpio_get_pupd(regs, idx)) {
253 case STM32_GPIO_PUPD_UP:
254 dir_flags |= GPIOD_PULL_UP;
255 break;
256 case STM32_GPIO_PUPD_DOWN:
257 dir_flags |= GPIOD_PULL_DOWN;
258 break;
259 default:
260 break;
261 }
262 *flags = dir_flags;
263
264 return 0;
265 }
266
267 static const struct dm_gpio_ops gpio_stm32_ops = {
268 .direction_input = stm32_gpio_direction_input,
269 .direction_output = stm32_gpio_direction_output,
270 .get_value = stm32_gpio_get_value,
271 .set_value = stm32_gpio_set_value,
272 .get_function = stm32_gpio_get_function,
273 .set_dir_flags = stm32_gpio_set_dir_flags,
274 .get_dir_flags = stm32_gpio_get_dir_flags,
275 };
276
gpio_stm32_probe(struct udevice * dev)277 static int gpio_stm32_probe(struct udevice *dev)
278 {
279 struct stm32_gpio_priv *priv = dev_get_priv(dev);
280 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
281 struct ofnode_phandle_args args;
282 const char *name;
283 struct clk clk;
284 fdt_addr_t addr;
285 int ret, i;
286
287 addr = dev_read_addr(dev);
288 if (addr == FDT_ADDR_T_NONE)
289 return -EINVAL;
290
291 priv->regs = (struct stm32_gpio_regs *)addr;
292
293 name = dev_read_string(dev, "st,bank-name");
294 if (!name)
295 return -EINVAL;
296 uc_priv->bank_name = name;
297
298 i = 0;
299 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
300 NULL, 3, i, &args);
301
302 if (!ret && args.args_count < 3)
303 return -EINVAL;
304
305 if (ret == -ENOENT) {
306 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
307 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
308 }
309
310 while (ret != -ENOENT) {
311 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
312 args.args[0]);
313
314 uc_priv->gpio_count += args.args[2];
315
316 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
317 ++i, &args);
318 if (!ret && args.args_count < 3)
319 return -EINVAL;
320 }
321
322 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
323 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
324 priv->gpio_range);
325
326 ret = clk_get_by_index(dev, 0, &clk);
327 if (ret < 0)
328 return ret;
329
330 ret = clk_enable(&clk);
331
332 if (ret) {
333 dev_err(dev, "failed to enable clock\n");
334 return ret;
335 }
336 dev_dbg(dev, "clock enabled\n");
337
338 return 0;
339 }
340
341 U_BOOT_DRIVER(gpio_stm32) = {
342 .name = "gpio_stm32",
343 .id = UCLASS_GPIO,
344 .probe = gpio_stm32_probe,
345 .ops = &gpio_stm32_ops,
346 .flags = DM_UC_FLAG_SEQ_ALIAS,
347 .priv_auto = sizeof(struct stm32_gpio_priv),
348 };
349