1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2006,2009 Freescale Semiconductor, Inc.
4 *
5 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Changes for multibus/multiadapter I2C support.
7 */
8
9 #include <common.h>
10 #include <command.h>
11 #include <i2c.h> /* Functional interface */
12 #include <log.h>
13 #include <time.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/fsl_i2c.h> /* HW definitions */
17 #include <clk.h>
18 #include <dm.h>
19 #include <mapmem.h>
20 #include <linux/delay.h>
21
22 /* The maximum number of microseconds we will wait until another master has
23 * released the bus. If not defined in the board header file, then use a
24 * generic value.
25 */
26 #ifndef CONFIG_I2C_MBB_TIMEOUT
27 #define CONFIG_I2C_MBB_TIMEOUT 100000
28 #endif
29
30 /* The maximum number of microseconds we will wait for a read or write
31 * operation to complete. If not defined in the board header file, then use a
32 * generic value.
33 */
34 #ifndef CONFIG_I2C_TIMEOUT
35 #define CONFIG_I2C_TIMEOUT 100000
36 #endif
37
38 #define I2C_READ_BIT 1
39 #define I2C_WRITE_BIT 0
40
41 DECLARE_GLOBAL_DATA_PTR;
42
43 #if !CONFIG_IS_ENABLED(DM_I2C)
44 static const struct fsl_i2c_base *i2c_base[4] = {
45 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
46 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
47 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
48 #endif
49 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
50 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
51 #endif
52 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
53 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
54 #endif
55 };
56 #endif
57
58 /* I2C speed map for a DFSR value of 1 */
59
60 #ifdef __M68K__
61 /*
62 * Map I2C frequency dividers to FDR and DFSR values
63 *
64 * This structure is used to define the elements of a table that maps I2C
65 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
66 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
67 * Sampling Rate (DFSR) registers.
68 *
69 * The actual table should be defined in the board file, and it must be called
70 * fsl_i2c_speed_map[].
71 *
72 * The last entry of the table must have a value of {-1, X}, where X is same
73 * FDR/DFSR values as the second-to-last entry. This guarantees that any
74 * search through the array will always find a match.
75 *
76 * The values of the divider must be in increasing numerical order, i.e.
77 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
78 *
79 * For this table, the values are based on a value of 1 for the DFSR
80 * register. See the application note AN2919 "Determining the I2C Frequency
81 * Divider Ratio for SCL"
82 *
83 * ColdFire I2C frequency dividers for FDR values are different from
84 * PowerPC. The protocol to use the I2C module is still the same.
85 * A different table is defined and are based on MCF5xxx user manual.
86 *
87 */
88 static const struct {
89 unsigned short divider;
90 u8 fdr;
91 } fsl_i2c_speed_map[] = {
92 {20, 32}, {22, 33}, {24, 34}, {26, 35},
93 {28, 0}, {28, 36}, {30, 1}, {32, 37},
94 {34, 2}, {36, 38}, {40, 3}, {40, 39},
95 {44, 4}, {48, 5}, {48, 40}, {56, 6},
96 {56, 41}, {64, 42}, {68, 7}, {72, 43},
97 {80, 8}, {80, 44}, {88, 9}, {96, 41},
98 {104, 10}, {112, 42}, {128, 11}, {128, 43},
99 {144, 12}, {160, 13}, {160, 48}, {192, 14},
100 {192, 49}, {224, 50}, {240, 15}, {256, 51},
101 {288, 16}, {320, 17}, {320, 52}, {384, 18},
102 {384, 53}, {448, 54}, {480, 19}, {512, 55},
103 {576, 20}, {640, 21}, {640, 56}, {768, 22},
104 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
105 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
106 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
107 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
108 {-1, 31}
109 };
110 #endif
111
112 /**
113 * Set the I2C bus speed for a given I2C device
114 *
115 * @param base: the I2C device registers
116 * @i2c_clk: I2C bus clock frequency
117 * @speed: the desired speed of the bus
118 *
119 * The I2C device must be stopped before calling this function.
120 *
121 * The return value is the actual bus speed that is set.
122 */
set_i2c_bus_speed(const struct fsl_i2c_base * base,uint i2c_clk,uint speed)123 static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
124 uint i2c_clk, uint speed)
125 {
126 ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
127
128 /*
129 * We want to choose an FDR/DFSR that generates an I2C bus speed that
130 * is equal to or lower than the requested speed. That means that we
131 * want the first divider that is equal to or greater than the
132 * calculated divider.
133 */
134 #ifdef __PPC__
135 u8 dfsr, fdr = 0x31; /* Default if no FDR found */
136 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
137 ushort a, b, ga, gb;
138 ulong c_div, est_div;
139
140 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
141 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
142 #else
143 /* Condition 1: dfsr <= 50/T */
144 dfsr = (5 * (i2c_clk / 1000)) / 100000;
145 #endif
146 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
147 fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
148 speed = i2c_clk / divider; /* Fake something */
149 #else
150 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
151 if (!dfsr)
152 dfsr = 1;
153
154 est_div = ~0;
155 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
156 for (gb = 0; gb < 8; gb++) {
157 b = 16 << gb;
158 c_div = b * (a + ((3 * dfsr) / b) * 2);
159 if (c_div > divider && c_div < est_div) {
160 ushort bin_gb, bin_ga;
161
162 est_div = c_div;
163 bin_gb = gb << 2;
164 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
165 fdr = bin_gb | bin_ga;
166 speed = i2c_clk / est_div;
167
168 debug("FDR: 0x%.2x, ", fdr);
169 debug("div: %ld, ", est_div);
170 debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
171 debug("a: %d, b: %d, speed: %d\n", a, b, speed);
172
173 /* Condition 2 not accounted for */
174 debug("Tr <= %d ns\n",
175 (b - 3 * dfsr) * 1000000 /
176 (i2c_clk / 1000));
177 }
178 }
179 if (a == 20)
180 a += 2;
181 if (a == 24)
182 a += 4;
183 }
184 debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
185 debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
186 #endif
187 writeb(dfsr, &base->dfsrr); /* set default filter */
188 writeb(fdr, &base->fdr); /* set bus speed */
189 #else
190 uint i;
191
192 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
193 if (fsl_i2c_speed_map[i].divider >= divider) {
194 u8 fdr;
195
196 fdr = fsl_i2c_speed_map[i].fdr;
197 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
198 writeb(fdr, &base->fdr); /* set bus speed */
199
200 break;
201 }
202 #endif
203 return speed;
204 }
205
206 #if !CONFIG_IS_ENABLED(DM_I2C)
get_i2c_clock(int bus)207 static uint get_i2c_clock(int bus)
208 {
209 if (bus)
210 return gd->arch.i2c2_clk; /* I2C2 clock */
211 else
212 return gd->arch.i2c1_clk; /* I2C1 clock */
213 }
214 #endif
215
fsl_i2c_fixup(const struct fsl_i2c_base * base)216 static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
217 {
218 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
219 unsigned long long timeval = 0;
220 int ret = -1;
221 uint flags = 0;
222
223 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
224 uint svr = get_svr();
225
226 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
227 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
228 flags = I2C_CR_BIT6;
229 #endif
230
231 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
232
233 timeval = get_ticks();
234 while (!(readb(&base->sr) & I2C_SR_MBB)) {
235 if ((get_ticks() - timeval) > timeout)
236 goto err;
237 }
238
239 if (readb(&base->sr) & I2C_SR_MAL) {
240 /* SDA is stuck low */
241 writeb(0, &base->cr);
242 udelay(100);
243 writeb(I2C_CR_MSTA | flags, &base->cr);
244 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
245 }
246
247 readb(&base->dr);
248
249 timeval = get_ticks();
250 while (!(readb(&base->sr) & I2C_SR_MIF)) {
251 if ((get_ticks() - timeval) > timeout)
252 goto err;
253 }
254 ret = 0;
255
256 err:
257 writeb(I2C_CR_MEN | flags, &base->cr);
258 writeb(0, &base->sr);
259 udelay(100);
260
261 return ret;
262 }
263
__i2c_init(const struct fsl_i2c_base * base,int speed,int slaveadd,int i2c_clk,int busnum)264 static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
265 slaveadd, int i2c_clk, int busnum)
266 {
267 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
268 unsigned long long timeval;
269
270 #ifdef CONFIG_SYS_I2C_INIT_BOARD
271 /* Call board specific i2c bus reset routine before accessing the
272 * environment, which might be in a chip on that bus. For details
273 * about this problem see doc/I2C_Edge_Conditions.
274 */
275 i2c_init_board();
276 #endif
277 writeb(0, &base->cr); /* stop I2C controller */
278 udelay(5); /* let it shutdown in peace */
279 set_i2c_bus_speed(base, i2c_clk, speed);
280 writeb(slaveadd << 1, &base->adr);/* write slave address */
281 writeb(0x0, &base->sr); /* clear status register */
282 writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
283
284 timeval = get_ticks();
285 while (readb(&base->sr) & I2C_SR_MBB) {
286 if ((get_ticks() - timeval) < timeout)
287 continue;
288
289 if (fsl_i2c_fixup(base))
290 debug("i2c_init: BUS#%d failed to init\n",
291 busnum);
292
293 break;
294 }
295 }
296
i2c_wait4bus(const struct fsl_i2c_base * base)297 static int i2c_wait4bus(const struct fsl_i2c_base *base)
298 {
299 unsigned long long timeval = get_ticks();
300 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
301
302 while (readb(&base->sr) & I2C_SR_MBB) {
303 if ((get_ticks() - timeval) > timeout)
304 return -1;
305 }
306
307 return 0;
308 }
309
i2c_wait(const struct fsl_i2c_base * base,int write)310 static int i2c_wait(const struct fsl_i2c_base *base, int write)
311 {
312 u32 csr;
313 unsigned long long timeval = get_ticks();
314 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
315
316 do {
317 csr = readb(&base->sr);
318 if (!(csr & I2C_SR_MIF))
319 continue;
320 /* Read again to allow register to stabilise */
321 csr = readb(&base->sr);
322
323 writeb(0x0, &base->sr);
324
325 if (csr & I2C_SR_MAL) {
326 debug("%s: MAL\n", __func__);
327 return -1;
328 }
329
330 if (!(csr & I2C_SR_MCF)) {
331 debug("%s: unfinished\n", __func__);
332 return -1;
333 }
334
335 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
336 debug("%s: No RXACK\n", __func__);
337 return -1;
338 }
339
340 return 0;
341 } while ((get_ticks() - timeval) < timeout);
342
343 debug("%s: timed out\n", __func__);
344 return -1;
345 }
346
i2c_write_addr(const struct fsl_i2c_base * base,u8 dev,u8 dir,int rsta)347 static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
348 u8 dir, int rsta)
349 {
350 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
351 | (rsta ? I2C_CR_RSTA : 0),
352 &base->cr);
353
354 writeb((dev << 1) | dir, &base->dr);
355
356 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
357 return 0;
358
359 return 1;
360 }
361
__i2c_write_data(const struct fsl_i2c_base * base,u8 * data,int length)362 static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
363 int length)
364 {
365 int i;
366
367 for (i = 0; i < length; i++) {
368 writeb(data[i], &base->dr);
369
370 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
371 break;
372 }
373
374 return i;
375 }
376
__i2c_read_data(const struct fsl_i2c_base * base,u8 * data,int length)377 static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
378 int length)
379 {
380 int i;
381
382 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
383 &base->cr);
384
385 /* dummy read */
386 readb(&base->dr);
387
388 for (i = 0; i < length; i++) {
389 if (i2c_wait(base, I2C_READ_BIT) < 0)
390 break;
391
392 /* Generate ack on last next to last byte */
393 if (i == length - 2)
394 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
395 &base->cr);
396
397 /* Do not generate stop on last byte */
398 if (i == length - 1)
399 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
400 &base->cr);
401
402 data[i] = readb(&base->dr);
403 }
404
405 return i;
406 }
407
__i2c_read(const struct fsl_i2c_base * base,u8 chip_addr,u8 * offset,int olen,u8 * data,int dlen)408 static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
409 int olen, u8 *data, int dlen)
410 {
411 int ret = -1; /* signal error */
412
413 if (i2c_wait4bus(base) < 0)
414 return -1;
415
416 /* Some drivers use offset lengths in excess of 4 bytes. These drivers
417 * adhere to the following convention:
418 * - the offset length is passed as negative (that is, the absolute
419 * value of olen is the actual offset length)
420 * - the offset itself is passed in data, which is overwritten by the
421 * subsequent read operation
422 */
423 if (olen < 0) {
424 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
425 ret = __i2c_write_data(base, data, -olen);
426
427 if (ret != -olen)
428 return -1;
429
430 if (dlen && i2c_write_addr(base, chip_addr,
431 I2C_READ_BIT, 1) != 0)
432 ret = __i2c_read_data(base, data, dlen);
433 } else {
434 if ((!dlen || olen > 0) &&
435 i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
436 __i2c_write_data(base, offset, olen) == olen)
437 ret = 0; /* No error so far */
438
439 if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
440 olen ? 1 : 0) != 0)
441 ret = __i2c_read_data(base, data, dlen);
442 }
443
444 writeb(I2C_CR_MEN, &base->cr);
445
446 if (i2c_wait4bus(base)) /* Wait until STOP */
447 debug("i2c_read: wait4bus timed out\n");
448
449 if (ret == dlen)
450 return 0;
451
452 return -1;
453 }
454
__i2c_write(const struct fsl_i2c_base * base,u8 chip_addr,u8 * offset,int olen,u8 * data,int dlen)455 static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
456 u8 *offset, int olen, u8 *data, int dlen)
457 {
458 int ret = -1; /* signal error */
459
460 if (i2c_wait4bus(base) < 0)
461 return -1;
462
463 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
464 __i2c_write_data(base, offset, olen) == olen) {
465 ret = __i2c_write_data(base, data, dlen);
466 }
467
468 writeb(I2C_CR_MEN, &base->cr);
469 if (i2c_wait4bus(base)) /* Wait until STOP */
470 debug("i2c_write: wait4bus timed out\n");
471
472 if (ret == dlen)
473 return 0;
474
475 return -1;
476 }
477
__i2c_probe_chip(const struct fsl_i2c_base * base,uchar chip)478 static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
479 {
480 /* For unknown reason the controller will ACK when
481 * probing for a slave with the same address, so skip
482 * it.
483 */
484 if (chip == (readb(&base->adr) >> 1))
485 return -1;
486
487 return __i2c_read(base, chip, 0, 0, NULL, 0);
488 }
489
__i2c_set_bus_speed(const struct fsl_i2c_base * base,uint speed,int i2c_clk)490 static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
491 uint speed, int i2c_clk)
492 {
493 writeb(0, &base->cr); /* stop controller */
494 set_i2c_bus_speed(base, i2c_clk, speed);
495 writeb(I2C_CR_MEN, &base->cr); /* start controller */
496
497 return 0;
498 }
499
500 #if !CONFIG_IS_ENABLED(DM_I2C)
fsl_i2c_init(struct i2c_adapter * adap,int speed,int slaveadd)501 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
502 {
503 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
504 get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
505 }
506
fsl_i2c_probe_chip(struct i2c_adapter * adap,uchar chip)507 static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
508 {
509 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
510 }
511
fsl_i2c_read(struct i2c_adapter * adap,u8 chip_addr,uint offset,int olen,u8 * data,int dlen)512 static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
513 int olen, u8 *data, int dlen)
514 {
515 u8 *o = (u8 *)&offset;
516
517 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
518 olen, data, dlen);
519 }
520
fsl_i2c_write(struct i2c_adapter * adap,u8 chip_addr,uint offset,int olen,u8 * data,int dlen)521 static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
522 int olen, u8 *data, int dlen)
523 {
524 u8 *o = (u8 *)&offset;
525
526 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
527 olen, data, dlen);
528 }
529
fsl_i2c_set_bus_speed(struct i2c_adapter * adap,uint speed)530 static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
531 {
532 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
533 get_i2c_clock(adap->hwadapnr));
534 }
535
536 /*
537 * Register fsl i2c adapters
538 */
539 U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
540 fsl_i2c_write, fsl_i2c_set_bus_speed,
541 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
542 0)
543 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
544 U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
545 fsl_i2c_write, fsl_i2c_set_bus_speed,
546 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
547 1)
548 #endif
549 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
550 U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
551 fsl_i2c_write, fsl_i2c_set_bus_speed,
552 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
553 2)
554 #endif
555 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
556 U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
557 fsl_i2c_write, fsl_i2c_set_bus_speed,
558 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
559 3)
560 #endif
561 #else /* CONFIG_DM_I2C */
562 static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
563 u32 chip_flags)
564 {
565 struct fsl_i2c_dev *dev = dev_get_priv(bus);
566
567 return __i2c_probe_chip(dev->base, chip_addr);
568 }
569
570 static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
571 {
572 struct fsl_i2c_dev *dev = dev_get_priv(bus);
573
574 return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
575 }
576
577 static int fsl_i2c_of_to_plat(struct udevice *bus)
578 {
579 struct fsl_i2c_dev *dev = dev_get_priv(bus);
580 struct clk clock;
581
582 dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
583
584 if (!dev->base)
585 return -ENOMEM;
586
587 dev->index = dev_read_u32_default(bus, "cell-index", -1);
588 dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
589 0x7f);
590 dev->speed = dev_read_u32_default(bus, "clock-frequency",
591 I2C_SPEED_FAST_RATE);
592
593 if (!clk_get_by_index(bus, 0, &clock))
594 dev->i2c_clk = clk_get_rate(&clock);
595 else
596 dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
597 gd->arch.i2c1_clk;
598
599 return 0;
600 }
601
602 static int fsl_i2c_probe(struct udevice *bus)
603 {
604 struct fsl_i2c_dev *dev = dev_get_priv(bus);
605
606 __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
607 dev->index);
608 return 0;
609 }
610
611 static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
612 {
613 struct fsl_i2c_dev *dev = dev_get_priv(bus);
614 struct i2c_msg *dmsg, *omsg, dummy;
615
616 memset(&dummy, 0, sizeof(struct i2c_msg));
617
618 /* We expect either two messages (one with an offset and one with the
619 * actual data) or one message (just data)
620 */
621 if (nmsgs > 2 || nmsgs == 0) {
622 debug("%s: Only one or two messages are supported.", __func__);
623 return -1;
624 }
625
626 omsg = nmsgs == 1 ? &dummy : msg;
627 dmsg = nmsgs == 1 ? msg : msg + 1;
628
629 if (dmsg->flags & I2C_M_RD)
630 return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
631 dmsg->buf, dmsg->len);
632 else
633 return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
634 dmsg->buf, dmsg->len);
635 }
636
637 static const struct dm_i2c_ops fsl_i2c_ops = {
638 .xfer = fsl_i2c_xfer,
639 .probe_chip = fsl_i2c_probe_chip,
640 .set_bus_speed = fsl_i2c_set_bus_speed,
641 };
642
643 static const struct udevice_id fsl_i2c_ids[] = {
644 { .compatible = "fsl-i2c", },
645 { /* sentinel */ }
646 };
647
648 U_BOOT_DRIVER(i2c_fsl) = {
649 .name = "i2c_fsl",
650 .id = UCLASS_I2C,
651 .of_match = fsl_i2c_ids,
652 .probe = fsl_i2c_probe,
653 .of_to_plat = fsl_i2c_of_to_plat,
654 .priv_auto = sizeof(struct fsl_i2c_dev),
655 .ops = &fsl_i2c_ops,
656 };
657
658 #endif /* CONFIG_DM_I2C */
659