1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 */
6
7 #include <common.h>
8 #include <errno.h>
9 #include <dm.h>
10 #include <fdtdec.h>
11 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
12 #include <log.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/pinmux.h>
16 #else
17 #include <asm/arch/s3c24x0_cpu.h>
18 #endif
19 #include <asm/global_data.h>
20 #include <asm/io.h>
21 #include <i2c.h>
22 #include "s3c24x0_i2c.h"
23
24 #ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
25 #define SYS_I2C_S3C24X0_SLAVE_ADDR 0
26 #else
27 #define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
28 #endif
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 /*
33 * Wait til the byte transfer is completed.
34 *
35 * @param i2c- pointer to the appropriate i2c register bank.
36 * @return I2C_OK, if transmission was ACKED
37 * I2C_NACK, if transmission was NACKED
38 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
39 */
40
WaitForXfer(struct s3c24x0_i2c * i2c)41 static int WaitForXfer(struct s3c24x0_i2c *i2c)
42 {
43 ulong start_time = get_timer(0);
44
45 do {
46 if (readl(&i2c->iiccon) & I2CCON_IRPND)
47 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
48 I2C_NACK : I2C_OK;
49 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
50
51 return I2C_NOK_TOUT;
52 }
53
read_write_byte(struct s3c24x0_i2c * i2c)54 static void read_write_byte(struct s3c24x0_i2c *i2c)
55 {
56 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
57 }
58
i2c_ch_init(struct s3c24x0_i2c * i2c,int speed,int slaveadd)59 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
60 {
61 ulong freq, pres = 16, div;
62 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
63 freq = get_i2c_clk();
64 #else
65 freq = get_PCLK();
66 #endif
67 /* calculate prescaler and divisor values */
68 if ((freq / pres / (16 + 1)) > speed)
69 /* set prescaler to 512 */
70 pres = 512;
71
72 div = 0;
73 while ((freq / pres / (div + 1)) > speed)
74 div++;
75
76 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
77 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
78
79 /* init to SLAVE REVEIVE and set slaveaddr */
80 writel(0, &i2c->iicstat);
81 writel(slaveadd, &i2c->iicadd);
82 /* program Master Transmit (and implicit STOP) */
83 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
84 }
85
s3c24x0_i2c_set_bus_speed(struct udevice * dev,unsigned int speed)86 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
87 {
88 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
89
90 i2c_bus->clock_frequency = speed;
91
92 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
93 SYS_I2C_S3C24X0_SLAVE_ADDR);
94
95 return 0;
96 }
97
98 /*
99 * cmd_type is 0 for write, 1 for read.
100 *
101 * addr_len can take any value from 0-255, it is only limited
102 * by the char, we could make it larger if needed. If it is
103 * 0 we skip the address write cycle.
104 */
i2c_transfer(struct s3c24x0_i2c * i2c,unsigned char cmd_type,unsigned char chip,unsigned char addr[],unsigned char addr_len,unsigned char data[],unsigned short data_len)105 static int i2c_transfer(struct s3c24x0_i2c *i2c,
106 unsigned char cmd_type,
107 unsigned char chip,
108 unsigned char addr[],
109 unsigned char addr_len,
110 unsigned char data[],
111 unsigned short data_len)
112 {
113 int i = 0, result;
114 ulong start_time = get_timer(0);
115
116 if (data == 0 || data_len == 0) {
117 /*Don't support data transfer of no length or to address 0 */
118 debug("i2c_transfer: bad call\n");
119 return I2C_NOK;
120 }
121
122 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
123 if (get_timer(start_time) > I2C_TIMEOUT_MS)
124 return I2C_NOK_TOUT;
125 }
126
127 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
128
129 /* Get the slave chip address going */
130 writel(chip, &i2c->iicds);
131 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
132 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
133 &i2c->iicstat);
134 else
135 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
136 &i2c->iicstat);
137
138 /* Wait for chip address to transmit. */
139 result = WaitForXfer(i2c);
140 if (result != I2C_OK)
141 goto bailout;
142
143 /* If register address needs to be transmitted - do it now. */
144 if (addr && addr_len) {
145 while ((i < addr_len) && (result == I2C_OK)) {
146 writel(addr[i++], &i2c->iicds);
147 read_write_byte(i2c);
148 result = WaitForXfer(i2c);
149 }
150 i = 0;
151 if (result != I2C_OK)
152 goto bailout;
153 }
154
155 switch (cmd_type) {
156 case I2C_WRITE:
157 while ((i < data_len) && (result == I2C_OK)) {
158 writel(data[i++], &i2c->iicds);
159 read_write_byte(i2c);
160 result = WaitForXfer(i2c);
161 }
162 break;
163
164 case I2C_READ:
165 if (addr && addr_len) {
166 /*
167 * Register address has been sent, now send slave chip
168 * address again to start the actual read transaction.
169 */
170 writel(chip, &i2c->iicds);
171
172 /* Generate a re-START. */
173 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
174 &i2c->iicstat);
175 read_write_byte(i2c);
176 result = WaitForXfer(i2c);
177
178 if (result != I2C_OK)
179 goto bailout;
180 }
181
182 while ((i < data_len) && (result == I2C_OK)) {
183 /* disable ACK for final READ */
184 if (i == data_len - 1)
185 writel(readl(&i2c->iiccon)
186 & ~I2CCON_ACKGEN,
187 &i2c->iiccon);
188 read_write_byte(i2c);
189 result = WaitForXfer(i2c);
190 data[i++] = readl(&i2c->iicds);
191 }
192 if (result == I2C_NACK)
193 result = I2C_OK; /* Normal terminated read. */
194 break;
195
196 default:
197 debug("i2c_transfer: bad call\n");
198 result = I2C_NOK;
199 break;
200 }
201
202 bailout:
203 /* Send STOP. */
204 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
205 read_write_byte(i2c);
206
207 return result;
208 }
209
s3c24x0_i2c_probe(struct udevice * dev,uint chip,uint chip_flags)210 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
211 {
212 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
213 uchar buf[1];
214 int ret;
215
216 buf[0] = 0;
217
218 /*
219 * What is needed is to send the chip address and verify that the
220 * address was <ACK>ed (i.e. there was a chip at that address which
221 * drove the data line low).
222 */
223 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
224
225 return ret != I2C_OK;
226 }
227
s3c24x0_do_msg(struct s3c24x0_i2c_bus * i2c_bus,struct i2c_msg * msg,int seq)228 static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
229 int seq)
230 {
231 struct s3c24x0_i2c *i2c = i2c_bus->regs;
232 bool is_read = msg->flags & I2C_M_RD;
233 uint status;
234 uint addr;
235 int ret, i;
236
237 if (!seq)
238 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
239
240 /* Get the slave chip address going */
241 addr = msg->addr << 1;
242 writel(addr, &i2c->iicds);
243 status = I2C_TXRX_ENA | I2C_START_STOP;
244 if (is_read)
245 status |= I2C_MODE_MR;
246 else
247 status |= I2C_MODE_MT;
248 writel(status, &i2c->iicstat);
249 if (seq)
250 read_write_byte(i2c);
251
252 /* Wait for chip address to transmit */
253 ret = WaitForXfer(i2c);
254 if (ret)
255 goto err;
256
257 if (is_read) {
258 for (i = 0; !ret && i < msg->len; i++) {
259 /* disable ACK for final READ */
260 if (i == msg->len - 1)
261 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
262 read_write_byte(i2c);
263 ret = WaitForXfer(i2c);
264 msg->buf[i] = readl(&i2c->iicds);
265 }
266 if (ret == I2C_NACK)
267 ret = I2C_OK; /* Normal terminated read */
268 } else {
269 for (i = 0; !ret && i < msg->len; i++) {
270 writel(msg->buf[i], &i2c->iicds);
271 read_write_byte(i2c);
272 ret = WaitForXfer(i2c);
273 }
274 }
275
276 err:
277 return ret;
278 }
279
s3c24x0_i2c_xfer(struct udevice * dev,struct i2c_msg * msg,int nmsgs)280 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
281 int nmsgs)
282 {
283 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
284 struct s3c24x0_i2c *i2c = i2c_bus->regs;
285 ulong start_time;
286 int ret, i;
287
288 start_time = get_timer(0);
289 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
290 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
291 debug("Timeout\n");
292 return -ETIMEDOUT;
293 }
294 }
295
296 for (ret = 0, i = 0; !ret && i < nmsgs; i++)
297 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
298
299 /* Send STOP */
300 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
301 read_write_byte(i2c);
302
303 return ret ? -EREMOTEIO : 0;
304 }
305
s3c_i2c_of_to_plat(struct udevice * dev)306 static int s3c_i2c_of_to_plat(struct udevice *dev)
307 {
308 const void *blob = gd->fdt_blob;
309 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
310 int node;
311
312 node = dev_of_offset(dev);
313
314 i2c_bus->regs = dev_read_addr_ptr(dev);
315
316 i2c_bus->id = pinmux_decode_periph_id(blob, node);
317
318 i2c_bus->clock_frequency =
319 dev_read_u32_default(dev, "clock-frequency",
320 I2C_SPEED_STANDARD_RATE);
321 i2c_bus->node = node;
322 i2c_bus->bus_num = dev_seq(dev);
323
324 exynos_pinmux_config(i2c_bus->id, 0);
325
326 i2c_bus->active = true;
327
328 return 0;
329 }
330
331 static const struct dm_i2c_ops s3c_i2c_ops = {
332 .xfer = s3c24x0_i2c_xfer,
333 .probe_chip = s3c24x0_i2c_probe,
334 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
335 };
336
337 static const struct udevice_id s3c_i2c_ids[] = {
338 { .compatible = "samsung,s3c2440-i2c" },
339 { }
340 };
341
342 U_BOOT_DRIVER(i2c_s3c) = {
343 .name = "i2c_s3c",
344 .id = UCLASS_I2C,
345 .of_match = s3c_i2c_ids,
346 .of_to_plat = s3c_i2c_of_to_plat,
347 .priv_auto = sizeof(struct s3c24x0_i2c_bus),
348 .ops = &s3c_i2c_ops,
349 };
350