1# SPDX-License-Identifier: GPL-2.0-only
2menu "IRQ chip support"
3
4config IRQCHIP
5	def_bool y
6	depends on OF_IRQ
7
8config ARM_GIC
9	bool
10	select IRQ_DOMAIN_HIERARCHY
11	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
12
13config ARM_GIC_PM
14	bool
15	depends on PM
16	select ARM_GIC
17
18config ARM_GIC_MAX_NR
19	int
20	depends on ARM_GIC
21	default 2 if ARCH_REALVIEW
22	default 1
23
24config ARM_GIC_V2M
25	bool
26	depends on PCI
27	select ARM_GIC
28	select PCI_MSI
29
30config GIC_NON_BANKED
31	bool
32
33config ARM_GIC_V3
34	bool
35	select IRQ_DOMAIN_HIERARCHY
36	select PARTITION_PERCPU
37	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
38
39config ARM_GIC_V3_ITS
40	bool
41	select GENERIC_MSI_IRQ_DOMAIN
42	default ARM_GIC_V3
43
44config ARM_GIC_V3_ITS_PCI
45	bool
46	depends on ARM_GIC_V3_ITS
47	depends on PCI
48	depends on PCI_MSI
49	default ARM_GIC_V3_ITS
50
51config ARM_GIC_V3_ITS_FSL_MC
52	bool
53	depends on ARM_GIC_V3_ITS
54	depends on FSL_MC_BUS
55	default ARM_GIC_V3_ITS
56
57config ARM_NVIC
58	bool
59	select IRQ_DOMAIN_HIERARCHY
60	select GENERIC_IRQ_CHIP
61
62config ARM_VIC
63	bool
64	select IRQ_DOMAIN
65
66config ARM_VIC_NR
67	int
68	default 4 if ARCH_S5PV210
69	default 2
70	depends on ARM_VIC
71	help
72	  The maximum number of VICs available in the system, for
73	  power management.
74
75config ARMADA_370_XP_IRQ
76	bool
77	select GENERIC_IRQ_CHIP
78	select PCI_MSI if PCI
79	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
80
81config ALPINE_MSI
82	bool
83	depends on PCI
84	select PCI_MSI
85	select GENERIC_IRQ_CHIP
86
87config AL_FIC
88	bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89	depends on OF || COMPILE_TEST
90	select GENERIC_IRQ_CHIP
91	select IRQ_DOMAIN
92	help
93	  Support Amazon's Annapurna Labs Fabric Interrupt Controller.
94
95config ATMEL_AIC_IRQ
96	bool
97	select GENERIC_IRQ_CHIP
98	select IRQ_DOMAIN
99	select SPARSE_IRQ
100
101config ATMEL_AIC5_IRQ
102	bool
103	select GENERIC_IRQ_CHIP
104	select IRQ_DOMAIN
105	select SPARSE_IRQ
106
107config I8259
108	bool
109	select IRQ_DOMAIN
110
111config BCM6345_L1_IRQ
112	bool
113	select GENERIC_IRQ_CHIP
114	select IRQ_DOMAIN
115	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
116
117config BCM7038_L1_IRQ
118	tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
119	depends on ARCH_BRCMSTB || BMIPS_GENERIC
120	default ARCH_BRCMSTB || BMIPS_GENERIC
121	select GENERIC_IRQ_CHIP
122	select IRQ_DOMAIN
123	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
124
125config BCM7120_L2_IRQ
126	tristate "Broadcom STB 7120-style L2 interrupt controller driver"
127	depends on ARCH_BRCMSTB || BMIPS_GENERIC
128	default ARCH_BRCMSTB || BMIPS_GENERIC
129	select GENERIC_IRQ_CHIP
130	select IRQ_DOMAIN
131
132config BRCMSTB_L2_IRQ
133	tristate "Broadcom STB generic L2 interrupt controller driver"
134	depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
135	default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
136	select GENERIC_IRQ_CHIP
137	select IRQ_DOMAIN
138
139config DAVINCI_AINTC
140	bool
141	select GENERIC_IRQ_CHIP
142	select IRQ_DOMAIN
143
144config DAVINCI_CP_INTC
145	bool
146	select GENERIC_IRQ_CHIP
147	select IRQ_DOMAIN
148
149config DW_APB_ICTL
150	bool
151	select GENERIC_IRQ_CHIP
152	select IRQ_DOMAIN_HIERARCHY
153
154config FARADAY_FTINTC010
155	bool
156	select IRQ_DOMAIN
157	select SPARSE_IRQ
158
159config HISILICON_IRQ_MBIGEN
160	bool
161	select ARM_GIC_V3
162	select ARM_GIC_V3_ITS
163
164config IMGPDC_IRQ
165	bool
166	select GENERIC_IRQ_CHIP
167	select IRQ_DOMAIN
168
169config IXP4XX_IRQ
170	bool
171	select IRQ_DOMAIN
172	select SPARSE_IRQ
173
174config MADERA_IRQ
175	tristate
176
177config IRQ_MIPS_CPU
178	bool
179	select GENERIC_IRQ_CHIP
180	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
181	select IRQ_DOMAIN
182	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
183
184config CLPS711X_IRQCHIP
185	bool
186	depends on ARCH_CLPS711X
187	select IRQ_DOMAIN
188	select SPARSE_IRQ
189	default y
190
191config OMPIC
192	bool
193
194config OR1K_PIC
195	bool
196	select IRQ_DOMAIN
197
198config OMAP_IRQCHIP
199	bool
200	select GENERIC_IRQ_CHIP
201	select IRQ_DOMAIN
202
203config ORION_IRQCHIP
204	bool
205	select IRQ_DOMAIN
206
207config PIC32_EVIC
208	bool
209	select GENERIC_IRQ_CHIP
210	select IRQ_DOMAIN
211
212config JCORE_AIC
213	bool "J-Core integrated AIC" if COMPILE_TEST
214	depends on OF
215	select IRQ_DOMAIN
216	help
217	  Support for the J-Core integrated AIC.
218
219config RDA_INTC
220	bool
221	select IRQ_DOMAIN
222
223config RENESAS_INTC_IRQPIN
224	bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
225	select IRQ_DOMAIN
226	help
227	  Enable support for the Renesas Interrupt Controller for external
228	  interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
229
230config RENESAS_IRQC
231	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
232	select GENERIC_IRQ_CHIP
233	select IRQ_DOMAIN
234	help
235	  Enable support for the Renesas Interrupt Controller for external
236	  devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
237
238config RENESAS_RZA1_IRQC
239	bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
240	select IRQ_DOMAIN_HIERARCHY
241	help
242	  Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
243	  to 8 external interrupts with configurable sense select.
244
245config SL28CPLD_INTC
246	bool "Kontron sl28cpld IRQ controller"
247	depends on MFD_SL28CPLD=y || COMPILE_TEST
248	select REGMAP_IRQ
249	help
250	  Interrupt controller driver for the board management controller
251	  found on the Kontron sl28 CPLD.
252
253config ST_IRQCHIP
254	bool
255	select REGMAP
256	select MFD_SYSCON
257	help
258	  Enables SysCfg Controlled IRQs on STi based platforms.
259
260config TB10X_IRQC
261	bool
262	select IRQ_DOMAIN
263	select GENERIC_IRQ_CHIP
264
265config TS4800_IRQ
266	tristate "TS-4800 IRQ controller"
267	select IRQ_DOMAIN
268	depends on HAS_IOMEM
269	depends on SOC_IMX51 || COMPILE_TEST
270	help
271	  Support for the TS-4800 FPGA IRQ controller
272
273config VERSATILE_FPGA_IRQ
274	bool
275	select IRQ_DOMAIN
276
277config VERSATILE_FPGA_IRQ_NR
278       int
279       default 4
280       depends on VERSATILE_FPGA_IRQ
281
282config XTENSA_MX
283	bool
284	select IRQ_DOMAIN
285	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
286
287config XILINX_INTC
288	bool "Xilinx Interrupt Controller IP"
289	depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP
290	select IRQ_DOMAIN
291	help
292	  Support for the Xilinx Interrupt Controller IP core.
293	  This is used as a primary controller with MicroBlaze and can also
294	  be used as a secondary chained controller on other platforms.
295
296config IRQ_CROSSBAR
297	bool
298	help
299	  Support for a CROSSBAR ip that precedes the main interrupt controller.
300	  The primary irqchip invokes the crossbar's callback which inturn allocates
301	  a free irq and configures the IP. Thus the peripheral interrupts are
302	  routed to one of the free irqchip interrupt lines.
303
304config KEYSTONE_IRQ
305	tristate "Keystone 2 IRQ controller IP"
306	depends on ARCH_KEYSTONE
307	help
308		Support for Texas Instruments Keystone 2 IRQ controller IP which
309		is part of the Keystone 2 IPC mechanism
310
311config MIPS_GIC
312	bool
313	select GENERIC_IRQ_IPI
314	select MIPS_CM
315
316config INGENIC_IRQ
317	bool
318	depends on MACH_INGENIC
319	default y
320
321config INGENIC_TCU_IRQ
322	bool "Ingenic JZ47xx TCU interrupt controller"
323	default MACH_INGENIC
324	depends on MIPS || COMPILE_TEST
325	select MFD_SYSCON
326	select GENERIC_IRQ_CHIP
327	help
328	  Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
329	  JZ47xx SoCs.
330
331	  If unsure, say N.
332
333config RENESAS_H8300H_INTC
334        bool
335	select IRQ_DOMAIN
336
337config RENESAS_H8S_INTC
338	bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
339	select IRQ_DOMAIN
340	help
341	  Enable support for the Renesas H8/300 Interrupt Controller, as found
342	  on Renesas H8S SoCs.
343
344config IMX_GPCV2
345	bool
346	select IRQ_DOMAIN
347	help
348	  Enables the wakeup IRQs for IMX platforms with GPCv2 block
349
350config IRQ_MXS
351	def_bool y if MACH_ASM9260 || ARCH_MXS
352	select IRQ_DOMAIN
353	select STMP_DEVICE
354
355config MSCC_OCELOT_IRQ
356	bool
357	select IRQ_DOMAIN
358	select GENERIC_IRQ_CHIP
359
360config MVEBU_GICP
361	bool
362
363config MVEBU_ICU
364	bool
365
366config MVEBU_ODMI
367	bool
368	select GENERIC_MSI_IRQ_DOMAIN
369
370config MVEBU_PIC
371	bool
372
373config MVEBU_SEI
374        bool
375
376config LS_EXTIRQ
377	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
378	select MFD_SYSCON
379
380config LS_SCFG_MSI
381	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
382	depends on PCI && PCI_MSI
383
384config PARTITION_PERCPU
385	bool
386
387config STM32_EXTI
388	bool
389	select IRQ_DOMAIN
390	select GENERIC_IRQ_CHIP
391
392config QCOM_IRQ_COMBINER
393	bool "QCOM IRQ combiner support"
394	depends on ARCH_QCOM && ACPI
395	select IRQ_DOMAIN_HIERARCHY
396	help
397	  Say yes here to add support for the IRQ combiner devices embedded
398	  in Qualcomm Technologies chips.
399
400config IRQ_UNIPHIER_AIDET
401	bool "UniPhier AIDET support" if COMPILE_TEST
402	depends on ARCH_UNIPHIER || COMPILE_TEST
403	default ARCH_UNIPHIER
404	select IRQ_DOMAIN_HIERARCHY
405	help
406	  Support for the UniPhier AIDET (ARM Interrupt Detector).
407
408config MESON_IRQ_GPIO
409       tristate "Meson GPIO Interrupt Multiplexer"
410       depends on ARCH_MESON || COMPILE_TEST
411       default ARCH_MESON
412       select IRQ_DOMAIN_HIERARCHY
413       help
414         Support Meson SoC Family GPIO Interrupt Multiplexer
415
416config GOLDFISH_PIC
417       bool "Goldfish programmable interrupt controller"
418       depends on MIPS && (GOLDFISH || COMPILE_TEST)
419       select GENERIC_IRQ_CHIP
420       select IRQ_DOMAIN
421       help
422         Say yes here to enable Goldfish interrupt controller driver used
423         for Goldfish based virtual platforms.
424
425config QCOM_PDC
426	tristate "QCOM PDC"
427	depends on ARCH_QCOM
428	select IRQ_DOMAIN_HIERARCHY
429	help
430	  Power Domain Controller driver to manage and configure wakeup
431	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
432
433config CSKY_MPINTC
434	bool
435	depends on CSKY
436	help
437	  Say yes here to enable C-SKY SMP interrupt controller driver used
438	  for C-SKY SMP system.
439	  In fact it's not mmio map in hardware and it uses ld/st to visit the
440	  controller's register inside CPU.
441
442config CSKY_APB_INTC
443	bool "C-SKY APB Interrupt Controller"
444	depends on CSKY
445	help
446	  Say yes here to enable C-SKY APB interrupt controller driver used
447	  by C-SKY single core SOC system. It uses mmio map apb-bus to visit
448	  the controller's register.
449
450config IMX_IRQSTEER
451	bool "i.MX IRQSTEER support"
452	depends on ARCH_MXC || COMPILE_TEST
453	default ARCH_MXC
454	select IRQ_DOMAIN
455	help
456	  Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
457
458config IMX_INTMUX
459	bool "i.MX INTMUX support" if COMPILE_TEST
460	default y if ARCH_MXC
461	select IRQ_DOMAIN
462	help
463	  Support for the i.MX INTMUX interrupt multiplexer.
464
465config LS1X_IRQ
466	bool "Loongson-1 Interrupt Controller"
467	depends on MACH_LOONGSON32
468	default y
469	select IRQ_DOMAIN
470	select GENERIC_IRQ_CHIP
471	help
472	  Support for the Loongson-1 platform Interrupt Controller.
473
474config TI_SCI_INTR_IRQCHIP
475	bool
476	depends on TI_SCI_PROTOCOL
477	select IRQ_DOMAIN_HIERARCHY
478	help
479	  This enables the irqchip driver support for K3 Interrupt router
480	  over TI System Control Interface available on some new TI's SoCs.
481	  If you wish to use interrupt router irq resources managed by the
482	  TI System Controller, say Y here. Otherwise, say N.
483
484config TI_SCI_INTA_IRQCHIP
485	bool
486	depends on TI_SCI_PROTOCOL
487	select IRQ_DOMAIN_HIERARCHY
488	select TI_SCI_INTA_MSI_DOMAIN
489	help
490	  This enables the irqchip driver support for K3 Interrupt aggregator
491	  over TI System Control Interface available on some new TI's SoCs.
492	  If you wish to use interrupt aggregator irq resources managed by the
493	  TI System Controller, say Y here. Otherwise, say N.
494
495config TI_PRUSS_INTC
496	tristate
497	depends on TI_PRUSS
498	default TI_PRUSS
499	select IRQ_DOMAIN
500	help
501	  This enables support for the PRU-ICSS Local Interrupt Controller
502	  present within a PRU-ICSS subsystem present on various TI SoCs.
503	  The PRUSS INTC enables various interrupts to be routed to multiple
504	  different processors within the SoC.
505
506config RISCV_INTC
507	bool "RISC-V Local Interrupt Controller"
508	depends on RISCV
509	default y
510	help
511	   This enables support for the per-HART local interrupt controller
512	   found in standard RISC-V systems.  The per-HART local interrupt
513	   controller handles timer interrupts, software interrupts, and
514	   hardware interrupts. Without a per-HART local interrupt controller,
515	   a RISC-V system will be unable to handle any interrupts.
516
517	   If you don't know what to do here, say Y.
518
519config SIFIVE_PLIC
520	bool "SiFive Platform-Level Interrupt Controller"
521	depends on RISCV
522	select IRQ_DOMAIN_HIERARCHY
523	help
524	   This enables support for the PLIC chip found in SiFive (and
525	   potentially other) RISC-V systems.  The PLIC controls devices
526	   interrupts and connects them to each core's local interrupt
527	   controller.  Aside from timer and software interrupts, all other
528	   interrupt sources are subordinate to the PLIC.
529
530	   If you don't know what to do here, say Y.
531
532config EXYNOS_IRQ_COMBINER
533	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
534	depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
535	help
536	  Say yes here to add support for the IRQ combiner devices embedded
537	  in Samsung Exynos chips.
538
539config LOONGSON_LIOINTC
540	bool "Loongson Local I/O Interrupt Controller"
541	depends on MACH_LOONGSON64
542	default y
543	select IRQ_DOMAIN
544	select GENERIC_IRQ_CHIP
545	help
546	  Support for the Loongson Local I/O Interrupt Controller.
547
548config LOONGSON_HTPIC
549	bool "Loongson3 HyperTransport PIC Controller"
550	depends on MACH_LOONGSON64
551	default y
552	select IRQ_DOMAIN
553	select GENERIC_IRQ_CHIP
554	help
555	  Support for the Loongson-3 HyperTransport PIC Controller.
556
557config LOONGSON_HTVEC
558	bool "Loongson3 HyperTransport Interrupt Vector Controller"
559	depends on MACH_LOONGSON64
560	default MACH_LOONGSON64
561	select IRQ_DOMAIN_HIERARCHY
562	help
563	  Support for the Loongson3 HyperTransport Interrupt Vector Controller.
564
565config LOONGSON_PCH_PIC
566	bool "Loongson PCH PIC Controller"
567	depends on MACH_LOONGSON64 || COMPILE_TEST
568	default MACH_LOONGSON64
569	select IRQ_DOMAIN_HIERARCHY
570	select IRQ_FASTEOI_HIERARCHY_HANDLERS
571	help
572	  Support for the Loongson PCH PIC Controller.
573
574config LOONGSON_PCH_MSI
575	bool "Loongson PCH MSI Controller"
576	depends on MACH_LOONGSON64 || COMPILE_TEST
577	depends on PCI
578	default MACH_LOONGSON64
579	select IRQ_DOMAIN_HIERARCHY
580	select PCI_MSI
581	help
582	  Support for the Loongson PCH MSI Controller.
583
584config MST_IRQ
585	bool "MStar Interrupt Controller"
586	depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
587	default ARCH_MEDIATEK
588	select IRQ_DOMAIN
589	select IRQ_DOMAIN_HIERARCHY
590	help
591	  Support MStar Interrupt Controller.
592
593config WPCM450_AIC
594	bool "Nuvoton WPCM450 Advanced Interrupt Controller"
595	depends on ARCH_WPCM450
596	help
597	  Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
598
599config IRQ_IDT3243X
600	bool
601	select GENERIC_IRQ_CHIP
602	select IRQ_DOMAIN
603
604config APPLE_AIC
605	bool "Apple Interrupt Controller (AIC)"
606	depends on ARM64
607	depends on ARCH_APPLE || COMPILE_TEST
608	help
609	  Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
610	  such as the M1.
611
612config MCHP_EIC
613	bool "Microchip External Interrupt Controller"
614	depends on ARCH_AT91 || COMPILE_TEST
615	select IRQ_DOMAIN
616	select IRQ_DOMAIN_HIERARCHY
617	help
618	  Support for Microchip External Interrupt Controller.
619
620endmenu
621