1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
5 */
6
7 #define LOG_CATEGORY UCLASS_RESET
8
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <log.h>
13 #include <malloc.h>
14 #include <reset-uclass.h>
15 #include <stm32_rcc.h>
16 #include <asm/io.h>
17 #include <dm/device_compat.h>
18 #include <linux/bitops.h>
19
20 /* offset of register without set/clear management */
21 #define RCC_MP_GCR_OFFSET 0x10C
22
23 /* reset clear offset for STM32MP RCC */
24 #define RCC_CL 0x4
25
26 struct stm32_reset_priv {
27 fdt_addr_t base;
28 };
29
stm32_reset_request(struct reset_ctl * reset_ctl)30 static int stm32_reset_request(struct reset_ctl *reset_ctl)
31 {
32 return 0;
33 }
34
stm32_reset_free(struct reset_ctl * reset_ctl)35 static int stm32_reset_free(struct reset_ctl *reset_ctl)
36 {
37 return 0;
38 }
39
stm32_reset_assert(struct reset_ctl * reset_ctl)40 static int stm32_reset_assert(struct reset_ctl *reset_ctl)
41 {
42 struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
43 int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
44 int offset = reset_ctl->id % BITS_PER_LONG;
45
46 dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
47 reset_ctl->id, bank, offset);
48
49 if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
50 if (bank != RCC_MP_GCR_OFFSET)
51 /* reset assert is done in rcc set register */
52 writel(BIT(offset), priv->base + bank);
53 else
54 clrbits_le32(priv->base + bank, BIT(offset));
55 else
56 setbits_le32(priv->base + bank, BIT(offset));
57
58 return 0;
59 }
60
stm32_reset_deassert(struct reset_ctl * reset_ctl)61 static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
62 {
63 struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
64 int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
65 int offset = reset_ctl->id % BITS_PER_LONG;
66
67 dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
68 reset_ctl->id, bank, offset);
69
70 if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
71 if (bank != RCC_MP_GCR_OFFSET)
72 /* reset deassert is done in rcc clr register */
73 writel(BIT(offset), priv->base + bank + RCC_CL);
74 else
75 setbits_le32(priv->base + bank, BIT(offset));
76 else
77 clrbits_le32(priv->base + bank, BIT(offset));
78
79 return 0;
80 }
81
82 static const struct reset_ops stm32_reset_ops = {
83 .request = stm32_reset_request,
84 .rfree = stm32_reset_free,
85 .rst_assert = stm32_reset_assert,
86 .rst_deassert = stm32_reset_deassert,
87 };
88
stm32_reset_probe(struct udevice * dev)89 static int stm32_reset_probe(struct udevice *dev)
90 {
91 struct stm32_reset_priv *priv = dev_get_priv(dev);
92
93 priv->base = dev_read_addr(dev);
94 if (priv->base == FDT_ADDR_T_NONE) {
95 /* for MFD, get address of parent */
96 priv->base = dev_read_addr(dev->parent);
97 if (priv->base == FDT_ADDR_T_NONE)
98 return -EINVAL;
99 }
100
101 return 0;
102 }
103
104 U_BOOT_DRIVER(stm32_rcc_reset) = {
105 .name = "stm32_rcc_reset",
106 .id = UCLASS_RESET,
107 .probe = stm32_reset_probe,
108 .priv_auto = sizeof(struct stm32_reset_priv),
109 .ops = &stm32_reset_ops,
110 };
111