1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
4 */
5
6 #define LOG_CATEGORY UCLASS_RTC
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <malloc.h>
12 #include <rtc.h>
13 #include <asm/io.h>
14 #include <dm/device_compat.h>
15 #include <linux/bitops.h>
16 #include <linux/iopoll.h>
17
18 #define STM32_RTC_TR 0x00
19 #define STM32_RTC_DR 0x04
20 #define STM32_RTC_ISR 0x0C
21 #define STM32_RTC_PRER 0x10
22 #define STM32_RTC_CR 0x18
23 #define STM32_RTC_WPR 0x24
24
25 /* STM32_RTC_TR bit fields */
26 #define STM32_RTC_SEC_SHIFT 0
27 #define STM32_RTC_SEC GENMASK(6, 0)
28 #define STM32_RTC_MIN_SHIFT 8
29 #define STM32_RTC_MIN GENMASK(14, 8)
30 #define STM32_RTC_HOUR_SHIFT 16
31 #define STM32_RTC_HOUR GENMASK(21, 16)
32
33 /* STM32_RTC_DR bit fields */
34 #define STM32_RTC_DATE_SHIFT 0
35 #define STM32_RTC_DATE GENMASK(5, 0)
36 #define STM32_RTC_MONTH_SHIFT 8
37 #define STM32_RTC_MONTH GENMASK(12, 8)
38 #define STM32_RTC_WDAY_SHIFT 13
39 #define STM32_RTC_WDAY GENMASK(15, 13)
40 #define STM32_RTC_YEAR_SHIFT 16
41 #define STM32_RTC_YEAR GENMASK(23, 16)
42
43 /* STM32_RTC_CR bit fields */
44 #define STM32_RTC_CR_FMT BIT(6)
45
46 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
47 #define STM32_RTC_ISR_INITS BIT(4)
48 #define STM32_RTC_ISR_RSF BIT(5)
49 #define STM32_RTC_ISR_INITF BIT(6)
50 #define STM32_RTC_ISR_INIT BIT(7)
51
52 /* STM32_RTC_PRER bit fields */
53 #define STM32_RTC_PRER_PRED_S_SHIFT 0
54 #define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
55 #define STM32_RTC_PRER_PRED_A_SHIFT 16
56 #define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
57
58 /* STM32_RTC_WPR key constants */
59 #define RTC_WPR_1ST_KEY 0xCA
60 #define RTC_WPR_2ND_KEY 0x53
61 #define RTC_WPR_WRONG_KEY 0xFF
62
63 struct stm32_rtc_priv {
64 fdt_addr_t base;
65 };
66
stm32_rtc_get(struct udevice * dev,struct rtc_time * tm)67 static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm)
68 {
69 struct stm32_rtc_priv *priv = dev_get_priv(dev);
70 u32 tr, dr;
71
72 tr = readl(priv->base + STM32_RTC_TR);
73 dr = readl(priv->base + STM32_RTC_DR);
74
75 tm->tm_sec = bcd2bin((tr & STM32_RTC_SEC) >> STM32_RTC_SEC_SHIFT);
76 tm->tm_min = bcd2bin((tr & STM32_RTC_MIN) >> STM32_RTC_MIN_SHIFT);
77 tm->tm_hour = bcd2bin((tr & STM32_RTC_HOUR) >> STM32_RTC_HOUR_SHIFT);
78
79 tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT);
80 tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT);
81 tm->tm_year = 2000 +
82 bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT);
83 tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT);
84 tm->tm_yday = 0;
85 tm->tm_isdst = 0;
86
87 dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
88 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
89 tm->tm_hour, tm->tm_min, tm->tm_sec);
90
91 return 0;
92 }
93
stm32_rtc_unlock(struct udevice * dev)94 static void stm32_rtc_unlock(struct udevice *dev)
95 {
96 struct stm32_rtc_priv *priv = dev_get_priv(dev);
97
98 writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
99 writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
100 }
101
stm32_rtc_lock(struct udevice * dev)102 static void stm32_rtc_lock(struct udevice *dev)
103 {
104 struct stm32_rtc_priv *priv = dev_get_priv(dev);
105
106 writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
107 }
108
stm32_rtc_enter_init_mode(struct udevice * dev)109 static int stm32_rtc_enter_init_mode(struct udevice *dev)
110 {
111 struct stm32_rtc_priv *priv = dev_get_priv(dev);
112 u32 isr = readl(priv->base + STM32_RTC_ISR);
113
114 if (!(isr & STM32_RTC_ISR_INITF)) {
115 isr |= STM32_RTC_ISR_INIT;
116 writel(isr, priv->base + STM32_RTC_ISR);
117
118 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
119 isr,
120 (isr & STM32_RTC_ISR_INITF),
121 100000);
122 }
123
124 return 0;
125 }
126
stm32_rtc_wait_sync(struct udevice * dev)127 static int stm32_rtc_wait_sync(struct udevice *dev)
128 {
129 struct stm32_rtc_priv *priv = dev_get_priv(dev);
130 u32 isr = readl(priv->base + STM32_RTC_ISR);
131
132 isr &= ~STM32_RTC_ISR_RSF;
133 writel(isr, priv->base + STM32_RTC_ISR);
134
135 /*
136 * Wait for RSF to be set to ensure the calendar registers are
137 * synchronised, it takes around 2 rtc_ck clock cycles
138 */
139 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
140 isr, (isr & STM32_RTC_ISR_RSF),
141 100000);
142 }
143
stm32_rtc_exit_init_mode(struct udevice * dev)144 static void stm32_rtc_exit_init_mode(struct udevice *dev)
145 {
146 struct stm32_rtc_priv *priv = dev_get_priv(dev);
147 u32 isr = readl(priv->base + STM32_RTC_ISR);
148
149 isr &= ~STM32_RTC_ISR_INIT;
150 writel(isr, priv->base + STM32_RTC_ISR);
151 }
152
stm32_rtc_set_time(struct udevice * dev,u32 time,u32 date)153 static int stm32_rtc_set_time(struct udevice *dev, u32 time, u32 date)
154 {
155 struct stm32_rtc_priv *priv = dev_get_priv(dev);
156 int ret;
157
158 stm32_rtc_unlock(dev);
159
160 ret = stm32_rtc_enter_init_mode(dev);
161 if (ret)
162 goto lock;
163
164 writel(time, priv->base + STM32_RTC_TR);
165 writel(date, priv->base + STM32_RTC_DR);
166
167 stm32_rtc_exit_init_mode(dev);
168
169 ret = stm32_rtc_wait_sync(dev);
170
171 lock:
172 stm32_rtc_lock(dev);
173 return ret;
174 }
175
stm32_rtc_set(struct udevice * dev,const struct rtc_time * tm)176 static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm)
177 {
178 u32 t, d;
179
180 dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
181 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
182 tm->tm_hour, tm->tm_min, tm->tm_sec);
183
184 if (tm->tm_year < 2000 || tm->tm_year > 2099)
185 return -EINVAL;
186
187 /* Time in BCD format */
188 t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC;
189 t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN;
190 t |= (bin2bcd(tm->tm_hour) << STM32_RTC_HOUR_SHIFT) & STM32_RTC_HOUR;
191
192 /* Date in BCD format */
193 d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE;
194 d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH;
195 d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) &
196 STM32_RTC_YEAR;
197 d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY;
198
199 return stm32_rtc_set_time(dev, t, d);
200 }
201
stm32_rtc_reset(struct udevice * dev)202 static int stm32_rtc_reset(struct udevice *dev)
203 {
204 dev_dbg(dev, "Reset DATE\n");
205
206 return stm32_rtc_set_time(dev, 0, 0);
207 }
208
stm32_rtc_init(struct udevice * dev)209 static int stm32_rtc_init(struct udevice *dev)
210 {
211 struct stm32_rtc_priv *priv = dev_get_priv(dev);
212 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
213 unsigned int rate;
214 struct clk clk;
215 int ret;
216 u32 isr = readl(priv->base + STM32_RTC_ISR);
217
218 if (isr & STM32_RTC_ISR_INITS)
219 return 0;
220
221 ret = clk_get_by_index(dev, 1, &clk);
222 if (ret)
223 return ret;
224
225 ret = clk_enable(&clk);
226 if (ret) {
227 clk_free(&clk);
228 return ret;
229 }
230
231 rate = clk_get_rate(&clk);
232
233 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
234 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
235 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
236
237 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
238 pred_s = (rate / (pred_a + 1)) - 1;
239
240 if (((pred_s + 1) * (pred_a + 1)) == rate)
241 break;
242 }
243
244 /*
245 * Can't find a 1Hz, so give priority to RTC power consumption
246 * by choosing the higher possible value for prediv_a
247 */
248 if (pred_s > pred_s_max || pred_a > pred_a_max) {
249 pred_a = pred_a_max;
250 pred_s = (rate / (pred_a + 1)) - 1;
251 }
252
253 stm32_rtc_unlock(dev);
254
255 ret = stm32_rtc_enter_init_mode(dev);
256 if (ret) {
257 dev_err(dev,
258 "Can't enter in init mode. Prescaler config failed.\n");
259 goto unlock;
260 }
261
262 prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
263 prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
264 writel(prer, priv->base + STM32_RTC_PRER);
265
266 /* Force 24h time format */
267 cr = readl(priv->base + STM32_RTC_CR);
268 cr &= ~STM32_RTC_CR_FMT;
269 writel(cr, priv->base + STM32_RTC_CR);
270
271 stm32_rtc_exit_init_mode(dev);
272
273 ret = stm32_rtc_wait_sync(dev);
274
275 unlock:
276 stm32_rtc_lock(dev);
277
278 if (ret) {
279 clk_disable(&clk);
280 clk_free(&clk);
281 }
282
283 return ret;
284 }
285
stm32_rtc_probe(struct udevice * dev)286 static int stm32_rtc_probe(struct udevice *dev)
287 {
288 struct stm32_rtc_priv *priv = dev_get_priv(dev);
289 struct clk clk;
290 int ret;
291
292 priv->base = dev_read_addr(dev);
293 if (priv->base == FDT_ADDR_T_NONE)
294 return -EINVAL;
295
296 ret = clk_get_by_index(dev, 0, &clk);
297 if (ret)
298 return ret;
299
300 ret = clk_enable(&clk);
301 if (ret) {
302 clk_free(&clk);
303 return ret;
304 }
305
306 ret = stm32_rtc_init(dev);
307
308 if (ret) {
309 clk_disable(&clk);
310 clk_free(&clk);
311 }
312
313 return ret;
314 }
315
316 static const struct rtc_ops stm32_rtc_ops = {
317 .get = stm32_rtc_get,
318 .set = stm32_rtc_set,
319 .reset = stm32_rtc_reset,
320 };
321
322 static const struct udevice_id stm32_rtc_ids[] = {
323 { .compatible = "st,stm32mp1-rtc" },
324 { }
325 };
326
327 U_BOOT_DRIVER(rtc_stm32) = {
328 .name = "rtc-stm32",
329 .id = UCLASS_RTC,
330 .probe = stm32_rtc_probe,
331 .of_match = stm32_rtc_ids,
332 .ops = &stm32_rtc_ops,
333 .priv_auto = sizeof(struct stm32_rtc_priv),
334 };
335