1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Qualcomm UART driver
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 *
7 * UART will work in Data Mover mode.
8 * Based on Linux driver.
9 */
10
11 #include <common.h>
12 #include <clk.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <malloc.h>
16 #include <serial.h>
17 #include <watchdog.h>
18 #include <asm/global_data.h>
19 #include <asm/io.h>
20 #include <linux/compiler.h>
21 #include <dm/pinctrl.h>
22
23 /* Serial registers - this driver works in uartdm mode*/
24
25 #define UARTDM_DMRX 0x34 /* Max RX transfer length */
26 #define UARTDM_NCF_TX 0x40 /* Number of chars to TX */
27
28 #define UARTDM_RXFS 0x50 /* RX channel status register */
29 #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
30 #define UARTDM_RXFS_BUF_MASK 0x7
31 #define UARTDM_MR1 0x00
32 #define UARTDM_MR2 0x04
33 #define UARTDM_CSR 0xA0
34
35 #define UARTDM_SR 0xA4 /* Status register */
36 #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
37 #define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */
38 #define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */
39
40 #define UARTDM_CR 0xA8 /* Command register */
41 #define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */
42 #define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */
43 #define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/
44 #define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */
45 #define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
46
47 #define UARTDM_IMR 0xB0 /* Interrupt mask register */
48 #define UARTDM_ISR 0xB4 /* Interrupt status register */
49 #define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */
50
51 #define UARTDM_TF 0x100 /* UART Transmit FIFO register */
52 #define UARTDM_RF 0x140 /* UART Receive FIFO register */
53
54 #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
55 #define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
56 #define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
57 #define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
58
59 DECLARE_GLOBAL_DATA_PTR;
60
61 struct msm_serial_data {
62 phys_addr_t base;
63 unsigned chars_cnt; /* number of buffered chars */
64 uint32_t chars_buf; /* buffered chars */
65 uint32_t clk_bit_rate; /* data mover mode bit rate register value */
66 };
67
msm_serial_fetch(struct udevice * dev)68 static int msm_serial_fetch(struct udevice *dev)
69 {
70 struct msm_serial_data *priv = dev_get_priv(dev);
71 unsigned sr;
72
73 if (priv->chars_cnt)
74 return priv->chars_cnt;
75
76 /* Clear error in case of buffer overrun */
77 if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
78 writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
79
80 /* We need to fetch new character */
81 sr = readl(priv->base + UARTDM_SR);
82
83 if (sr & UARTDM_SR_RX_READY) {
84 /* There are at least 4 bytes in fifo */
85 priv->chars_buf = readl(priv->base + UARTDM_RF);
86 priv->chars_cnt = 4;
87 } else {
88 /* Check if there is anything in fifo */
89 priv->chars_cnt = readl(priv->base + UARTDM_RXFS);
90 /* Extract number of characters in UART packing buffer*/
91 priv->chars_cnt = (priv->chars_cnt >>
92 UARTDM_RXFS_BUF_SHIFT) &
93 UARTDM_RXFS_BUF_MASK;
94 if (!priv->chars_cnt)
95 return 0;
96
97 /* There is at least one charcter, move it to fifo */
98 writel(UARTDM_CR_CMD_FORCE_STALE,
99 priv->base + UARTDM_CR);
100
101 priv->chars_buf = readl(priv->base + UARTDM_RF);
102 writel(UARTDM_CR_CMD_RESET_STALE_INT,
103 priv->base + UARTDM_CR);
104 writel(0x7, priv->base + UARTDM_DMRX);
105 }
106
107 return priv->chars_cnt;
108 }
109
msm_serial_getc(struct udevice * dev)110 static int msm_serial_getc(struct udevice *dev)
111 {
112 struct msm_serial_data *priv = dev_get_priv(dev);
113 char c;
114
115 if (!msm_serial_fetch(dev))
116 return -EAGAIN;
117
118 c = priv->chars_buf & 0xFF;
119 priv->chars_buf >>= 8;
120 priv->chars_cnt--;
121
122 return c;
123 }
124
msm_serial_putc(struct udevice * dev,const char ch)125 static int msm_serial_putc(struct udevice *dev, const char ch)
126 {
127 struct msm_serial_data *priv = dev_get_priv(dev);
128
129 if (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
130 !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
131 return -EAGAIN;
132
133 writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
134
135 writel(1, priv->base + UARTDM_NCF_TX);
136 writel(ch, priv->base + UARTDM_TF);
137
138 return 0;
139 }
140
msm_serial_pending(struct udevice * dev,bool input)141 static int msm_serial_pending(struct udevice *dev, bool input)
142 {
143 if (input) {
144 if (msm_serial_fetch(dev))
145 return 1;
146 }
147
148 return 0;
149 }
150
151 static const struct dm_serial_ops msm_serial_ops = {
152 .putc = msm_serial_putc,
153 .pending = msm_serial_pending,
154 .getc = msm_serial_getc,
155 };
156
msm_uart_clk_init(struct udevice * dev)157 static int msm_uart_clk_init(struct udevice *dev)
158 {
159 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
160 "clock-frequency", 115200);
161 uint clkd[2]; /* clk_id and clk_no */
162 int clk_offset;
163 struct udevice *clk_dev;
164 struct clk clk;
165 int ret;
166
167 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
168 clkd, 2);
169 if (ret)
170 return ret;
171
172 clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
173 if (clk_offset < 0)
174 return clk_offset;
175
176 ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
177 if (ret)
178 return ret;
179
180 clk.id = clkd[1];
181 ret = clk_request(clk_dev, &clk);
182 if (ret < 0)
183 return ret;
184
185 ret = clk_set_rate(&clk, clk_rate);
186 clk_free(&clk);
187 if (ret < 0)
188 return ret;
189
190 return 0;
191 }
192
uart_dm_init(struct msm_serial_data * priv)193 static void uart_dm_init(struct msm_serial_data *priv)
194 {
195 writel(priv->clk_bit_rate, priv->base + UARTDM_CSR);
196 writel(0x0, priv->base + UARTDM_MR1);
197 writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
198 writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
199 writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
200 }
msm_serial_probe(struct udevice * dev)201 static int msm_serial_probe(struct udevice *dev)
202 {
203 int ret;
204 struct msm_serial_data *priv = dev_get_priv(dev);
205
206 /* No need to reinitialize the UART after relocation */
207 if (gd->flags & GD_FLG_RELOC)
208 return 0;
209
210 ret = msm_uart_clk_init(dev);
211 if (ret)
212 return ret;
213
214 pinctrl_select_state(dev, "uart");
215 uart_dm_init(priv);
216
217 return 0;
218 }
219
msm_serial_of_to_plat(struct udevice * dev)220 static int msm_serial_of_to_plat(struct udevice *dev)
221 {
222 struct msm_serial_data *priv = dev_get_priv(dev);
223
224 priv->base = dev_read_addr(dev);
225 if (priv->base == FDT_ADDR_T_NONE)
226 return -EINVAL;
227
228 priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
229 "bit-rate", UART_DM_CLK_RX_TX_BIT_RATE);
230
231 return 0;
232 }
233
234 static const struct udevice_id msm_serial_ids[] = {
235 { .compatible = "qcom,msm-uartdm-v1.4" },
236 { }
237 };
238
239 U_BOOT_DRIVER(serial_msm) = {
240 .name = "serial_msm",
241 .id = UCLASS_SERIAL,
242 .of_match = msm_serial_ids,
243 .of_to_plat = msm_serial_of_to_plat,
244 .priv_auto = sizeof(struct msm_serial_data),
245 .probe = msm_serial_probe,
246 .ops = &msm_serial_ops,
247 };
248