1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SH QSPI (Quad SPI) driver
4 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 */
8
9 #include <common.h>
10 #include <console.h>
11 #include <malloc.h>
12 #include <spi.h>
13 #include <wait_bit.h>
14 #include <asm/arch/rmobile.h>
15 #include <asm/io.h>
16 #include <linux/bitops.h>
17
18 /* SH QSPI register bit masks <REG>_<BIT> */
19 #define SPCR_MSTR 0x08
20 #define SPCR_SPE 0x40
21 #define SPSR_SPRFF 0x80
22 #define SPSR_SPTEF 0x20
23 #define SPPCR_IO3FV 0x04
24 #define SPPCR_IO2FV 0x02
25 #define SPPCR_IO1FV 0x01
26 #define SPBDCR_RXBC0 BIT(0)
27 #define SPCMD_SCKDEN BIT(15)
28 #define SPCMD_SLNDEN BIT(14)
29 #define SPCMD_SPNDEN BIT(13)
30 #define SPCMD_SSLKP BIT(7)
31 #define SPCMD_BRDV0 BIT(2)
32 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
33 SPCMD_SPNDEN | SPCMD_SSLKP | \
34 SPCMD_BRDV0
35 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
36 SPCMD_BRDV0
37 #define SPBFCR_TXRST BIT(7)
38 #define SPBFCR_RXRST BIT(6)
39 #define SPBFCR_TXTRG 0x30
40 #define SPBFCR_RXTRG 0x07
41
42 /* SH QSPI register set */
43 struct sh_qspi_regs {
44 u8 spcr;
45 u8 sslp;
46 u8 sppcr;
47 u8 spsr;
48 u32 spdr;
49 u8 spscr;
50 u8 spssr;
51 u8 spbr;
52 u8 spdcr;
53 u8 spckd;
54 u8 sslnd;
55 u8 spnd;
56 u8 dummy0;
57 u16 spcmd0;
58 u16 spcmd1;
59 u16 spcmd2;
60 u16 spcmd3;
61 u8 spbfcr;
62 u8 dummy1;
63 u16 spbdcr;
64 u32 spbmul0;
65 u32 spbmul1;
66 u32 spbmul2;
67 u32 spbmul3;
68 };
69
70 struct sh_qspi_slave {
71 #if !CONFIG_IS_ENABLED(DM_SPI)
72 struct spi_slave slave;
73 #endif
74 struct sh_qspi_regs *regs;
75 };
76
sh_qspi_init(struct sh_qspi_slave * ss)77 static void sh_qspi_init(struct sh_qspi_slave *ss)
78 {
79 /* QSPI initialize */
80 /* Set master mode only */
81 writeb(SPCR_MSTR, &ss->regs->spcr);
82
83 /* Set SSL signal level */
84 writeb(0x00, &ss->regs->sslp);
85
86 /* Set MOSI signal value when transfer is in idle state */
87 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
88
89 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
90 writeb(0x01, &ss->regs->spbr);
91
92 /* Disable Dummy Data Transmission */
93 writeb(0x00, &ss->regs->spdcr);
94
95 /* Set clock delay value */
96 writeb(0x00, &ss->regs->spckd);
97
98 /* Set SSL negation delay value */
99 writeb(0x00, &ss->regs->sslnd);
100
101 /* Set next-access delay value */
102 writeb(0x00, &ss->regs->spnd);
103
104 /* Set equence command */
105 writew(SPCMD_INIT2, &ss->regs->spcmd0);
106
107 /* Reset transfer and receive Buffer */
108 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
109
110 /* Clear transfer and receive Buffer control bit */
111 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
112
113 /* Set equence control method. Use equence0 only */
114 writeb(0x00, &ss->regs->spscr);
115
116 /* Enable SPI function */
117 setbits_8(&ss->regs->spcr, SPCR_SPE);
118 }
119
sh_qspi_cs_activate(struct sh_qspi_slave * ss)120 static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
121 {
122 /* Set master mode only */
123 writeb(SPCR_MSTR, &ss->regs->spcr);
124
125 /* Set command */
126 writew(SPCMD_INIT1, &ss->regs->spcmd0);
127
128 /* Reset transfer and receive Buffer */
129 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
130
131 /* Clear transfer and receive Buffer control bit */
132 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
133
134 /* Set equence control method. Use equence0 only */
135 writeb(0x00, &ss->regs->spscr);
136
137 /* Enable SPI function */
138 setbits_8(&ss->regs->spcr, SPCR_SPE);
139 }
140
sh_qspi_cs_deactivate(struct sh_qspi_slave * ss)141 static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
142 {
143 /* Disable SPI Function */
144 clrbits_8(&ss->regs->spcr, SPCR_SPE);
145 }
146
sh_qspi_xfer_common(struct sh_qspi_slave * ss,unsigned int bitlen,const void * dout,void * din,unsigned long flags)147 static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
148 const void *dout, void *din, unsigned long flags)
149 {
150 u32 nbyte, chunk;
151 int i, ret = 0;
152 u8 dtdata = 0, drdata;
153 u8 *tdata = &dtdata, *rdata = &drdata;
154 u32 *spbmul0 = &ss->regs->spbmul0;
155
156 if (dout == NULL && din == NULL) {
157 if (flags & SPI_XFER_END)
158 sh_qspi_cs_deactivate(ss);
159 return 0;
160 }
161
162 if (bitlen % 8) {
163 printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
164 return 1;
165 }
166
167 nbyte = bitlen / 8;
168
169 if (flags & SPI_XFER_BEGIN) {
170 sh_qspi_cs_activate(ss);
171
172 /* Set 1048576 byte */
173 writel(0x100000, spbmul0);
174 }
175
176 if (flags & SPI_XFER_END)
177 writel(nbyte, spbmul0);
178
179 if (dout != NULL)
180 tdata = (u8 *)dout;
181
182 if (din != NULL)
183 rdata = din;
184
185 while (nbyte > 0) {
186 /*
187 * Check if there is 32 Byte chunk and if there is, transfer
188 * it in one burst, otherwise transfer on byte-by-byte basis.
189 */
190 chunk = (nbyte >= 32) ? 32 : 1;
191
192 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
193 chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
194
195 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
196 true, 1000, true);
197 if (ret)
198 return ret;
199
200 for (i = 0; i < chunk; i++) {
201 writeb(*tdata, &ss->regs->spdr);
202 if (dout != NULL)
203 tdata++;
204 }
205
206 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
207 true, 1000, true);
208 if (ret)
209 return ret;
210
211 for (i = 0; i < chunk; i++) {
212 *rdata = readb(&ss->regs->spdr);
213 if (din != NULL)
214 rdata++;
215 }
216
217 nbyte -= chunk;
218 }
219
220 if (flags & SPI_XFER_END)
221 sh_qspi_cs_deactivate(ss);
222
223 return ret;
224 }
225
226 #if !CONFIG_IS_ENABLED(DM_SPI)
to_sh_qspi(struct spi_slave * slave)227 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
228 {
229 return container_of(slave, struct sh_qspi_slave, slave);
230 }
231
spi_cs_is_valid(unsigned int bus,unsigned int cs)232 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
233 {
234 return 1;
235 }
236
spi_cs_activate(struct spi_slave * slave)237 void spi_cs_activate(struct spi_slave *slave)
238 {
239 struct sh_qspi_slave *ss = to_sh_qspi(slave);
240
241 sh_qspi_cs_activate(ss);
242 }
243
spi_cs_deactivate(struct spi_slave * slave)244 void spi_cs_deactivate(struct spi_slave *slave)
245 {
246 struct sh_qspi_slave *ss = to_sh_qspi(slave);
247
248 sh_qspi_cs_deactivate(ss);
249 }
250
spi_setup_slave(unsigned int bus,unsigned int cs,unsigned int max_hz,unsigned int mode)251 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
252 unsigned int max_hz, unsigned int mode)
253 {
254 struct sh_qspi_slave *ss;
255
256 if (!spi_cs_is_valid(bus, cs))
257 return NULL;
258
259 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
260 if (!ss) {
261 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
262 return NULL;
263 }
264
265 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
266
267 /* Init SH QSPI */
268 sh_qspi_init(ss);
269
270 return &ss->slave;
271 }
272
spi_free_slave(struct spi_slave * slave)273 void spi_free_slave(struct spi_slave *slave)
274 {
275 struct sh_qspi_slave *spi = to_sh_qspi(slave);
276
277 free(spi);
278 }
279
spi_claim_bus(struct spi_slave * slave)280 int spi_claim_bus(struct spi_slave *slave)
281 {
282 return 0;
283 }
284
spi_release_bus(struct spi_slave * slave)285 void spi_release_bus(struct spi_slave *slave)
286 {
287 }
288
spi_xfer(struct spi_slave * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)289 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
290 const void *dout, void *din, unsigned long flags)
291 {
292 struct sh_qspi_slave *ss = to_sh_qspi(slave);
293
294 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
295 }
296
297 #else
298
299 #include <dm.h>
300
sh_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)301 static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
302 const void *dout, void *din, unsigned long flags)
303 {
304 struct udevice *bus = dev->parent;
305 struct sh_qspi_slave *ss = dev_get_plat(bus);
306
307 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
308 }
309
sh_qspi_set_speed(struct udevice * dev,uint speed)310 static int sh_qspi_set_speed(struct udevice *dev, uint speed)
311 {
312 /* This is a SPI NOR controller, do nothing. */
313 return 0;
314 }
315
sh_qspi_set_mode(struct udevice * dev,uint mode)316 static int sh_qspi_set_mode(struct udevice *dev, uint mode)
317 {
318 /* This is a SPI NOR controller, do nothing. */
319 return 0;
320 }
321
sh_qspi_probe(struct udevice * dev)322 static int sh_qspi_probe(struct udevice *dev)
323 {
324 struct sh_qspi_slave *ss = dev_get_plat(dev);
325
326 sh_qspi_init(ss);
327
328 return 0;
329 }
330
sh_qspi_of_to_plat(struct udevice * dev)331 static int sh_qspi_of_to_plat(struct udevice *dev)
332 {
333 struct sh_qspi_slave *plat = dev_get_plat(dev);
334
335 plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
336
337 return 0;
338 }
339
340 static const struct dm_spi_ops sh_qspi_ops = {
341 .xfer = sh_qspi_xfer,
342 .set_speed = sh_qspi_set_speed,
343 .set_mode = sh_qspi_set_mode,
344 };
345
346 static const struct udevice_id sh_qspi_ids[] = {
347 { .compatible = "renesas,qspi" },
348 { }
349 };
350
351 U_BOOT_DRIVER(sh_qspi) = {
352 .name = "sh_qspi",
353 .id = UCLASS_SPI,
354 .of_match = sh_qspi_ids,
355 .ops = &sh_qspi_ops,
356 .of_to_plat = sh_qspi_of_to_plat,
357 .plat_auto = sizeof(struct sh_qspi_slave),
358 .probe = sh_qspi_probe,
359 };
360 #endif
361