1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 Xilinx, Inc.
4 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
5 *
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
7 */
8
9 #include <clk.h>
10 #include <common.h>
11 #include <dm.h>
12 #include <dm/device_compat.h>
13 #include <log.h>
14 #include <malloc.h>
15 #include <spi.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <linux/bitops.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
23 #define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
24 #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
25 #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
26 #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
27 #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
28 #define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
29 #define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
30 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
31 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
32 #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
33 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
34 #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
35 #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
36 #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
37 #define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
38
39 /* zynq qspi Transmit Data Register */
40 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
41 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
42 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
43 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
44
45 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
46 #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
47
48 #define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
49 #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
50 #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
51
52 #define ZYNQ_QSPI_FIFO_DEPTH 63
53 #define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
54
55 /* zynq qspi register set */
56 struct zynq_qspi_regs {
57 u32 cr; /* 0x00 */
58 u32 isr; /* 0x04 */
59 u32 ier; /* 0x08 */
60 u32 idr; /* 0x0C */
61 u32 imr; /* 0x10 */
62 u32 enr; /* 0x14 */
63 u32 dr; /* 0x18 */
64 u32 txd0r; /* 0x1C */
65 u32 drxr; /* 0x20 */
66 u32 sicr; /* 0x24 */
67 u32 txftr; /* 0x28 */
68 u32 rxftr; /* 0x2C */
69 u32 gpior; /* 0x30 */
70 u32 reserved0[19];
71 u32 txd1r; /* 0x80 */
72 u32 txd2r; /* 0x84 */
73 u32 txd3r; /* 0x88 */
74 u32 reserved1[5];
75 u32 lqspicfg; /* 0xA0 */
76 u32 lqspists; /* 0xA4 */
77 };
78
79 /* zynq qspi platform data */
80 struct zynq_qspi_plat {
81 struct zynq_qspi_regs *regs;
82 u32 frequency; /* input frequency */
83 u32 speed_hz;
84 };
85
86 /* zynq qspi priv */
87 struct zynq_qspi_priv {
88 struct zynq_qspi_regs *regs;
89 u8 cs;
90 u8 mode;
91 u8 fifo_depth;
92 u32 freq; /* required frequency */
93 const void *tx_buf;
94 void *rx_buf;
95 unsigned len;
96 int bytes_to_transfer;
97 int bytes_to_receive;
98 unsigned int is_inst;
99 unsigned cs_change:1;
100 };
101
zynq_qspi_of_to_plat(struct udevice * bus)102 static int zynq_qspi_of_to_plat(struct udevice *bus)
103 {
104 struct zynq_qspi_plat *plat = dev_get_plat(bus);
105 const void *blob = gd->fdt_blob;
106 int node = dev_of_offset(bus);
107
108 plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
109 node, "reg");
110
111 return 0;
112 }
113
114 /**
115 * zynq_qspi_init_hw - Initialize the hardware
116 * @priv: Pointer to the zynq_qspi_priv structure
117 *
118 * The default settings of the QSPI controller's configurable parameters on
119 * reset are
120 * - Master mode
121 * - Baud rate divisor is set to 2
122 * - Threshold value for TX FIFO not full interrupt is set to 1
123 * - Flash memory interface mode enabled
124 * - Size of the word to be transferred as 8 bit
125 * This function performs the following actions
126 * - Disable and clear all the interrupts
127 * - Enable manual slave select
128 * - Enable auto start
129 * - Deselect all the chip select lines
130 * - Set the size of the word to be transferred as 32 bit
131 * - Set the little endian mode of TX FIFO and
132 * - Enable the QSPI controller
133 */
zynq_qspi_init_hw(struct zynq_qspi_priv * priv)134 static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
135 {
136 struct zynq_qspi_regs *regs = priv->regs;
137 u32 confr;
138
139 /* Disable QSPI */
140 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
141
142 /* Disable Interrupts */
143 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
144
145 /* Clear the TX and RX threshold reg */
146 writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
147 writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
148
149 /* Clear the RX FIFO */
150 while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
151 readl(®s->drxr);
152
153 /* Clear Interrupts */
154 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
155
156 /* Manual slave select and Auto start */
157 confr = readl(®s->cr);
158 confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
159 confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
160 ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
161 ZYNQ_QSPI_CR_MSTREN_MASK;
162 writel(confr, ®s->cr);
163
164 /* Disable the LQSPI feature */
165 confr = readl(®s->lqspicfg);
166 confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
167 writel(confr, ®s->lqspicfg);
168
169 /* Enable SPI */
170 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
171 }
172
zynq_qspi_probe(struct udevice * bus)173 static int zynq_qspi_probe(struct udevice *bus)
174 {
175 struct zynq_qspi_plat *plat = dev_get_plat(bus);
176 struct zynq_qspi_priv *priv = dev_get_priv(bus);
177 struct clk clk;
178 unsigned long clock;
179 int ret;
180
181 priv->regs = plat->regs;
182 priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
183
184 ret = clk_get_by_name(bus, "ref_clk", &clk);
185 if (ret < 0) {
186 dev_err(bus, "failed to get clock\n");
187 return ret;
188 }
189
190 clock = clk_get_rate(&clk);
191 if (IS_ERR_VALUE(clock)) {
192 dev_err(bus, "failed to get rate\n");
193 return clock;
194 }
195
196 ret = clk_enable(&clk);
197 if (ret) {
198 dev_err(bus, "failed to enable clock\n");
199 return ret;
200 }
201
202 /* init the zynq spi hw */
203 zynq_qspi_init_hw(priv);
204
205 plat->frequency = clock;
206 plat->speed_hz = plat->frequency / 2;
207
208 debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
209
210 return 0;
211 }
212
213 /**
214 * zynq_qspi_read_data - Copy data to RX buffer
215 * @priv: Pointer to the zynq_qspi_priv structure
216 * @data: The 32 bit variable where data is stored
217 * @size: Number of bytes to be copied from data to RX buffer
218 */
zynq_qspi_read_data(struct zynq_qspi_priv * priv,u32 data,u8 size)219 static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
220 {
221 u8 byte3;
222
223 debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
224 data, (unsigned)(priv->rx_buf), size);
225
226 if (priv->rx_buf) {
227 switch (size) {
228 case 1:
229 *((u8 *)priv->rx_buf) = data;
230 priv->rx_buf += 1;
231 break;
232 case 2:
233 *((u16 *)priv->rx_buf) = data;
234 priv->rx_buf += 2;
235 break;
236 case 3:
237 *((u16 *)priv->rx_buf) = data;
238 priv->rx_buf += 2;
239 byte3 = (u8)(data >> 16);
240 *((u8 *)priv->rx_buf) = byte3;
241 priv->rx_buf += 1;
242 break;
243 case 4:
244 /* Can not assume word aligned buffer */
245 memcpy(priv->rx_buf, &data, size);
246 priv->rx_buf += 4;
247 break;
248 default:
249 /* This will never execute */
250 break;
251 }
252 }
253 priv->bytes_to_receive -= size;
254 if (priv->bytes_to_receive < 0)
255 priv->bytes_to_receive = 0;
256 }
257
258 /**
259 * zynq_qspi_write_data - Copy data from TX buffer
260 * @priv: Pointer to the zynq_qspi_priv structure
261 * @data: Pointer to the 32 bit variable where data is to be copied
262 * @size: Number of bytes to be copied from TX buffer to data
263 */
zynq_qspi_write_data(struct zynq_qspi_priv * priv,u32 * data,u8 size)264 static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
265 u32 *data, u8 size)
266 {
267 if (priv->tx_buf) {
268 switch (size) {
269 case 1:
270 *data = *((u8 *)priv->tx_buf);
271 priv->tx_buf += 1;
272 *data |= 0xFFFFFF00;
273 break;
274 case 2:
275 *data = *((u16 *)priv->tx_buf);
276 priv->tx_buf += 2;
277 *data |= 0xFFFF0000;
278 break;
279 case 3:
280 *data = *((u16 *)priv->tx_buf);
281 priv->tx_buf += 2;
282 *data |= (*((u8 *)priv->tx_buf) << 16);
283 priv->tx_buf += 1;
284 *data |= 0xFF000000;
285 break;
286 case 4:
287 /* Can not assume word aligned buffer */
288 memcpy(data, priv->tx_buf, size);
289 priv->tx_buf += 4;
290 break;
291 default:
292 /* This will never execute */
293 break;
294 }
295 } else {
296 *data = 0;
297 }
298
299 debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
300 *data, (u32)priv->tx_buf, size);
301
302 priv->bytes_to_transfer -= size;
303 if (priv->bytes_to_transfer < 0)
304 priv->bytes_to_transfer = 0;
305 }
306
307 /**
308 * zynq_qspi_chipselect - Select or deselect the chip select line
309 * @priv: Pointer to the zynq_qspi_priv structure
310 * @is_on: Select(1) or deselect (0) the chip select line
311 */
zynq_qspi_chipselect(struct zynq_qspi_priv * priv,int is_on)312 static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
313 {
314 u32 confr;
315 struct zynq_qspi_regs *regs = priv->regs;
316
317 confr = readl(®s->cr);
318
319 if (is_on) {
320 /* Select the slave */
321 confr &= ~ZYNQ_QSPI_CR_SS_MASK;
322 confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
323 ZYNQ_QSPI_CR_SS_MASK;
324 } else
325 /* Deselect the slave */
326 confr |= ZYNQ_QSPI_CR_SS_MASK;
327
328 writel(confr, ®s->cr);
329 }
330
331 /**
332 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
333 * @priv: Pointer to the zynq_qspi_priv structure
334 * @size: Number of bytes to be copied to fifo
335 */
zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv * priv,u32 size)336 static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
337 {
338 u32 data = 0;
339 u32 fifocount = 0;
340 unsigned len, offset;
341 struct zynq_qspi_regs *regs = priv->regs;
342 static const unsigned offsets[4] = {
343 ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
344 ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
345
346 while ((fifocount < size) &&
347 (priv->bytes_to_transfer > 0)) {
348 if (priv->bytes_to_transfer >= 4) {
349 if (priv->tx_buf) {
350 memcpy(&data, priv->tx_buf, 4);
351 priv->tx_buf += 4;
352 } else {
353 data = 0;
354 }
355 writel(data, ®s->txd0r);
356 priv->bytes_to_transfer -= 4;
357 fifocount++;
358 } else {
359 /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
360 if (!(readl(®s->isr)
361 & ZYNQ_QSPI_IXR_TXOW_MASK) &&
362 !priv->rx_buf)
363 return;
364 len = priv->bytes_to_transfer;
365 zynq_qspi_write_data(priv, &data, len);
366 offset = (priv->rx_buf) ? offsets[0] : offsets[len];
367 writel(data, ®s->cr + (offset / 4));
368 }
369 }
370 }
371
372 /**
373 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
374 * @priv: Pointer to the zynq_qspi structure
375 *
376 * This function handles TX empty and Mode Fault interrupts only.
377 * On TX empty interrupt this function reads the received data from RX FIFO and
378 * fills the TX FIFO if there is any data remaining to be transferred.
379 * On Mode Fault interrupt this function indicates that transfer is completed,
380 * the SPI subsystem will identify the error as the remaining bytes to be
381 * transferred is non-zero.
382 *
383 * returns: 0 for poll timeout
384 * 1 transfer operation complete
385 */
zynq_qspi_irq_poll(struct zynq_qspi_priv * priv)386 static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
387 {
388 struct zynq_qspi_regs *regs = priv->regs;
389 u32 rxindex = 0;
390 u32 rxcount;
391 u32 status, timeout;
392
393 /* Poll until any of the interrupt status bits are set */
394 timeout = get_timer(0);
395 do {
396 status = readl(®s->isr);
397 } while ((status == 0) &&
398 (get_timer(timeout) < ZYNQ_QSPI_WAIT));
399
400 if (status == 0) {
401 printf("zynq_qspi_irq_poll: Timeout!\n");
402 return -ETIMEDOUT;
403 }
404
405 writel(status, ®s->isr);
406
407 /* Disable all interrupts */
408 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
409 if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
410 (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
411 /*
412 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
413 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
414 * is empty
415 */
416 rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
417 rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
418 while ((rxindex < rxcount) &&
419 (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
420 /* Read out the data from the RX FIFO */
421 u32 data;
422 data = readl(®s->drxr);
423
424 if (priv->bytes_to_receive >= 4) {
425 if (priv->rx_buf) {
426 memcpy(priv->rx_buf, &data, 4);
427 priv->rx_buf += 4;
428 }
429 priv->bytes_to_receive -= 4;
430 } else {
431 zynq_qspi_read_data(priv, data,
432 priv->bytes_to_receive);
433 }
434 rxindex++;
435 }
436
437 if (priv->bytes_to_transfer) {
438 /* There is more data to send */
439 zynq_qspi_fill_tx_fifo(priv,
440 ZYNQ_QSPI_RXFIFO_THRESHOLD);
441
442 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
443 } else {
444 /*
445 * If transfer and receive is completed then only send
446 * complete signal
447 */
448 if (!priv->bytes_to_receive) {
449 /* return operation complete */
450 writel(ZYNQ_QSPI_IXR_ALL_MASK,
451 ®s->idr);
452 return 1;
453 }
454 }
455 }
456
457 return 0;
458 }
459
460 /**
461 * zynq_qspi_start_transfer - Initiates the QSPI transfer
462 * @priv: Pointer to the zynq_qspi_priv structure
463 *
464 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
465 * transfer to be completed.
466 *
467 * returns: Number of bytes transferred in the last transfer
468 */
zynq_qspi_start_transfer(struct zynq_qspi_priv * priv)469 static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
470 {
471 u32 data = 0;
472 struct zynq_qspi_regs *regs = priv->regs;
473
474 debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
475 (u32)priv, (u32)priv, priv->len);
476
477 priv->bytes_to_transfer = priv->len;
478 priv->bytes_to_receive = priv->len;
479
480 if (priv->len < 4)
481 zynq_qspi_fill_tx_fifo(priv, priv->len);
482 else
483 zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
484
485 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
486
487 /* wait for completion */
488 do {
489 data = zynq_qspi_irq_poll(priv);
490 } while (data == 0);
491
492 return (priv->len) - (priv->bytes_to_transfer);
493 }
494
zynq_qspi_transfer(struct zynq_qspi_priv * priv)495 static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
496 {
497 unsigned cs_change = 1;
498 int status = 0;
499
500 while (1) {
501 /* Select the chip if required */
502 if (cs_change)
503 zynq_qspi_chipselect(priv, 1);
504
505 cs_change = priv->cs_change;
506
507 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
508 status = -1;
509 break;
510 }
511
512 /* Request the transfer */
513 if (priv->len) {
514 status = zynq_qspi_start_transfer(priv);
515 priv->is_inst = 0;
516 }
517
518 if (status != priv->len) {
519 if (status > 0)
520 status = -EMSGSIZE;
521 debug("zynq_qspi_transfer:%d len:%d\n",
522 status, priv->len);
523 break;
524 }
525 status = 0;
526
527 if (cs_change)
528 /* Deselect the chip */
529 zynq_qspi_chipselect(priv, 0);
530
531 break;
532 }
533
534 return status;
535 }
536
zynq_qspi_claim_bus(struct udevice * dev)537 static int zynq_qspi_claim_bus(struct udevice *dev)
538 {
539 struct udevice *bus = dev->parent;
540 struct zynq_qspi_priv *priv = dev_get_priv(bus);
541 struct zynq_qspi_regs *regs = priv->regs;
542
543 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
544
545 return 0;
546 }
547
zynq_qspi_release_bus(struct udevice * dev)548 static int zynq_qspi_release_bus(struct udevice *dev)
549 {
550 struct udevice *bus = dev->parent;
551 struct zynq_qspi_priv *priv = dev_get_priv(bus);
552 struct zynq_qspi_regs *regs = priv->regs;
553
554 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
555
556 return 0;
557 }
558
zynq_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)559 static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
560 const void *dout, void *din, unsigned long flags)
561 {
562 struct udevice *bus = dev->parent;
563 struct zynq_qspi_priv *priv = dev_get_priv(bus);
564 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
565
566 priv->cs = slave_plat->cs;
567 priv->tx_buf = dout;
568 priv->rx_buf = din;
569 priv->len = bitlen / 8;
570
571 debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
572 dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags);
573
574 /*
575 * Festering sore.
576 * Assume that the beginning of a transfer with bits to
577 * transmit must contain a device command.
578 */
579 if (dout && flags & SPI_XFER_BEGIN)
580 priv->is_inst = 1;
581 else
582 priv->is_inst = 0;
583
584 if (flags & SPI_XFER_END)
585 priv->cs_change = 1;
586 else
587 priv->cs_change = 0;
588
589 zynq_qspi_transfer(priv);
590
591 return 0;
592 }
593
zynq_qspi_set_speed(struct udevice * bus,uint speed)594 static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
595 {
596 struct zynq_qspi_plat *plat = dev_get_plat(bus);
597 struct zynq_qspi_priv *priv = dev_get_priv(bus);
598 struct zynq_qspi_regs *regs = priv->regs;
599 uint32_t confr;
600 u8 baud_rate_val = 0;
601
602 if (speed > plat->frequency)
603 speed = plat->frequency;
604
605 /* Set the clock frequency */
606 confr = readl(®s->cr);
607 if (speed == 0) {
608 /* Set baudrate x8, if the freq is 0 */
609 baud_rate_val = 0x2;
610 } else if (plat->speed_hz != speed) {
611 while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
612 ((plat->frequency /
613 (2 << baud_rate_val)) > speed))
614 baud_rate_val++;
615
616 plat->speed_hz = speed / (2 << baud_rate_val);
617 }
618 confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
619 confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
620
621 writel(confr, ®s->cr);
622 priv->freq = speed;
623
624 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
625
626 return 0;
627 }
628
zynq_qspi_set_mode(struct udevice * bus,uint mode)629 static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
630 {
631 struct zynq_qspi_priv *priv = dev_get_priv(bus);
632 struct zynq_qspi_regs *regs = priv->regs;
633 uint32_t confr;
634
635 /* Set the SPI Clock phase and polarities */
636 confr = readl(®s->cr);
637 confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
638
639 if (mode & SPI_CPHA)
640 confr |= ZYNQ_QSPI_CR_CPHA_MASK;
641 if (mode & SPI_CPOL)
642 confr |= ZYNQ_QSPI_CR_CPOL_MASK;
643
644 writel(confr, ®s->cr);
645 priv->mode = mode;
646
647 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
648
649 return 0;
650 }
651
652 static const struct dm_spi_ops zynq_qspi_ops = {
653 .claim_bus = zynq_qspi_claim_bus,
654 .release_bus = zynq_qspi_release_bus,
655 .xfer = zynq_qspi_xfer,
656 .set_speed = zynq_qspi_set_speed,
657 .set_mode = zynq_qspi_set_mode,
658 };
659
660 static const struct udevice_id zynq_qspi_ids[] = {
661 { .compatible = "xlnx,zynq-qspi-1.0" },
662 { }
663 };
664
665 U_BOOT_DRIVER(zynq_qspi) = {
666 .name = "zynq_qspi",
667 .id = UCLASS_SPI,
668 .of_match = zynq_qspi_ids,
669 .ops = &zynq_qspi_ops,
670 .of_to_plat = zynq_qspi_of_to_plat,
671 .plat_auto = sizeof(struct zynq_qspi_plat),
672 .priv_auto = sizeof(struct zynq_qspi_priv),
673 .probe = zynq_qspi_probe,
674 };
675