1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved 4 */ 5 6 #ifndef __STPMIC1_H__ 7 #define __STPMIC1_H__ 8 9 #include <drivers/stm32_i2c.h> 10 #include <util.h> 11 12 #define TURN_ON_REG 0x1U 13 #define TURN_OFF_REG 0x2U 14 #define ICC_LDO_TURN_OFF_REG 0x3U 15 #define ICC_BUCK_TURN_OFF_REG 0x4U 16 #define RESET_STATUS_REG 0x5U 17 #define VERSION_STATUS_REG 0x6U 18 #define MAIN_CONTROL_REG 0x10U 19 #define PADS_PULL_REG 0x11U 20 #define BUCK_PULL_DOWN_REG 0x12U 21 #define LDO14_PULL_DOWN_REG 0x13U 22 #define LDO56_PULL_DOWN_REG 0x14U 23 #define VIN_CONTROL_REG 0x15U 24 #define PONKEY_TIMER_REG 0x16U 25 #define MASK_RANK_BUCK_REG 0x17U 26 #define MASK_RESET_BUCK_REG 0x18U 27 #define MASK_RANK_LDO_REG 0x19U 28 #define MASK_RESET_LDO_REG 0x1AU 29 #define WATCHDOG_CONTROL_REG 0x1BU 30 #define WATCHDOG_TIMER_REG 0x1CU 31 #define BUCK_ICC_TURNOFF_REG 0x1DU 32 #define LDO_ICC_TURNOFF_REG 0x1EU 33 #define BUCK_APM_CONTROL_REG 0x1FU 34 #define BUCK1_CONTROL_REG 0x20U 35 #define BUCK2_CONTROL_REG 0x21U 36 #define BUCK3_CONTROL_REG 0x22U 37 #define BUCK4_CONTROL_REG 0x23U 38 #define VREF_DDR_CONTROL_REG 0x24U 39 #define LDO1_CONTROL_REG 0x25U 40 #define LDO2_CONTROL_REG 0x26U 41 #define LDO3_CONTROL_REG 0x27U 42 #define LDO4_CONTROL_REG 0x28U 43 #define LDO5_CONTROL_REG 0x29U 44 #define LDO6_CONTROL_REG 0x2AU 45 #define BUCK1_PWRCTRL_REG 0x30U 46 #define BUCK2_PWRCTRL_REG 0x31U 47 #define BUCK3_PWRCTRL_REG 0x32U 48 #define BUCK4_PWRCTRL_REG 0x33U 49 #define VREF_DDR_PWRCTRL_REG 0x34U 50 #define LDO1_PWRCTRL_REG 0x35U 51 #define LDO2_PWRCTRL_REG 0x36U 52 #define LDO3_PWRCTRL_REG 0x37U 53 #define LDO4_PWRCTRL_REG 0x38U 54 #define LDO5_PWRCTRL_REG 0x39U 55 #define LDO6_PWRCTRL_REG 0x3AU 56 #define FREQUENCY_SPREADING_REG 0x3BU 57 #define USB_CONTROL_REG 0x40U 58 #define ITLATCH1_REG 0x50U 59 #define ITLATCH2_REG 0x51U 60 #define ITLATCH3_REG 0x52U 61 #define ITLATCH4_REG 0x53U 62 #define ITSETLATCH1_REG 0x60U 63 #define ITSETLATCH2_REG 0x61U 64 #define ITSETLATCH3_REG 0x62U 65 #define ITSETLATCH4_REG 0x63U 66 #define ITCLEARLATCH1_REG 0x70U 67 #define ITCLEARLATCH2_REG 0x71U 68 #define ITCLEARLATCH3_REG 0x72U 69 #define ITCLEARLATCH4_REG 0x73U 70 #define ITMASK1_REG 0x80U 71 #define ITMASK2_REG 0x81U 72 #define ITMASK3_REG 0x82U 73 #define ITMASK4_REG 0x83U 74 #define ITSETMASK1_REG 0x90U 75 #define ITSETMASK2_REG 0x91U 76 #define ITSETMASK3_REG 0x92U 77 #define ITSETMASK4_REG 0x93U 78 #define ITCLEARMASK1_REG 0xA0U 79 #define ITCLEARMASK2_REG 0xA1U 80 #define ITCLEARMASK3_REG 0xA2U 81 #define ITCLEARMASK4_REG 0xA3U 82 #define ITSOURCE1_REG 0xB0U 83 #define ITSOURCE2_REG 0xB1U 84 #define ITSOURCE3_REG 0xB2U 85 #define ITSOURCE4_REG 0xB3U 86 87 /* Registers masks */ 88 #define LDO_VOLTAGE_MASK GENMASK_32(6, 2) 89 #define BUCK_VOLTAGE_MASK GENMASK_32(7, 2) 90 #define LDO_BUCK_VOLTAGE_SHIFT 2 91 #define LDO_BUCK_ENABLE_POS 0 92 #define LDO_BUCK_ENABLE_MASK BIT(LDO_BUCK_ENABLE_POS) 93 #define LDO_BUCK_HPLP_POS 1 94 #define LDO_BUCK_RANK_MASK BIT(0) 95 #define LDO_BUCK_RESET_MASK BIT(0) 96 #define LDO_BUCK_PULL_DOWN_MASK GENMASK_32(1, 0) 97 98 /* Pull down register */ 99 #define BUCK1_PULL_DOWN_SHIFT 0 100 #define BUCK2_PULL_DOWN_SHIFT 2 101 #define BUCK3_PULL_DOWN_SHIFT 4 102 #define BUCK4_PULL_DOWN_SHIFT 6 103 #define VREF_DDR_PULL_DOWN_SHIFT 4 104 105 /* Buck Mask reset register */ 106 #define BUCK1_MASK_RESET_SHIFT 0 107 #define BUCK2_MASK_RESET_SHIFT 1 108 #define BUCK3_MASK_RESET_SHIFT 2 109 #define BUCK4_MASK_RESET_SHIFT 3 110 111 /* LDO Mask reset register */ 112 #define LDO1_MASK_RESET_SHIFT 0 113 #define LDO2_MASK_RESET_SHIFT 1 114 #define LDO3_MASK_RESET_SHIFT 2 115 #define LDO4_MASK_RESET_SHIFT 3 116 #define LDO5_MASK_RESET_SHIFT 4 117 #define LDO6_MASK_RESET_SHIFT 5 118 #define VREF_DDR_MASK_RESET_SHIFT 6 119 120 /* Main PMIC Control Register (MAIN_CONTROL_REG) */ 121 #define ICC_EVENT_ENABLED BIT(4) 122 #define PWRCTRL_POLARITY_HIGH BIT(3) 123 #define PWRCTRL_PIN_VALID BIT(2) 124 #define RESTART_REQUEST_ENABLED BIT(1) 125 #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0) 126 127 /* Main PMIC PADS Control Register (PADS_PULL_REG) */ 128 #define WAKEUP_DETECTOR_DISABLED BIT(4) 129 #define PWRCTRL_PD_ACTIVE BIT(3) 130 #define PWRCTRL_PU_ACTIVE BIT(2) 131 #define WAKEUP_PD_ACTIVE BIT(1) 132 #define PONKEY_PU_ACTIVE BIT(0) 133 134 /* Main PMIC VINLOW Control Register (VIN_CONTROL_REGC DMSC) */ 135 #define SWIN_DETECTOR_ENABLED BIT(7) 136 #define SWOUT_DETECTOR_ENABLED BIT(6) 137 #define VINLOW_HYST_MASK GENMASK_32(5, 4) 138 #define VINLOW_HYST_SHIFT 4 139 #define VINLOW_THRESHOLD_MASK GENMASK_32(3, 1) 140 #define VINLOW_THRESHOLD_SHIFT 1 141 #define VINLOW_ENABLED BIT(0) 142 #define VINLOW_CTRL_REG_MASK GENMASK_32(7, 0) 143 144 /* USB Control Register */ 145 #define BOOST_OVP_DISABLED_POS 7 146 #define VBUS_OTG_DETECTION_DISABLED_POS 6 147 #define OCP_LIMIT_HIGH_POS 3 148 #define SWIN_SWOUT_ENABLED_POS 2 149 #define USBSW_OTG_SWITCH_ENABLED_POS 1 150 #define BOOST_ENABLED_POS 0 151 152 /* 153 * Bind SPMIC1 device driver with a specific I2C bus instance 154 * @i2c_handle: target I2C instance to use 155 * @i2c_addr: I2C address of the STPMIC1 device 156 */ 157 void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr); 158 159 /* Read STPMIC1 device version information */ 160 int stpmic1_get_version(unsigned long *version); 161 162 /* Read STPMIC1 device internal registers content */ 163 void stpmic1_dump_regulators(void); 164 165 /* Enable power control in STPMIC1 device */ 166 int stpmic1_powerctrl_on(void); 167 168 /* Disable STPMIC1 device */ 169 int stpmic1_switch_off(void); 170 171 /* Read/write/update STPMIC1 device internal register */ 172 int stpmic1_register_read(uint8_t register_id, uint8_t *value); 173 int stpmic1_register_write(uint8_t register_id, uint8_t value); 174 int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask); 175 176 /* API for gating of regulators driven from STPMIC1 device */ 177 bool stpmic1_regulator_is_valid(const char *name); 178 int stpmic1_regulator_enable(const char *name); 179 int stpmic1_regulator_disable(const char *name); 180 bool stpmic1_is_regulator_enabled(const char *name); 181 182 void stpmic1_regulator_levels_mv(const char *name, 183 const uint16_t **levels, 184 size_t *levels_count); 185 186 /* API for voltage cnotrol of regulators driven from STPMIC1 device */ 187 int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts); 188 int stpmic1_regulator_voltage_get(const char *name); 189 int stpmic1_regulator_mask_reset_set(const char *name); 190 191 /* API for low power configuration of regulators driven from STPMIC1 device */ 192 int stpmic1_lp_copy_reg(const char *name); 193 int stpmic1_lp_reg_on_off(const char *name, uint8_t enable); 194 int stpmic1_lp_set_mode(const char *name, uint8_t hplp); 195 int stpmic1_lp_set_voltage(const char *name, uint16_t millivolts); 196 197 /* 198 * Specific API for controlling regulators driven from STPMIC1 device 199 * from unpaged execution context of the STPMIC1 driver. 200 */ 201 202 /* 203 * The STPMIC1 is accessed during low power sequence in unpaged 204 * execution context. To prevent adding an unpaged constraint on 205 * STPMIC1 regulator definitions, conversion tables and device tree 206 * content, the regulators configurations are read from device tree 207 * at boot time and saved in memory for being applied at runtime 208 * without needing pager support. 209 * 210 * There are 2 types of regulator configuration loaded during such 211 * low power and unpaged sequences: boot-on (bo) configuration and 212 * low power (lp) configuration. 213 */ 214 struct stpmic1_bo_cfg { 215 uint8_t ctrl_reg; 216 uint8_t min_value; 217 uint8_t enable_pos; 218 uint8_t mask; 219 uint8_t pd_reg; 220 uint8_t pd_value; 221 uint8_t pd_mask; 222 uint8_t mrst_reg; 223 uint8_t mrst_value; 224 uint8_t mrst_mask; 225 }; 226 227 struct stpmic1_lp_cfg { 228 uint8_t ctrl_reg; 229 uint8_t lp_reg; 230 uint8_t value; 231 uint8_t mask; 232 }; 233 234 int stpmic1_bo_enable_cfg(const char *name, struct stpmic1_bo_cfg *cfg); 235 int stpmic1_bo_enable_unpg(struct stpmic1_bo_cfg *cfg); 236 int stpmic1_bo_voltage_cfg(const char *name, uint16_t min_millivolt, 237 struct stpmic1_bo_cfg *cfg); 238 int stpmic1_bo_voltage_unpg(struct stpmic1_bo_cfg *cfg); 239 240 int stpmic1_bo_pull_down_cfg(const char *name, 241 struct stpmic1_bo_cfg *cfg); 242 int stpmic1_bo_pull_down_unpg(struct stpmic1_bo_cfg *cfg); 243 244 int stpmic1_bo_mask_reset_cfg(const char *name, struct stpmic1_bo_cfg *cfg); 245 int stpmic1_bo_mask_reset_unpg(struct stpmic1_bo_cfg *cfg); 246 247 bool stpmic1_regu_has_lp_cfg(const char *name); 248 int stpmic1_lp_cfg(const char *name, struct stpmic1_lp_cfg *cfg); 249 int stpmic1_lp_load_unpg(struct stpmic1_lp_cfg *cfg); 250 int stpmic1_lp_on_off_unpg(struct stpmic1_lp_cfg *cfg, int enable); 251 int stpmic1_lp_mode_unpg(struct stpmic1_lp_cfg *cfg, 252 unsigned int mode); 253 int stpmic1_lp_voltage_cfg(const char *name, uint16_t millivolts, 254 struct stpmic1_lp_cfg *cfg); 255 int stpmic1_lp_voltage_unpg(struct stpmic1_lp_cfg *cfg); 256 257 #endif /*__STPMIC1_H__*/ 258