1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019, Rick Chen <rick@andestech.com>
4 * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
5 *
6 * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
7 * The PLMT block holds memory-mapped mtime register
8 * associated with timer tick.
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <timer.h>
14 #include <asm/io.h>
15 #include <dm/device-internal.h>
16 #include <linux/err.h>
17
18 /* mtime register */
19 #define MTIME_REG(base) ((ulong)(base))
20
andes_plmt_get_count(struct udevice * dev)21 static u64 notrace andes_plmt_get_count(struct udevice *dev)
22 {
23 return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
24 }
25
26 #if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
27 /**
28 * timer_early_get_rate() - Get the timer rate before driver model
29 */
timer_early_get_rate(void)30 unsigned long notrace timer_early_get_rate(void)
31 {
32 return RISCV_MMODE_TIMER_FREQ;
33 }
34
35 /**
36 * timer_early_get_count() - Get the timer count before driver model
37 *
38 */
timer_early_get_count(void)39 u64 notrace timer_early_get_count(void)
40 {
41 return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
42 }
43 #endif
44
45 static const struct timer_ops andes_plmt_ops = {
46 .get_count = andes_plmt_get_count,
47 };
48
andes_plmt_probe(struct udevice * dev)49 static int andes_plmt_probe(struct udevice *dev)
50 {
51 dev_set_priv(dev, dev_read_addr_ptr(dev));
52 if (!dev_get_priv(dev))
53 return -EINVAL;
54
55 return timer_timebase_fallback(dev);
56 }
57
58 static const struct udevice_id andes_plmt_ids[] = {
59 { .compatible = "riscv,plmt0" },
60 { }
61 };
62
63 U_BOOT_DRIVER(andes_plmt) = {
64 .name = "andes_plmt",
65 .id = UCLASS_TIMER,
66 .of_match = andes_plmt_ids,
67 .ops = &andes_plmt_ops,
68 .probe = andes_plmt_probe,
69 .flags = DM_FLAG_PRE_RELOC,
70 };
71