1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ 3 4 #ifndef __MLX5_ESW_QOS_H__ 5 #define __MLX5_ESW_QOS_H__ 6 7 #ifdef CONFIG_MLX5_ESWITCH 8 9 int mlx5_esw_qos_set_vport_min_rate(struct mlx5_eswitch *esw, 10 struct mlx5_vport *evport, 11 u32 min_rate, 12 struct netlink_ext_ack *extack); 13 int mlx5_esw_qos_set_vport_max_rate(struct mlx5_eswitch *esw, 14 struct mlx5_vport *evport, 15 u32 max_rate, 16 struct netlink_ext_ack *extack); 17 void mlx5_esw_qos_create(struct mlx5_eswitch *esw); 18 void mlx5_esw_qos_destroy(struct mlx5_eswitch *esw); 19 int mlx5_esw_qos_vport_enable(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 20 u32 max_rate, u32 bw_share); 21 void mlx5_esw_qos_vport_disable(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 22 23 int mlx5_esw_devlink_rate_leaf_tx_share_set(struct devlink_rate *rate_leaf, void *priv, 24 u64 tx_share, struct netlink_ext_ack *extack); 25 int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, void *priv, 26 u64 tx_max, struct netlink_ext_ack *extack); 27 int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void *priv, 28 u64 tx_share, struct netlink_ext_ack *extack); 29 int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, void *priv, 30 u64 tx_max, struct netlink_ext_ack *extack); 31 int mlx5_esw_devlink_rate_node_new(struct devlink_rate *rate_node, void **priv, 32 struct netlink_ext_ack *extack); 33 int mlx5_esw_devlink_rate_node_del(struct devlink_rate *rate_node, void *priv, 34 struct netlink_ext_ack *extack); 35 int mlx5_esw_devlink_rate_parent_set(struct devlink_rate *devlink_rate, 36 struct devlink_rate *parent, 37 void *priv, void *parent_priv, 38 struct netlink_ext_ack *extack); 39 #endif 40 41 #endif 42